Transformerless Quasi-Z-Source Inverter to Reduce Leakage Current for Single-Phase Grid-Tied Applications

Abstract

The conventional single-phase quasi-Z-source (QZS) inverter has a high leakage current as it is connected to the grid. To address this problem, this paper proposes a transformerless QZS inverter, which can reduce the leakage current for single-phase grid-tied applications. The proposed inverter effectively alleviates the leakage current problem by removing high-frequency components for the common-mode voltage. The operation principle of the proposed inverter is described together with its control strategy. A control scheme is presented for regulating the DC-link voltage and the grid current. A 1.0 kW prototype inverter was designed and tested to verify the performance of the proposed inverter. Silicon carbide (SiC) power devices were applied to the proposed inverter to increase the power efficiency. The experimental results showed that the proposed inverter achieved high performance for leakage current reduction and power efficiency improvement.

1. Introduction

Quasi-Z-source (QZS) inverters have been widely used for grid-tied applications, due to their advantages over the traditional voltage-source inverters (VSIs) using a DC-DC converter [1,2,3,4,5,6,7]. Figure 1 shows the circuit diagram of the QZS inverter for single-phase grid-tied applications [2,3,4]. It has a QZS circuit (L₁, L₂, C₁, C₂, D₁) and a full-bridge inverter (S₁, S₂, S₃, S₄, L₃, L₄). As it is connected to the grid v_g without an isolation transformer, a leakage current i_p flows through the parasitic capacitance C_p between the inverter and the grid [5]. This leakage current originated from the common-mode voltage v_p, which changes rapidly as the inverter operates with high switching frequency [6]. Due to shoot-through states, the common-mode voltage in the QZS inverter can be higher than that in the conventional VSIs [7]. This leads to a higher leakage current, which decreases the power efficiency of the inverter.

A simple way to reduce the leakage current is to use bipolar pulse-width modulation (PWM) [8]. Power switches are diagonally operated when bipolar PWM is adopted. The common-mode voltage requires only a grid frequency component, yielding a low leakage current. However, as the voltage v_AB has two levels V_PN and −V_PN, the output filter inductors L₃ and L₄ should have high current ripples and high core losses. Despite its low leakage current characteristic, a QZS inverter with bipolar PWM is not suitable for grid-tied applications because of its reduced power efficiency.

Another method is to use a decoupling circuit to disconnect the inverter from the grid [9,10,11,12,13,14,15]. The decoupling circuit technique has been described for single-phase transformerless inverter applications in [9]. Many advanced transformerless inverters have been developed for voltage source inverters, such as the H5 inverter [10], the highly efficient and reliable inverter concept (HERIC) inverter [11], and the H6 inverter [12]. Many efforts have also been made to develop transformerless inverters by applying decoupling circuits to the current source inverters [16,17]. To date, however, only a few studies [13,14,15] have been reported that apply decoupling circuits to ZS inverters. In [13], a symmetric ZS HERIC inverter was proposed. It uses an additional two power switches for maintaining the common-mode voltage constant. In [14,15], a QZS HERIC inverter was suggested. It uses an additional two power switches and two power diodes for clamping the common-mode voltage. The inverters in [13,14,15] commonly have three distinct switching states, namely powering, freewheeling, and shoot-through states. During powering states, the inverter delivers the DC power into the grid. During shoot-through states, the inverter is decoupled from the grid by turning on all power switches simultaneously in full-bridge inverter legs. After every powering state and shoot-through state, freewheeling states are necessary. During freewheeling states, the grid current circulates through extra power switches, which operate with the grid frequency. However, the previous inverters [13,14,15] have drawbacks such as (1) they still use the bipolar PWM for power switches in full-bridge inverter legs; and (2) they always need freewheeling states for every powering state and shoot-through state. These drawbacks increase the number of switching times for the power switches, causing high switching power losses.

To address the above-mentioned drawbacks, this paper proposes a transformerless QZS inverter, which can effectively reduce the leakage current for single-phase grid-tied applications. Figure 2 shows the circuit diagram of the proposed inverter. The idea behind the proposed inverter was to relate two high-frequency switching legs (S₁, S₂ and S₃, S₄) with the grid using a bidirectional switch (S₅, S₆) and two inductors (L₃, L₄). The bidirectional switch operates with the grid frequency, providing a current path for clamping the common-mode voltage v_p to the neutral and the grid voltage v_g, for positive and negative grid cycles, respectively. The leakage current i_p can be reduced due to the absence of high-frequency components for v_p. Shoot-through states are implemented by turning on two power switches simultaneously in only one switching leg. This leads to low switching power losses compared to the previous inverters in [13,14,15]. A control scheme is suggested for regulating the DC-link voltage V_PN and the grid current i_g. Since the peak DC-link voltage is controlled by a voltage controller, the grid current control can be directly implemented to regulate i_g. In this paper, Section 2 describes the operation principle and the control strategy of the proposed inverter. Section 3 presents the experimental results for a 1.0 kW prototype inverter. Silicon carbide (SiC) power devices were applied to the proposed inverter to increase the power efficiency. Section 4 ends the paper by presenting the conclusion.

2. Proposed Inverter

2.1. Operation Principle

Figure 2 shows a circuit diagram of the proposed inverter. It has a QZS circuit (L₁, L₂, C₁, C₂, D₁), a full-bridge inverter (S₁, S₂, S₃, S₄, L₃, L₄), and a bidirectional switch (S₅, S₆). C_p is modeled as the parasitic capacitance between the inverter and the grid voltage v_g. V_in is the DC voltage. V_PN is the DC-link voltage. V_C1 and V_C2 are the capacitor voltages for C₁ and C₂, respectively. i_L1 and i_L2 are the inductor currents for L₁ and L₂, respectively. i_L3 and i_L4 are the inductor currents for L₃ and L₄, respectively. i_L1 ~ i_L4 are assumed to be continuous. C₁ and C₂ are assumed to have large capacitance so that their ripple components are negligible.

The proposed inverter has three switching states, namely the powering, freewheeling, and shoot-through states. For a positive grid cycle, S₆ is always turned on. S₁ and S₂ operate complementarily during the non-shoot-through states. Figure 3 shows the switching circuit diagrams of the proposed inverter for a positive grid cycle. During the powering state in Figure 3a, S₁ is turned on. The DC voltage source supplies electric power to the grid as D₁ is turned on. i_g flows through v_g, S₆, V_PN, S₁, and L₃. The following voltage equation is obtained as in:

$$-V_{PN}+V_{L3}+v_g=0$$

(1)

i_L1 flows through L₁, D_Sb, C₁, and V_in. i_L2 flows through L₂, C₂, and D₁. The following voltage equations are obtained as in:

$$V_{L1}=V_{in}-V_{C1}$$

(2)

$$V_{L2}=-V_{C2}$$

(3)

During the freewheeling state in Figure 3b, S₂ is turned on. The energy stored in L₃ is transferred to v_g. i_g freewheels through v_g, S₆, S₂, and L₃. The following voltage equation is obtained as in:

$$V_{L3}+v_g=0$$

(4)

As L₁ and L₂ are discharged, C₁ and C₂ are charged. During the shoot-through state in Figure 3c, S₁ and S₂ are turned on simultaneously. As D₁ is turned off, L₁ and L₂ are charged. The following voltage equations are obtained as in:

$$V_{L1}=V_{in}+V_{C2}$$

(5)

$$V_{L2}=V_{C1}$$

(6)

i_g flows through v_g, S₆, S₂, and L₃, as in the freewheeling state.

Figure 4 shows the switching circuit diagrams of the proposed inverter for a negative grid cycle. S₅ is always turned on for a negative grid cycle. S₃ and S₄ operate complementarily during the non-shoot-through states. The operation principle for a negative grid cycle is not described here because it can be analogously explained as the operation principle for a positive grid cycle.

As shown in Figure 3, S₆ provides a closed path for C_p to be clamped to the zero voltage for a positive grid cycle. On the other hand, as shown in Figure 4, S₅ provides a closed path for C_p to be clamped to the grid voltage for a negative grid cycle for a negative grid cycle. Then, the common-mode voltage v_p can be represented as in:

$$v_p=\{\begin{array}{ll}0& when{v}_g>0\\ v_g& when{v}_g\le 0.\end{array}$$

(7)

The parasitic capacitance C_p can be free from the high-frequency components for both positive and negative grid cycles. This leads to the low leakage current i_p, regardless of the high-frequency switching operation of the inverter.

Figure 5 shows the signal diagrams for S₁ ~ S₄ when they operate with high switching frequency. S₁ and S₃ are the main control switches for positive and negative grid cycles, respectively. S₁ (S₃) and S₂ (S₄) operate complementarily during the non-shoot-through states, respectively. A simple boost modulation scheme is adopted for generating the shoot-through duty cycles [18]. The shoot-through state is equally distributed into two parts adjacent with the on-time of the main control switch. Shoot-through states are implemented by turning on two power switches simultaneously in only one switching leg, which leads to low switching power losses, compared to the previous inverters in [13,14,15]. Given that the on-time interval for the main control switch is T_ON for one switching period T_S, from (1) and (4), the average voltage V_L3,avg for L₃ over T_S should be zero, respectively, as in:

$$V_{L3,avg}=\frac{(V_{PN}-v_g)T_{ON}-v_g(T_S-T_{ON})}{T_S}=0.$$

(8)

The ratio between T_ON and T_S is obtained as in:

$$\frac{T_{ON}}{T_S}=\frac{v_g}{V_{PN}}=\frac{V_g\left|\sin \omega t\right|}{V_{PN}}$$

(9)

where V_g is the positive peak value of v_g, and ω is the angular frequency of v_g. Given that the time interval during the shoot-through state is T_ST for T_S, the average voltages V_L1,avg and V_L2,avg for L₁ and L₂ over T_S should be zero, respectively, as in:

$$V_{L1,avg}=\frac{(V_{in}+V_{C2})T_{ST}+(V_{in}-V_{C1})(T_S-T_{ST})}{T_S}=0,$$

(10)

$$V_{L2,avg}=\frac{V_{C1}{T}_{ST}-V_{C2}(T_S-T_{ST})}{T_S}=0.$$

(11)

From Equations (10) and (11), we have:

$$V_{C1}-V_{C2}=V_{in}.$$

(12)

From Equation (11), the shoot-through duty cycle D_ST is represented as in:

$$D_{ST}=\frac{T_{ST}}{T_S}=\frac{V_{C2}}{V_{C1}+V_{C2}}.$$

(13)

From Equations (12) and (13), V_C1 and V_C2 are represented as in:

$$V_{C1}=\frac{1-D_{ST}}{1-2D_{ST}}{V}_{in},$$

(14)

$$V_{C2}=\frac{D_{ST}}{1-2D_{ST}}{V}_{in}.$$

(15)

Since V_PN = V_C1 + V_C2, from Equations (14) and (15), we have:

$$\frac{V_{PN}}{V_{in}}=\frac{1}{1-2D_{ST}}.$$

(16)

2.2. Control Strategy

As the proposed inverter steps down the DC-link voltage V_PN to the level of v_g, it regulates the DC-link voltage and controls the grid current i_g. From Equations (3) and (6), the average voltage for L₂ over T_S is obtained with the inductor current deviation ∆i_L2 as in:

$$L_2\frac{\Delta i_{L2}}{T_S}=V_{C1}{D}_{ST}-V_{C2}(1-D_{ST}).$$

(17)

Since V_PN = V_C1 + V_C2, D_ST is derived as in:

$$D_{ST}=\frac{V_{C2}}{V_{PN}}+L_2\frac{\Delta i_{L2}}{V_{PN}{T}_S}.$$

(18)

Suppose that L₁ = L₂ = L_i and i_L1 = i_L2 = i_i, D_ST can be represented as in:

$$D_{ST}=D_{ST,N}+D_{ST,C}$$

(19)

where D_ST,N is the nominal shoot-through duty cycle and D_ST,C is the controlled shoot-through duty cycle as in:

$$D_{ST,N}=\frac{V_{C2}}{V_{PN}^{*}},$$

(20)

$$D_{ST,C}=L_i\frac{\left|\Delta i_i\right|}{V_{PN}^{*}{T}_S}.$$

(21)

V*_PN is the reference value for the peak DC-link voltage. To make the peak DC-link voltage to track its reference V*_PN, the following proportional-integral (PI) voltage control is used as in:

$$D_{ST,C}=k_p(V_{C2}^{*}-V_{C2})+k_i{\displaystyle \int (V_{C2}^{*}-V_{C2})dt}$$

(22)

where k_p and k_i are the PI control gains, respectively. Here, V*_C2 is the reference value for the capacitor voltage V_C2, which is utilized for the DC-link voltage control as V_PN is a pulsating voltage [19]. V*_C2 is given as in:

$$V_{C2}^{*}=\frac{V_{PN}^{*}-V_{in}}{2},$$

(23)

which is obtained from the following relations as V_PN = V_C1 + V_C2 and V_in = V_C1 – V_C2.

For the positive grid cycle, from Equations (1) and (4), the average voltage for L₃ over T_S is obtained with the grid current deviation ∆i_g as in:

$$L_3\frac{\Delta i_g}{T_S}=(V_{PN}-v_g)D_1-v_g(1-D_1)=0$$

(24)

where D₁ is the duty cycle of S₁ without considering D_ST. From Equation (24), D₁ is represented as in:

$$D_1=\frac{v_g}{V_{PN}}+L_3\frac{\Delta i_g}{V_{PN}{T}_S},\hspace{1em}\hspace{1em}when{v}_g>0.$$

(25)

Similarly, the duty cycle D₃ of S₃ without considering D_ST for a negative grid cycle can be represented as in:

$$D_3=-\frac{v_g}{V_{PN}}-L_4\frac{\Delta i_g}{V_{PN}{T}_S},\hspace{1em}\hspace{1em}when{v}_g<0.$$

(26)

Supposed that L₃ = L₄ = L_g, D₁ and D₃ without considering D_ST can be represented as the sinusoidal PWM duty cycle D_SPWM as in:

$$D_{SPWM}=D_{SPWM,N}+D_{SPWM,C}$$

(27)

where D_SPWM,N is the nominal sinusoidal PWM duty cycle and D_SPWM,C is the controlled sinusoidal PWM duty cycle as in:

$$D_{SPWM,N}=\frac{V_g\left|\sin \omega t\right|}{V_{PN}^{*}},$$

(28)

$$D_{SPWM,C}=L_g\frac{\left|\Delta i_g\right|}{V_{PN}^{*}{T}_S}.$$

(29)

To make the grid current to track its reference i*_g, the following proportional (P) current control is used as in:

$$D_{SPWM,C}=k_g(i_g^{*}-\left|i_g\right|)$$

(30)

where k_g is the P control gain. i*_g is given as in:

$$i_g^{*}=I_g^{*}\left|\sin \omega t\right|$$

(31)

where I*_g is the peak magnitude of the current reference. Figure 6 shows the control block diagrams of the proposed inverter. Figure 6a shows the control block diagram for the DC-link voltage control. Figure 6b shows the control block diagram for the grid current control. The phase-locked loop (PLL) control is used for the grid synchronization [20]. The duty cycle for the main control switch can be finally obtained by summing D_SPWM and D_ST.

3. Experimental Results

A 1.0 kW prototype inverter was designed for the proposed inverter for v_g = 60 Hz/220 V_rms. The valve regulated lead-acid batteries were used for the DC voltage V_in, the nominal voltage of which was 250 V. The V*_PN was set to 500 V for D_ST = 0.25. SiC metal-oxide field-effect transistors (MOSFETs) (C2M0080120D, CREE) were used for S_b. A SiC Schottky diode (C4D20120D, CREE) was used for D₁. A digital signal controller (dsPIC30F6015, Microchip) was used for implementing the DC-link voltage and grid current controllers and for generating the duty cycle signals.

The inverter in Figure 1 and the inverter in [15] were designed using insulated gate bipolar transistors (IGBTs). In the conventional inverter in Figure 1, an IGBT (IKW25T120, Infineon) was used for S₁ ~ S₄ with a switching frequency of 10 kHz. A unipolar PWM was adopted for the conventional inverter, due to its better switching performance than a bipolar PWM. In the inverter in [15], IKW25T120 was used for S₁ ~ S₄ with a switching frequency of 10 kHz. IKW25T120 and C4D20120D were used for the extra power switches and extra power diodes, respectively. The proposed inverter used IKW25T120 for S₁ ~ S₄ with a switching frequency of 10 kHz and for S₅ and S₆ with a switching frequency of 60 Hz, respectively. Figure 7 shows a picture of the prototype inverter. The inductance for L₁ ~ L₄ was selected as 1.0 mH. L₃ and L₄ were implemented as a coupled inductor, which simplified the circuit layout. The capacitance for C₁ and C₂ was selected as 560 μF.

Figure 8 shows the experimental waveforms of the conventional inverter in Figure 1 and the proposed inverter, respectively. Figure 8a shows v_g and v_p in the conventional inverter. Figure 8b shows v_g and i_p in the conventional inverter. Figure 8c shows v_g and v_p in the proposed inverter. Figure 8d shows v_g and i_p in the proposed inverter. The leakage current in the proposed inverter was greatly reduced compared to that in the conventional inverter.

Figure 9 shows the experimental waveforms of the proposed inverter. Figure 9a shows the V_in, V_PN, v_g, and i_g. The proposed inverter steps up V_in to V_PN, and controls i_g with high power factor. Figure 9b shows the V_in, V_C2, and V_PN. The peak DC-link voltage was regulated and the grid current was controlled in the proposed inverter. Figure 9c shows the V_in, V_C12, V_C2, and i_L1. Since the proposed inverter operates in the grid-tied mode, a twice grid frequency DC ripple current was observed on the DC input side. If active power decoupling schemes [17] are adopted, the ripple components as well as the reactive component sizes can be reduced.

Figure 10 shows the power efficiency curves of the inverters. Figure 10a shows the power efficiency curves when the IGBTs have been adopted for the power switches. The inverter in Figure 1 achieved an efficiency of 91.7% at the rated power. The inverter in [15] achieved an efficiency of 92.1% at the rated power. The proposed inverter achieved an efficiency of 92.6% at the rated power, obtaining the highest efficiency of 92.9% at 0.6 kW. The proposed inverter obtained higher power efficiency than the previous inverters. The proposed inverter not only improved the power efficiency by reducing the leakage current, but also alleviated switching power losses by reducing the number of switching times for power switches. Figure 10b shows the power efficiency curves when the SiC MOSFETs were adopted for the power switches. It is observed that the power efficiency was improved when the SiC MOSFETS were used for the power switches. The inverter in Figure 1 achieved an efficiency of 93.6% at the rated power. The inverter in [15] achieved an efficiency of 94.0% at the rated power. The proposed inverter achieved an efficiency of 94.7% at the rated power, obtaining the highest efficiency of 95.1% at 0.6 kW. Regardless of the types of power switches, the proposed inverter achieved higher power efficiency than previous inverters.

4. Discussion

4.1. Power Loss Comparison

A unipolar PWM was used for both the conventional inverter in Figure 1 and the proposed inverter. In both inverters, S₁ and S₂ (S₃ and S₄) had one turn-on switching loss and one turn-off switching loss during one switching period, respectively, for the positive (negative) grid cycle. Both inverters had two turn-on switching losses and two turn-off switching losses during one switching period. The number of switching times was identical during one switching period, as one of the switching legs operated at grid frequency. The number of conducted switching devices was also identical during one switching period. Then, both inverters had identical switching and conduction losses. Even though they had identical power losses for the switching devices, the conventional inverter in Figure 1 had a high leakage current, while the proposed inverter had a low leakage current. This is the reason why the proposed inverter achieved higher power efficiency than the conventional inverter in Figure 1.

Figure 11a shows the circuit diagram of the previous inverter in [15]. Figure 11b shows its switching signal diagrams for S₁ ~ S₄ during one switching period. In the previous inverter in [15], S₅ (S₆) was always turned on for the positive (negative) grid cycle. S₁ and S₄ (S₂ and S₃) operated together during one switching period. In order to generate the shoot-through switching states, S₁, S₂, S₃, and S₄ had to be simultaneously turned on during one switching period, as shown in Figure 11b. S₁ and S₄ (S₂ and S₃) had two turn-on switching losses and two turn-off switching losses during one switching period, respectively, for the positive (negative) grid cycle. Meanwhile, S₂ and S₃ (S₁ and S₄) had one turn-on switching loss and one turn-off switching loss during one switching period, respectively, for the positive (negative) grid cycle. Then, the previous inverter in [15] had six turn-on switching losses and six turn-off switching losses during one switching period. Thus, the previous inverter in [15] had higher switching losses than the proposed inverter, even though the additional switches (S₅, S₆) in both inverters operated at the grid frequency. In addition, the conduction losses of the previous inverter in [15] were higher than the proposed inverter because of the use of two additional diodes. This is the reason why the proposed inverter achieved higher power efficiency than the previous inverter in [15]. This is also the reason why the previous inverter in [15] achieved lower power efficiency than the conventional inverter in Figure 1. As the power level decreased, the switching power losses became significant, which reduced the light load efficiency.

4.2. Topological Investigation

The decoupling circuits for reducing the leakage current can be divided into two concepts, namely AC-based and DC-based decoupling techniques [9]. The proposed inverter can be derived from the AC-based decoupling technique as the bidirectional switch (S₅, S₆) and two inductors (L₃, L₄) provide the current path for clamping the common-mode voltage to the neutral and the grid voltage for the positive and negative grid cycles, respectively. The DC-link voltage between the QZS circuit and the full-bridge inverter pulsates as the shoot-through state is generated. Thus, deriving a DC-based decoupling technique will be quite achievable for the ZS-based inverters. Along with the present state of the art and trend of decoupling circuit techniques [9], the embedded-switch inverter (ESI) [21] and zero-voltage state rectifier (ZVR) [22] concepts can be candidate solutions for extending leakage current reduction schemes to three-phase inverter applications. Furthermore, multilevel inverters using cascaded topologies [23,24,25] can be advanced approaches for QZS inverters to improve the output power quality.

5. Conclusions

A high-efficiency transformerless QZS inverter was proposed for single-phase grid-tied applications. The proposed inverter effectively reduced the leakage current, providing high power efficiency. A bidirectional switch operating with the grid frequency was used, which provided a current path to remove high-frequency components for the common-mode voltage. Switching power losses were also alleviated by reducing the number of switching times for power switches. The operation principle of the proposed inverter was described. A control scheme was suggested for regulating the DC-link voltage and the grid current. A 1.0 kW prototype inverter was designed and tested to evaluate the performance of the proposed inverter. SiC MOSFETs were applied to the proposed inverter to increase the power efficiency. The experimental results showed that the proposed inverter achieved high performance in terms of leakage current reduction and power efficiency improvement.