Analysis of the Voltage-Dependent Plasticity in Organic Neuromorphic Devices

Abstract

The bias-dependent signal transmission of flexible synaptic transistors is investigated. The novel neuromorphic devices are fabricated on a thin and transparent plastic sheet, incorporating a high-performance organic semiconductor, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, into the active channel. Upon spike emulation at different synaptic voltages, the short-term plasticity feature of the devices is substantially modulated. By adopting an iterative model for the synaptic output currents, key physical parameters associated with the charge carrier dynamics are estimated. The correlative extraction approach is found to yield the close fits to the experimental results, and the systematic evolution of the timing constants is rationalized.

1. Introduction

Neuromorphic engineering is an emerging technological area, which aims at mimicking the biological functionalities of neurons, synapses, or a whole brain by various electronic materials and devices [1,2,3,4,5,6]. Recently, the use of organic electronics in neuromorphic systems has gained tremendous attention, thanks to its capacity to expand the technological scope of such systems by creating unconventional interfaces such as direct neuroprotheses and robotic sensory bridges [7,8,9,10]. There are many possible routes to organic-based neuromorphic architecture, including electrochemical [11,12], memristive [13], and field-effect approaches [14,15,16]. Among them, organic field-effect transistor (OFET)-based synaptic devices are a particularly promising element, considering the possibility of a fully solid-state, flexible neuromorphic chip that leverages the versatility of OFETs in constructing various circuit building blocks [17,18,19,20]. Despite the rapidly growing technological viability of OFET synapses, there is still a lack of understanding on fundamental phenomena prevailing at the single-device level, which acts as a current bottleneck for the development of organic-based complex neuromorphic hardware systems. We recognize this issue, and present here a detailed analysis of one specific neuromorphic functionality, namely the short-term plasticity (STP) in flexible OFET synaptic devices. By combining experimental measurements and numerical modeling, systematic understanding of the voltage-dependent transmission behavior at the synaptic junction is obtained. By increasing the input-spike voltage magnitude, slowing down of both charging and discharging is observed, as the floating carrier reservoir turns electrostatically populated. The detailed analysis from this study builds a solid foundation for advanced models and the realization of flexible organic neuromorphic circuitries.

2. Experimental Methods

The organic synaptic transistors based on a floating-gate OFET architecture were fabricated with dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) semiconductor (Figure 1a), according to the bottom-gate, top-contact structure depicted in Figure 1b. A key to this device is the utilization of the ultra-thin, flat Al nanolayer, which is surface-oxidized to form an Al/AlOx stack [16]. The device fabrication processes are summarized as follows. The gate substrate is prepared as a flexible and transparent polyethylene terephthalate (PET) sheet, which has a predeposited conducting indium tin oxide (ITO) film (130 nm) (surface resistivity 60 Ω/sq, Sigma-Aldrich). The ITO surface was planarized by a 40-nm thick poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS, Clevios™, Heraeus) buffer layer to reduce the gate leakage. Then, insulating poly(methyl methacrylate) (PMMA, M.W. = 120,000, Sigma-Aldrich) was spin-coated from a toluene solution to serve as a blocking dielectric (410 nm). The Al functional layer with a nominal thickness of 3 nm was thermally evaporated and exposed to ambient air for oxidation. DNTT (sublimed grade, 99%, Sigma-Aldrich) was vacuum-evaporated for a hole-transporting molecular channel (50 nm). Finally, the Au source/drain electrodes (30 nm) were evaporated through a shadow mask.

For emulating the STP behavior, we used the quasi-two-terminal electrical configuration shown in Figure 1c. Here, the gate and drain electrodes were externally wired and connected to a common computer controlled source-measure unit (Keithely 2400). The synaptic voltage (V_syn) pulses were generated by using a LabVIEW code, for them to have a specific number of sharp spike-like electrical stimulation stages with varying frequencies. The synaptic current (I_syn) was measured as a function of time as the output signal.

3. Results and Discussion

Materials characterization including atomic force microscopy (AFM) and transmission electron microscopy (TEM) as well as the basic transistor characterization such as transfer, output, mobility measurements has been reported in our previous paper [16]. Here, we introduce a numerical model that is applied to analyze the experimental STP. It is based on the functional model initially developed for nanoparticle organic memory field-effect transistors (NOMFET), by Bichler and co-workers [21]. In this study, we modify the notations and introduce the correlative parametrization approach, so that it can better describe our synaptic devices. Let’s first recapitulate the physical meaning of such a model, by drawing a parallel between a biological synapse and a synaptic transistor channel. As shown in Figure 1d, the communication through a biological synapse is signaled by the action potential of the presynaptic neuron, which in turn activates the release of neurotransmitters toward the postsynaptic neuron. Part of these chemical messengers are eventually pulled back into the presynaptic neuron through re-uptake. Therefore, a specific time-domain pattern of neural signals conditions the dynamic variation of synaptic strength. Similarly, in our OFETs, holes accumulated at the DNTT channel serve as electronic signal carriers. Since the V_syn is bound to drain and gate, part of the transporting holes are trapped into the Al floating gate when a spike arrives. These trapped carriers can be easily detrapped into the channel, which is a key feature of our transistors with an ultra-thin tunnel oxide. Therefore, the STP behavior can be emulated by adjusting the input V_syn pulses.

For the square-type input V_syn waveform consisting of varying frequency and duty cycles, the direct relationship between the nth synaptic current I_n and the (n + 1)th one I_n+1 can be iteratively established. As an intermediate, the current I_n+ is the value at the falling edge of each synaptic spike and is dictated by how much the floating gate is charged during that pulse, which is written as

$$I_{n+}=I_n\exp \left(-\frac{W}{{\tau }_t}\right)+I_0\left[\exp \left(-\frac{\Delta E_F}{kT}\right)\left\{1-\exp \left(-\frac{W}{{\tau }_t}\right)\right\}\right]$$

(1)

where W is the activation pulse width, τ_t is the trapping time constant, I₀ is the initial current, ΔE_F is the semiconductor Fermi-level shift at the fully charged state of the floating gate, k is the Boltzmann constant, and T is the absolute temperature. Between two pulses (while V_syn = 0 V), the carriers now leave the floating gate by natural detrapping, partially recovering the channel current, expressed as

$$I_{n+1}=I_{n+}\exp \left(-\frac{T_p-W}{{\tau }_d}\right)+I_0\left[1-\exp \left(-\frac{T_p-W}{{\tau }_d}\right)\right]$$

(2)

where T_p is the pulse time period and τ_d is the detrapping time constant. Merging Equations (1) and (2) gives the final model

$$\begin{gathered} I_{n+1}=I_n\exp \left(-\frac{W}{{\tau }_t}\right)\exp \left(-\frac{T_p-W}{{\tau }_d}\right)+I_0\left[\exp \left(-\frac{\Delta E_F}{kT}\right)\left\{1-\exp \left(-\frac{W}{{\tau }_t}\right)\right\}\exp \left(-\frac{T_p-W}{{\tau }_d}\right)+ \\ \left\{1-\exp \left(-\frac{T_p-W}{{\tau }_d}\right)\right\}\right]. \end{gathered}$$

(3)

To gain insights into the voltage-dependent signal transmission properties, we experimentally recorded the STP behavior of the same transistor, at four different magnitudes of V_syn as −4, −6, −8, and −10 V. The composition of the input signals (i.e., the frequency sequence and the number of spikes at each stage) was kept the same except for the voltage magnitude. Our test input waveforms consisted of six stages with the frequencies of 5, 1, 0.2, 2, 4, and 0.5 Hz. These frequencies determine the value of T_p, and W was fixed as 20 ms. Therefore, the remaining task in modeling is to fit the experimental I_syn data by determining four parameters, which are I₀, ΔE_F, τ_t, and τ_d. Instead of setting all these fitting parameters free, we employed a correlative extraction approach for more physically reliable results. The main idea is that the asymptotic final current I₀exp(−ΔE_F/kT) should reflect the same amount of trapped carriers, and therefore have a quadratic dependence on the V_syn magnitude considering the forced saturation-regime transistor operation. To systematically apply this method, we first extracted the four fitting parameters from the data set at the lowest value of V_syn = −4 V. Then, we calculated the I₀exp(−ΔE_F/kT) value for V_syn = −4 V, and then let this base asymptotic limit quadratically increase with increasing V_syn. Therefore, for the three other data sets (V_syn = −6, −8, and −10 V), the apparent initial I₀ value together with the prefixed I₀exp(−ΔE_F/kT) value allowed for the unambiguous calculation of ΔE_F for each V_syn.

Figure 2a shows that I₀ monotonously increases in magnitude with increasing V_syn values, which is accounted for by the channel current flow enhanced by both gate (free carrier density) and drain voltages (lateral electric field) [18]. Interestingly, the ΔE_F follows a similar trend before experiencing a small drop at a high V_syn. This evidences that gate-induced trapping (decreasing the free carriers) and gate-enhanced hole accumulation act together to set the right balance for the Fermi level approachable at the fully charged state [22]. The inset of Figure 2a confirms that the magnitude of V_syn and the asymptotic synaptic current follows the quadratic dependence, evidenced by slope 2 on this log-log representation.

Having determined the values of I₀ and ΔE_F, the two timing constants were estimated by performing global fitting to the experimental results. Figure 2b shows that despite the ultra-thin nature of our AlOx favoring spontaneous relaxation, the detrapping time constant τ_d is greater than the trapping counterpart τ_t at all voltage biases considered. Another important finding here is that the magnitude of V_syn can substantially influence the ratio between τ_d and τ_t values, implying a direct impact on the STP modulation.

Figure 3 shows the direct comparison between the experimental STP results and the model currents reproduced by inserting the parameters in Figure 2 into Equation (3). Similar STP behaviors have been observed in several field-effect synaptic transistors [14,15,16]. In brief, we can notice that even with the constant magnitude of V_syn, the produced I_syn quite significantly changes its magnitude responding to the spiking frequency. At a high V_syn frequency, a monotonous decrease in current is monitored because the negative gate pulse traps holes from the channel into the floating gate. When this frequency decreases, the amount of holes escaping the traps (per time) can exceed that of the holes being trapped into the floating gate, so that the I_syn gradually recovers its strength. In Figure 3, the model-calculated values are in a broad agreement with the measurements, and showed a similar trend in STP modulation. With increasing V_syn, the overall magnitude of output current I_syn went up, and it was necessary to introduce different timing parameters at each test voltage to fully explain the voltage-dependent transmission behavior. As shown in Figure 2b, the evolution of τ_d was more dramatic than that of τ_t, which is reflected in Figure 3 as the suppressed potentiation at V_syn = −8 or −10 V. This result also indicates that further optimization in synaptic voltages or structural engineering of nanoscale trapping media [23] may enable a switchable short-term and long-term neuromorphic behavior out of the same base architecture.

4. Conclusions

We have reported on a combined experimental and theoretical analysis of the voltage-dependent synaptic plasticity in flexible OFETs. An iterative model was used in conjunction with the correlative extraction to understand the STP characteristics at different voltages. It was found that the applied voltage has a significant impact on I₀, ΔE_F, and timing constants. Among them, the τ_d experienced a particularly remarkable rise, turning the device into a practically depressing synapse at large voltages. At the same time, we have noticed the limited applicability of the model, evidenced by fitting errors. This indicates that an advanced model will need to be developed based on the physical characteristics of each complex trapping mechanism, which may for instance include the multiple time constants with a direct functional link to the materials and operational conditions.