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J. Sens. Actuator Netw. 2013, 2(3), 631-652; doi:10.3390/jsan2030631

Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research

* ,
Institute for Software Integrated Systems, Vanderbilt University, 1025 16th Ave S, Nashville, TN 37212, USA
* Authors to whom correspondence should be addressed.
Received: 10 July 2013 / Revised: 20 August 2013 / Accepted: 27 August 2013 / Published: 9 September 2013
(This article belongs to the Special Issue Feature Papers)
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Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on the medium access control (MAC) layer and above. SRAM field-programmable gate array (FPGA)-based software-defined radios (SDR), on the other hand, provide a flexible architecture to experiment with any and all layers of the radio stack, but usually require desktop computers and draw high currents that prohibit mobile or longer-term outdoor deployments. To address these issues, we have developed a modular flash FPGA-based wireless research platform, called Marmote SDR, that has computational resources comparable to those of SRAM FPGA-based radio platforms, but at a reduced power consumption, with duty cycling support. We discuss the design decisions underlying Marmote SDR and evaluate its power consumption. Furthermore, we present and evaluate an asynchronous and multiple access communication protocol specifically designed for data-gathering wireless sensor networks.
Keywords: flash FPGA; WSN; SDR; PHY layer; DS-CDMA flash FPGA; WSN; SDR; PHY layer; DS-CDMA
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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Szilvási, S.; Babják, B.; Völgyesi, P.; Lédeczi, Á. Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research. J. Sens. Actuator Netw. 2013, 2, 631-652.

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