Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model

Abstract

One major concern of channel engineering in nanotransistors is the coupling of the conduction channel to the source/drain contacts. In a number of previous publications, we have developed a semiempirical quantum model in quantitative agreement with three series of experimental transistors. On the basis of this model, an overlap parameter $0\le C\le 1$ can be defined as a criterion for the quality of the contact-to-channel coupling: A high level of C means good matching between the wave functions in the source/drain and in the conduction channel associated with a low contact-to-channel reflection. We show that a high level of C leads to a high saturation current in the ON-state and a large slope of the transfer characteristic in the OFF-state. Furthermore, relevant for future device miniaturization, we analyze the contribution of the tunneling current to the total drain current. It is seen for a device with a gate length of 26 nm that for all gate voltages, the share of the tunneling current becomes small for small drain voltages. With increasing drain voltage, the contribution of the tunneling current grows considerably showing Fowler–Nordheim oscillations. In the ON-state, the classically allowed current remains dominant for large drain voltages. In the OFF-state, the tunneling current becomes dominant.

1. Introduction

At this time, transistors in integrated circuits are projected with channel lengths below 10 nm. At this length scale quantum transport plays a substantial role. Microscopic modeling of the drain current of such a nanotransistor thus requires the evaluation of the wave functions of the charge carriers [1,2,3,4,5,6,7,8,9,10] or the evaluation of Greens functions [11,12,13,14,15,16,17,18,19,20,21,22]. Because of the considerable effort for such microscopic calculations, there is a need for more flexible compact modeling like BSIM (Berkeley Short-channel IGFET Model) [23,24,25,26,27], the virtual source model [28,29,30,31,32,33] or wave function-based models [1,5,7,34,35,36,37,38,39,40]. In this paper, we focus on the latter approach in which the microscopic wave functions of the charge carriers are approximated in a compact form.

A microscopic calculation of the wave functions of the charge carriers requires the time-consuming numerical solution of the Schrödinger equation in at least two relevant dimensions (along the conduction channel and perpendicular to the semiconductor-insulator interface). To move towards a compact quantum model, an essential step is therefore the formulation of a one-dimensional effective model, which can be constructed and evaluated quickly. In our approach, we start from a complete three-dimensional microscopic R-matrix-description of a nanotransistor in the Landauer–Büttiker formalism and reduce it systematically to a one-dimensional effective model [5,37]. Here, one assumes a separable form of the scattering potential in the conduction channel with only a single relevant mode (‘single level approximation’). The resulting one-dimensional effective model is microscopically justified for the OFF-state and for the threshold voltage region, which are essential for complementary logic. Assuming furthermore a piecewise linear potential, the effective model can be formulated in a scale-invariant form using only five dimensionless transistor parameters [38]. These transistor parameters describe the height of the source-drain barrier, the device temperature, the channel length and the applied drain voltage. The fifth parameter, the overlap parameter $0\le C\le 1$, is particularly relevant for channel engineering because it gives a criterion for the quality of the coupling between the contacts and the conduction channel: a high level of C means good matching properties (low reflection) between the wave functions in the source/drain contact and in the conduction channel. In a model with equal transverse confinement in the contacts and in the conduction channel as in [35,36], one has $C=1$. Finally, assuming the applicability of our theoretical results in the piecewise linear potential approximation, the described five transistor parameters are adjusted to the experimental traces [39,40]. Excellent agreement between theory and experimental traces is found for three series of transistors (‘A-, B- and C-transistors’) fabricated and measured by Globalfoundries with gate lengths of 30 nm, 26 nm and 22 nm.

This paper contains a detailed study of the overlap parameter of the C-transistors. We relate the results for the overlap parameter to the sub-threshold slope and to the saturation current in the experimental transfer characteristics. Here, we also compare the present results for the C-transistors with previous results for the A-transistors with a much poorer overlap parameter and a poorer saturation current. It is found that a large overlap parameter is associated with a large sub-threshold slope in the transfer characteristic and a high saturation current in the ON-state. The magnitude of the saturation current turns out to be strongly influenced by the magnitude of a characteristic jump in the overlap parameter occurring at the threshold voltage. This jump is particularly pronounced for short channel devices and for low temperatures. It is probably a non-linear phenomenon resulting from the Coulomb interaction, which determines the potential in the shallow junction extensions between the contacts and conduction channel. At low temperatures, thermal random motion is reduced and screening is improved, and one expects a smooth transition between the contacts and the conduction channel.

With future device miniaturization in mind, we analyze the contribution of the tunneling current to the total drain current. Taking the C-transistor with the intermediate gate length of 26 nm as an example it is seen that for all gate voltages, the share of the tunneling current becomes small for small drain voltages. With increasing drain voltage, the contribution of the tunneling current grows considerably showing Fowler–Nordheim oscillations. In the ON-state, the classically-allowed current remains barely dominant for large drain voltages. In contrast, in the OFF-state, the drain current becomes nearly entirely a tunneling current for large drain voltages.

2. Semiempirical Transistor Model

Our semiempirical model is reviewed in detail in the Appendix A. This section contains only an account of the central equations in a nut-shell.

2.1. Scale-Invariant Drain Current

In [39,40], a formula for the drain current of a nanotransistor per width J is derived as given by:

$$j=\frac{J}{J_0}=C{\int }_0^{\infty }dϵ\left[s(ϵ-m)-s(ϵ-m+v_D)\right]T^{ef}\left(ϵ\right)\equiv j(v_0,u,C,v_D,l).$$

(1)

Here, one has five dimensionless transistor parameters $v_0=V_0/E_F$ (effective barrier height), $u=k_{B}T/E_F$ (normalized device temperature), C (wave function overlap; for the microscopic interpretation, see Equation (A19)), $l=L/\lambda$ (effective channel length) and $v_D=e{U}_D/E_F$ (normalized drain voltage), where L is the channel length of the transistor, $\lambda =\hslash /\sqrt{2m^{*}{E}_F}$ is the scaling length and $U_D$ is the applied drain voltage. For the microcopic interpretation of the energy $ϵ$ see Equation (A26). While the three transistor parameters $v_0,u$ and C result from a fit of the experimental output characteristics (see the next section), the remaining quantities can be calculated assuming that the Fermi energy in the source contact $E_F$ and the chemical potential $\mu \left(T\right)$ are known from the doping concentration: modeling the contacts as a homogeneous three-dimensional electron gas appropriate for a wide transistor with a large junction depth, one has:

$$m=\frac{\mu }{E_F}=u{X}_{1/2}\left(\frac{4}{3\sqrt{\pi }}{u}^{-3/2}\right)$$

(2)

where $X_{1/2}$ is the inverse function of the Fermi–Dirac integral of order $1/2$. Furthermore, we adopt from [37,38] values for the current normalization constant $J_0=2e{N}_v^{ch}{E}_F/\left(h\lambda \right)\sim$ 50 mA/$\mathsf{\mu }$m with the valley degeneracy $N_v^{ch}$ in the conduction channel, for the characteristic length $\lambda \sim$ 1 nm and for the Fermi energy in the source $E_F=0.35$ eV. This way, for the investigated devices, the effective channel length l is given by the channel length in nanometers. The supply function is calculated from:

$$s\left(\alpha \right)=\sqrt{\frac{u}{4\pi }}{F}_{-\frac{1}{2}}\left(-\frac{\alpha }{u}\right),$$

(3)

where $F_{-1/2}$ is the Fermi–Dirac integral of order $-1/2$. The supply function gives the number of occupied scattering states per energy interval and per channel width. The effective current transmission $T^{ef}$ is calculated from the scattering solutions of a normalized one-dimensional effective Schrödinger equation in the scaled x-coordinate $\widehat{x}=x/L\to x$:

$$\left[-\frac{1}{l^2}\frac{d^2}{d{x}^2}+v^{ef}\left(x\right)-ϵ\right]{\psi }^{ef}\left(x\right)=0$$

(4)

with the effective potential given by:

$$v^{ef}\left(x\right)=\left\{\begin{array}{cc}0\hfill & \mathrm{for}x<0\hfill \\ v_0-v_{D}x\hfill & \mathrm{for}0\le x\le 1\hfill \\ -v_D\hfill & \mathrm{for}x\ge 1.\hfill \end{array}\right.$$

(5)

For the microscopic interpretation of the effective potential, see Equation (A22). The effective potential of height $v_0$ is plotted in Figure 1b. The source-incident scattering solution of (4) takes the asymptotic form:

$${\psi }^{ef}(x<0)=e^{i{k}_{1}x}+r^{ef}{e}^{-i{k}_{1}x}\mathrm{with}{k}_1=l\sqrt{ϵ}$$

(6)

and:

$${\psi }^{ef}(x>1)=t^{ef}{e}^{i{k}_{2}x}\mathrm{with}{k}_2=l\sqrt{ϵ+v_D}.$$

(7)

It now holds that $T^{ef}=k_2{\left|t^{ef}\right|}^2{k}_1^{-1}$ (see Equation (A25)).

From the effective Schrödinger Equation (4), it is clear that contributions to $T^{ef}$ with $ϵ<v_0$ are due to source-drain tunneling. Typical forms for the effective current transmission and the supply function in (3) are given in Figure 8, and they are illustrated in Figure 1c: As is well known, $T^{ef}$ approaches zero for $ϵ\ll v_0$ and approaches unity for $ϵ\gg v_0$. Since at room temperature, the thermal energy $k_{B}T$ is considerably smaller than $E_F$, the supply function decays quickly for $ϵ>m$. As a consequence, in the OFF-state with $v_0>m\sim 1$, which is illustrated in Figure 1, there is only a small overlap between the two factors $s(ϵ-m)-s(ϵ-m-v_D)$ and $T^{ef}\left(ϵ\right)$ in (1), and the total drain current becomes small.

2.2. Calibration of the System Parameters

It is seen from Equation (1) that the normalized current per width j can be calculated from five transistor parameters $v_0,u,C,v_D$ and l. From the measurements of J, $U_D$ and L, one obtains directly the three parameters j, $v_D$ and l from the values for $J_0$, $E_F$ and $\lambda$, which are adopted from [37,38]. To find the three missing transistor parameters $v_0$, u and C in Equation (1), we assume the existence of three calibration functions $v_0\left(U_G\right)$, $u\left(U_G\right)$ and $C\left(U_G\right)$ depending only on the experimental gate voltage $U_G$. Through these calibration functions, the drain current becomes dependent on $U_G$. The calibration functions result from the minimization of the root mean square deviation:

$$\Delta J_{rms}\left(U_G\right)=\sqrt{\frac{1}{N}\sum _i^N{\left[\frac{J^{exp}(U_D^i,U_G)-J^{th}(U_D^i,v_0,u,C)}{J^{exp}(U_D^i,U_G)}\right]}^2}$$

(8)

at given $U_G$. Here, $J^{exp}(U_D^i,U_G)$ is the experimental current measured at N equidistant drain voltages $U_D^i$. The theoretical current is calculated from (1) as:

$$J^{th}(U_D^i,v_0,u,C)=J_{0}j(v_0,u,C,v_D=q{U}_D^i/E_F,l=L/\lambda ).$$

(9)

The values of the parameters $v_0$, u and C that lead to the minimum of $\Delta J_{rms}\left(U_G\right)$ constitute the calibration functions $v_0\left(U_G\right)$, $u\left(U_G\right)$ and $C\left(U_G\right)$. One obtains the calibrated theoretical current plotted in Figure 2 and Figure 3 as:

$$J^{cal}(U_D,U_G)=J^{th}[v_0\left(U_G\right),u\left(U_G\right),C\left(U_G\right),q{U}_D/E_F,L/\lambda ].$$

(10)

3. The Calibration Functions

3.1. Experimental and Theoretical Output Characteristic

We analyze the experimental and theoretical output characteristics of a series of three n-channel transistors (‘C-transistors’) with gate lengths of $L=22$ nm (C1), $L=26$ nm (C2, identical to B3 in [40]) and $L=30$ nm (C3, identical to B4 in [40]). The characteristics are plotted in Figure 2 and Figure 3 for three environment temperatures $T=233$ K, 298 K and 398 K [41]. In all cases, excellent agreement between experiment and theory is found. The threshold gate voltage for the C-transistors we locate at $U_G^{th}=0.6$ V where the ID-VD traces show a close to linear behavior. As usual, in the ON-state, the drain current grows weaker than linearly with increasing drain voltage showing a negative bending. In contrast, in the OFF-state, the drain current grows faster than exponentially with the drain voltage at small drain voltages and exponentially at larger drain voltages leading to a positive bending. These results for the OFF-state have already been reported in [39,42] for another series of transistors. In agreement with our theoretical results in [38], the slope of the close to linear threshold trace is found to decrease slightly with channel length and to increase slightly with temperature.

The location of $U_G^{th}$ around 0.6 V is confirmed, first by an inspection of the temperature dependence of the drain current and, second, by an inspection of the calibration functions: Above $U_G^{th}$, in the ON-state (see Figure 2), the output characteristics are only weakly temperature dependent [43]. In contrast, below $U_G^{th}$, in the OFF-state (see Figure 3), the drain current increases strongly with increasing temperature, which suggests thermal activation. This contrast is consistent with the metallic characteristics of conduction in the ON-state and its insulator characteristic in the OFF-state.

The inspection of the calibration functions yields: First, above $U_G^{th}$, the barrier height parameter $v_0$ falls below the chemical potential m indicating classically allowed transport without thermal activation, while below, $U_G^{th}$ we have $v_0>m$ (see Figure 4). Second, above $U_G^{th}$, the device temperature parameter u increases strongly with increasing gate voltage (see Figure 4), while below $U_G^{th}$, the device temperature stays around the environment temperature. Third, the overlap parameter C takes a jump at $U_G^{th}$ (see Figure 5).

3.2. The Calibration Functions for Barrier Height and Device Temperature

The calibration functions for the barrier height and for the device temperature of the three C-transistors are shown in Figure 4 for the three environment temperatures. The general structure is the same in all cases and coincides with the one reported in [39,40]: In the OFF-state, for gate voltages below $U_G^{th}$, the barrier height lies above the chemical potential m in the source and drops as a nearly linear function of the gate voltage, $v_0\left(U_G\right)\sim 2-2U_G\left[V\right]$. At $U_G^{th}$, one has $v_0\sim m$, and the conduction channel becomes strongly populated. For gate voltages above $U_G^{th}$, in the ON-state, the drop of $v_0\left(U_G\right)$ is much weaker than in the OFF-state. This we attribute to better screening when the conduction channel is populated. As can be expected, the screening effect is most pronounced in the shortest channel device C1 at low temperatures. Here, the barrier height remains roughly constant in the entire ON-state regime in spite of the increased applied gate voltage. As a further consequence of the changed screening conditions in the ON-state, we adduce the jump in the overlap calibration function C of the transistors at $U_G^{th}$ (see Figure 5), which is by far most pronounced for C1 at low temperatures. In an intuitive physical picture, we explain the reduction of screening at higher temperatures invoking increased random thermal motion: because of Poisson’s equation, screening of an external potential requires a specific adjustment of the electron density. This adjustment is prevented by Pauli’s exclusion principle in small dimensions, on the one hand, and by random thermal motion, on the other.

For all examined transistors and environment temperatures, the device temperature stays close to the environment temperature in the OFF-state due to small ohmic heating. A careful inspection of Figure 4 shows that the device temperature generally increases slightly when increasing the environment temperature. Above the threshold, the drain current sets in, and Ohmic heating leads to rising device temperatures. At $E_F\sim 0.35$ eV, one has at room temperature 298 K the value $k_{B}T/E_F\sim 0.075$. The temperature difference $\Delta T$ = 398 K − 298 K corresponds to $k_B\Delta T/E_F\sim 0.025$.

3.3. The Calibration Function for the Overlap Parameter and Transfer Characteristic

In Figure 5, the calibration function of the overlap parameter (‘overlap function’) is depicted. In all cases, the overlap function is a growing function of the gate voltage showing a jump at $U_G^{th}$, which is most pronounced at low temperatures and short channel lengths. As mentioned, these properties can be explained by improved screening conditions with increasing population of the conduction channel. The fact that C takes values greater than unity above the threshold gate voltage indicates that at least one excited mode at the interface plays a role above the threshold so that the single-level approximation leading to Equation (A19) is not strictly applicable any more. In the screening picture, it can also be explained that in the OFF-state, the overlap functions of all C-transistors at the low temperatures of $T=233$ K and $T=298$ K take very small values and are nearly the same. This is consistent with the expectation that in the OFF-state, the population of the conduction channel is nearly absent at low temperatures (‘no screening limit’). Furthermore, in the OFF-state, for all C-transistors, the overlap parameter is much larger at the high temperature of $T=398$ K. This we attribute to the thermally-activated population of the channel. In contrast, in the ON-state for all C-transistors, the overlap parameter is smaller at the high temperature due to the less pronounced jump in C at the threshold voltage. This we attribute to random thermal motions degrading the screening properties of the strongly populated ‘metallic’ conduction channel.

In Figure 6a, we compare the overlap functions of the three A-transistors Ai, $i=1,2,3$ taken from [39] to the ones of the C-transistors Ci, $i=1,2,3$ at the room-environment temperature. Here, Ai has the same channel length as Ci. In the OFF-state, the temperature parameters of both the A- and the C-transistors are close to room-environment temperature, and the barrier height parameter of both the A- and the C-transistors is given by $v_0\left(U_G\right)\sim 2-2U_G\left[V\right]$. Therefore, in the OFF-state, the essential differences between the A- and the C-transistors lies in the overlap parameter. In Figure 6b, we also include the transfer characteristics of the A- and C-transistors to find relations between features in the overlap function and the transfer characteristics of the devices. It is observed that for small gate voltages the overlap functions of the A- and C-devices are very similar and that the transfer characteristics are close to each other. With increasing gate voltage, the overlap parameters of the C-devices increase while those of the A-devices stay constant. As a consequence, the slope of the transfer characteristics of the C-devices exceeds that of the A-devices leading to a larger drain current of the C-transistors. At the threshold, a strong Coulomb coupling between the contacts and the conduction channel leads to the described jump in the overlap parameter of the C-transistors. In contrast, in the A-devices, the increase in the overlap parameter around the threshold is gradual and not so pronounced. As a consequence, the saturation current in the C-devices is markedly larger than that of the A-devices. The comparison between the A- and the C-transistors therefore indicates that a large overlap factor leads to large slopes of the transfer characteristic in the OFF-state and to large saturation currents in the ON-state. This finding suggests that the overlap factor might serve as a quantitative criterion of a systematic classification of nanotransistors in the future.

4. Tunneling Current

In Figure 7, we plot the classically forbidden tunneling part of the drain current:

$$J^t=C{J}_0{\int }_0^{v_0}dϵ\left[s(ϵ-m)-s(ϵ-m+v_D)\right]T^{ef}\left(ϵ\right)$$

(11)

normalized to the total current in Equation (1) (see the green area in Figure 1c). As can be expected, the share of the tunneling current $J^t$ always decreases with increasing the gate voltage, increases with increasing the drain voltage and decreases with increasing channel length. It is seen that for all gate voltages and channel lengths, the contribution of $J^t$ becomes small for small drain voltages. With increasing drain voltage, the contribution of the tunneling current grows, showing oscillations. These oscillations arise from Fabry–Perot-type resonances in the transmission (see [44] and Figure 8). As can be taken from Figure 2 and Figure 3, the Fabry–Perot-type resonances are averaged out efficiently in the energy integral in (1) to determine the total drain current j at the experimental temperatures. However, due to the abrupt upper limit $v_0$ of the energy integration in (11), the tunneling current is discernibly increased whenever a Fabry–Perot resonance falls below $v_0$ corresponding to the inset of resonant Fowler–Nordheim tunneling (see Figure 3 of [44]). The resulting oscillations in $J^T$ are probably overestimated in the abrupt barrier potential in Equation (5). In the OFF-state, i.e., for the gate voltages below $U_G^{th}$, one finds a rise of $J^t/J_0$ for all transistors up to well above $80\%$ for $V_D\ge 0.5$ V. Above $U_G^{th}$, one finds a weaker rise of $J^t/J_0$ for all transistors, which still ranges between $20\%$ and $50\%$ for $V_D\ge 0.5$ V.

We analyze the strong increase of $J^t/J_0$ with increasing drain voltage in the OFF-state. For this purpose, the constituents of the integrand in (11) are plotted in Figure 8 for a small drain voltage and for a large drain voltage. These constituents are the effective current transmission $T^{ef}$ and the difference of the supply functions in source and drain contact $s(ϵ-m)-s(ϵ-m-v_D)$ (‘supply function difference’), which show the general behavior discussed in Figure 1. Comparing the results for the small drain voltage to the ones at the large drain voltage, one finds: First, the supply function difference is always larger for the large drain voltage, though this difference is small in the range of relevant energies where $T^{ef}$ is finite. Second, and most important, for the large drain voltage, $T^{ef}$ sets in at much smaller energies, so that it is much larger than $T^{ef}$ for the small drain voltage in the range of tunneling-energies below $v_0$. As a consequence of these two findings, the product function is larger and wider for the large drain voltage, yielding a much larger value for $J^t$ in (11).

5. Conclusions for Channel Engineering

The comparison between the A- and C-devices in Figure 6 suggests that the coupling between the contacts and the channel is of great importance for the switching properties of a transistor. One expects that the quality of this coupling sensitively depends on the doping profile in the shallow junction extension. Here, an important factor are the screening properties arising in the doping profile. In the C-transistors, a good contact-to-channel coupling exists leading to a growing population of the conduction channel in the OFF-state when approaching the threshold voltage through thermal excitation. This causes a significant increase of the sub-threshold slope in the transfer characteristic. Moreover, at good channel coupling, a jump in the overlap factor arises at the threshold voltage causing a large saturation current in the ON-state. This jump in the overlap factor is most likely a non-linear phenomenon resembling a metal-insulator transition. Therefore, for the theoretical investigation of an optimal doping profile in the shallow junction extension, a calculation of the Coulomb interaction at least in the Hartree approximation is necessary, which is left to future research.