Performance Analysis of Harmonic-Reduced Modified PUC Multi-Level Inverter Based on an MPC Algorithm

Abstract

Renewable and distributed energy generation includes wind turbines, fuel cells, solar cells, and batteries. These distributed energy sources need special power converters in order to connect them to the grid and make the generated power available for public use. Solar energy is the most readily available energy source; hence, if utilized properly, it can power up both domestic and industrial loads. Solar cells produce DC power, and this should be converted to an AC source with the help of inverters. A multi-level inverter for an application is selected based on a trade-off between cost, complexity, losses, and total harmonic distortion (THD). A packed U-cell (PUC) topology is composed of power switches and voltage sources connected in a series-parallel fashion. This basic unit can be extended to a greater number of output voltage levels. The significance of this design is the reduced use of power switches, gate drivers, protection circuits, and capacitors. The converter presented in this paper is a 31-level topology switched by a variable switching frequency-based model predictive controller that helps in achieving optimal output with reduced harmonics to a great extent. The gate driver circuit is also optimized in terms of power consumption and size complexity. A comparison of the 9-level and the 31-level PUC inverters is carried out to study the impact of the number of levels on the total harmonic distortion. The simulation results depict that the total harmonic distortion (THD) for a nominal modulation index of 0.8 is 11.54% and 3.27% for the 9-level multi-level inverter (MLI) and the 31-level modified packed U-cell multi-level inverter (MPUC-MLI), respectively. The reduction in THD is attributed to the increased number of steps in the output when using the model predictive controller.

1. Introduction

Clean power and renewable energy generation are always evergreen topics of research, and many studies have shown that such energy generation is made possible by distributed small generation units. Some sources of distributed generation include wind turbines, fuel cells, solar cells, and batteries. These distributed energy sources need special power converters in order to connect them to the grid and make the generated power available for public use. Solar energy is the most readily available energy source; hence, if utilized properly, it can power up both domestic and industrial loads. Solar cells produce DC power, and this should be converted to an AC source with the help of inverters. Traditional inverters have some demerits, such as distorted output voltage rich in harmonics, high stress, losses, etc., and this induces the necessity for developing efficient inverters. The designed modified packed U-cell (MPUC) inverter is tested by designing a hardware prototype, and results were produced.

As multi-level power converter topologies have been proven to improve the power quality, reduce harmonic distortion, and, hence, act as efficient power converters, a comprehensive review of the different multi-level converters along with their merits and demerits is detailed in [1]. Contrary to power electronic converters, a simple active filter is proven to be active in reducing harmonics in [2]. A medium voltage multi-level inverter (MLI) [3] is designed for reducing harmonic distortion by reducing the switching frequency. Different industrial-grade multi-level inverters are the topics of discussion in [4], along with the various modulation and control techniques. In [5], a packed-U-cell-based multi-level inverter along with a sinusoidal modulation is proposed. A variety of application areas of power electronic converters, such as transportation, renewable energy production, and industrial drives, are the topics covered in [6]. A cascaded multi-level inverter design was proposed in order to reduce losses due to switching and distortions caused by harmonics [7]. A detailed review of the different PUC-based inverter designs, their operation, outputs, and modeling, along with a comparison with other multi-level converters, is presented in [8].

An H-Bridge inverter of 17 levels designed using flying and floating capacitors is proposed in [9]. A difference in modulation technique is introduced by a model predictive controller for inverter switching proposed in [10]. Similarly, a five-level PUC inverter that uses modulation switching based on a sensor-less voltage control is presented in [11]. An application-specific solution for the case of a solar powered water pump is given in [12]. It details the use of a common (VSI) voltage source inverter controlled by switches for a brushless DC (BLDC) motor load. An efficient controller design is proposed in [13] for industrial multi-level converters. A single phase five-level inverter designed from two T-type bridges is detailed in [14]. In [15], a single DC source with a smaller number of solid-state switches and gate drivers is used in the design of a three-level boost cascaded H-Bridge inverter, whereas a controller with fault tolerance for a cascaded H-Bridge is detailed in [16]. A cascaded H-bridge MLI design for a photo-voltaic (PV) grid with inverted decoupling is proposed in [17]. Detailed reviews of various predictive control techniques for the grid and converter level are presented in [18].

A hybrid PUC architecture with a reduced number of switches that is capable of producing 7- and 15-level outputs is proposed in [19] for high power, low voltage applications. An experimental review of different control configurations of a PUC converter that uses a PI controller and a model predictive controller for five- and seven-level inverters is provided in [20]. A PWM-based switching for a PUC converter and its effectiveness in distributing losses and reducing harmonics, which, in turn, increases the reliability of the converter, is explained in [21]. In [22], a new topology of a seven-level PUC converter with a reduced device count and cost factor is explained, along with relevant results. Switching techniques that use a multiple-carrier-based PWM method are used for a seven-level PUC converter, and its resulting enhancements are explained in [23]. A seven-level PUC converter that uses asymmetrical DC links for producing a reduced harmonic output signal is proposed in [24], along with the results. A frequency-dependent level shifted sinusoidal PWM switched PI controller used for a 15-level PUC is explained in [25].

A comparison of a cascaded hybrid bridge converter and a PUC converter with a varied height modulation is depicted in [26]. A 31-level H-cascaded asymmetrical inverter is designed and verified in [27] with the aim of reducing harmonics. A PI controller switched seven-level PUC converter is studied in [28] and is found to reduce harmonics. Fault analysis of multi-level inverters is the topic of interest in [29], and a machine learning algorithm is used for classification and diagnosis of the fault detected from signal processing. A CNN-LSTM-based switching control of an LC filter converter for a three phase multi-level inverter is the topic of discussion in [30], and it is found that CNN can produce effective switching, whereas LC filters help in reducing harmonics. A hybrid MLI controlled by a damped second order integral controller as applied to solar PV cells is studied in [31], and its efficiency is found. A review of recent optimization techniques following the design and control of MLI is studied in [32]. A sliding mode control along with a finite control-set-based control algorithm for a transformer-less voltage restorer is the topic discussed in [33]. A suitable weight function is used to enhance balancing of the inverter. A zeta converter to regulate output from PV array and a level-shifted switching-based MLI inverter is discussed in [34], and it is found to give promising results for PV array. In [35], a unified power quality controller is proposed, and this model uses an MLI based on ANN and soft computing techniques for mitigating various power quality issues. A switched capacitor MLI to achieve 19-level output is explained in [36], along with its results.

Identification of a faulty switch in an inverter circuit by metering the near field using wavelet packet transform is proposed in [37]. A PUC five-level inverter, which is gated by a finite control set MPC controller, is used for testing the fault identification algorithm. An algorithmic method that uses voltages of capacitors in addition to the cost function, while determining the switching states at each sampling time, is used for controlling various PUC architectures in [38]. An artificial-intelligence-based auto-adjusting cost function optimization for controlling a seven-level PUC inverter is proposed and experimentally verified in [39]. A seven-level PUC inverter for a PV system with maximum power point tracking and a finite set model predictive algorithm is experimentally studied in [40]. A modified five-level PUC inverter is studied in [41], where a finite control-set-based prediction control is used for determining the switching states. PUC capacitor voltage estimates based on a switched observer are used for determining the switching states of an MPC-based seven-level PUC inverter in [42].

As distributed energy generation has started flourishing, the need for efficient power conversion is very rapidly growing; thus, development in the power electronics field is inevitable. Multi-level inverters are a promising solution for effective high-power exchange with low harmonic content and reduced switching losses. Conventional MLIs have many demerits, which include: i) implementation cost; ii) complexity of design with an increase in voltage levels; and iii) the number of solid-state devices increases with voltage levels. As there are difficulties, there are also opportunities for improvement. A lot of research has been carried out in designing efficient multi-level inverters, and one among them is the PUC design, which uses power switches and capacitors to form the basic U-cell unit. Such a design has both the advantages of a cascaded H-Bridge (CHB) and flying capacitors (FC). Figure 1a reveals the components that make up the basic U-cell. It consists of one capacitor that connects two solid-state devices on either side.

As there are a lot of merits to the multi-level inverters, this paper proposes a 31-level MPUC inverter, which is gated in a dynamic manner by a variable switching frequency model predictive controller, which determines the switching states based on a cost function optimization for optimal grid current and capacitor voltages. This switching algorithm is implemented in a PIC microcontroller. The prediction efficiency of the switching algorithm is verified by simulation for 9-level and 31-level PUC inverters. There are multiple algorithmic implementations available in the literature for smaller-level MLIs where the number of switching states is smaller, whereas, in this paper, the cost function optimization has been used for switching a 31-level inverter efficiently. A 31-level design is prototyped, and the hardware results are verified.

2. Materials and Methods

The primary objective of using the multi-level inverters (MLI) is to increase the operating voltage and the current of the converters used. And, MLIs come with the advantages of higher operational voltage than the rated voltage of the components, stepped outputs with lower harmonic content, and reduced dv/dt changes. However, these MLIs come with a huge number of power switches that need to be reduced for optimizing cost and efficiency.

Packed U-cell (PUC) topologies are preferred over the other MLIs because of the reduced number of components used. For example, while considering a 9-level MLI, the components used by different inverter topologies are given in

Table 1. Components used by different inverter topologies.

Inverter topology	Number of power switches	Number of capacitors	Number of dc sources
Manufacturer	Formax Electronics pvt ltd	Asoka Electronics	Generic Electronics
Component Description	15 V, 1 A MOSFET switches	1000uF/100V Electrolytic Capacitor	KBPC1510 15 A 1000 V Bridge Rectifier
Packed U Cell	8	2	1
Cascaded H Bridge	16	0	4
Flying Capacitor	16	36	1

.

A varied number of stage-based MLIs were studied in the literature, ranging from 5-level PUCs in [11,14,37,41], 7-level PUCs in [19,22,23,24,28,39,40,42], 15-level PUCs in [19,25], 19-level PUCs in [36], and a 31-level PUC in [27], each being handled by different control mechanisms. As the number of steps in a PUC increases, the stress on the power switches decreases, as the handling voltage reduces. As the number of steps in the output increases, the total harmonic distortion (THD) tends to reduce. As the optimal function of the MLI is desired, a 31-level PUC inverter was considered for design, and the output quality was compared with a 9-level PUC in this work.

2.1. A 31-Level MPUC Inverter

A 31-level MPUC inverter circuit was designed, and its performance with respect to output voltage and the harmonics produced were analyzed. The proposed modified PUC inverter used five pairs of power electronic switches (S1–S6, S2–S7, S3–S8, S4–S9, and S5–S10) connected across the DC source connected to dc1 and three capacitors (C2, C3, and C4, respectively). Considering dc₁ as a reference, then the other voltage levels are given as:

• dc₂ = 7/15(dc₁);
• dc₃ = 3/15(dc₁);
• dc₄ = 1/15(dc₁).

Figure 2 depicts the MLI design, and

Table 2. Voltage levels of the 31-level MPUC inverter.

±(-dc4)	±(-dc3 + dc4)	±(-dc3)	±(-dc2 + dc3)	±(-dc2 + dc3-dc4)
±(-dc2 + dc4)	±(-dc2)	±(-dc1 + dc2)	±(-dc1 + dc2-dc4)	±(-dc1 + dc2-dc3 + dc4)
±(-dc1 + dc2-dc3)	±(-dc1 + dc3)	±(-dc1 + dc3-dc4)	±(-dc1 + dc4)	±(-dc1) and zero

lists the 31-level voltages’ steps that yield the desired output. The different voltage levels are:

The DC power available from the solar cells has to be converted to a usable form by power converters before being fed to the load or connected to the power grid. Effective conversion of DC to AC power depends on the efficiency of the inverter. Thus, highly efficient and low THD inverter designs are required. Thus, this work detailed an efficient MPUC inverter design verified by simulation and then validated by hardware prototype implementation.

2.2. Modulation Technique

The process of gating the solid-state devices’ ON and OFF in order to convert the input to the desired output form is called modulation. The modulation pulses are generated at different time intervals with different pulse widths based on some algorithm. The effective prediction of these pulses determines the nearness of the generated output to the desired output, and, thus, the modulation strategy plays an important role in the design of any power inverter/converter. In addition, the modulation algorithm should have good voltage quality and it should be simple, low-cost, and of modular design; at the same time, simultaneous switching of voltage levels is be avoided, and switching frequency should be reduced.

There are several modulation techniques used for switching the power devices in an MLI. These include Pulse Width Modulation (PWM) [21,23,25,34], Voltage balancing [11,33], Algorithmic-Controller-based PWM [37,38,40,41,42], and Artificial-Intelligence-based Controller [30,35,39]. In this work, a model predictive control algorithm was used to predict the width and instance of the switching pulses based on a reference sine wave. A model predictive control algorithm was used in this inverter, and its workflow is depicted below in Figure 3.

2.3. Model Predictive Controller

A model predictive controller gives the optimal switching state as the output, which gates the inverter switches. A prediction of the output is made from the present values of the load or the grid current I and the capacitor voltage levels dc₂, dc₃, and dc₄. The cost function is determined from the DC reference voltage input dc₁ and the sine wave generated from the PLL. If the error is minimal between the predicted and desired values, then the output is given, i.e., the switching pulses to trigger the power electronic switches are generated and given to the inverter.

2.4. Model Predictive Controller for 31-Level MPUC Inverter

The capacitor voltages dc₂, dc₃, and dc₄ were at 7/15(dc₁), 3/15(dc₁), and 1/15(dc₁), respectively. The switches (1,6), (2,7), (3,8), (4,9), and (5,10) were switched alternatively by the controller. The relationship between the load current i, the capacitor voltages dc₂, dc₃, and dc₄, and the switching states represented by SWx are given by Equations (1)–(4). A 31-level inverter requires 5 different variables to represent all its switching states (say, sw₁ to sw₅, each carrying a value of 0 or 1). When sw₁ is ‘0’, the switch S6 conducts, and when sw₁ is ‘1’, S1 conducts. The variables that constitute the equations are defined as dc₁, which is the voltage input from source; dc₂, dc₃, and dc₄, which are the capacitor voltages; sw₁ to sw₅, which represent the switching states whose value takes up {1,0} for ON and OFF states, respectively; L, which is the inductance value; i(t), which is the grid or load current; v_g(t), which is the grid voltage; and C₂ to C₄, which are the capacitances:

$${\mathrm{C}}_2\frac{{\mathrm{ddc}}_{2 }\left(\mathrm{t}\right)}{\mathrm{dt}}=\left({\mathrm{sw}}_3-{ \mathrm{sw}}_2\right)\mathrm{i}\left(\mathrm{t}\right)$$

(1)

$${\mathrm{C}}_3\frac{{\mathrm{ddc}}_{3 }\left(\mathrm{t}\right)}{\mathrm{dt}}=\left({\mathrm{sw}}_4-{ \mathrm{sw}}_3\right)\mathrm{i}\left(\mathrm{t}\right)$$

(2)

$${\mathrm{C}}_4\frac{{\mathrm{ddc}}_{4 }\left(\mathrm{t}\right)}{\mathrm{dt}}=\left({\mathrm{sw}}_5-{ \mathrm{sw}}_4\right)\mathrm{i}\left(\mathrm{t}\right)$$

(3)

$$\mathrm{L}\frac{\mathrm{di}\left(\mathrm{t}\right)}{\mathrm{dt}}=\left({\mathrm{sw}}_1-{ \mathrm{sw}}_2\right){\mathrm{dc}}_1\left(\mathrm{t}\right)+\left({\mathrm{sw}}_2-{ \mathrm{sw}}_3\right){\mathrm{dc}}_2\left(\mathrm{t}\right)+\left({\mathrm{sw}}_3-{ \mathrm{sw}}_4\right){\mathrm{dc}}_3\left(\mathrm{t}\right)+\left({\mathrm{sw}}_4-{ \mathrm{sw}}_5\right){\mathrm{dc}}_4\left(\mathrm{t}\right)-{ \mathrm{v}}_{\mathrm{g}}\left(\mathrm{t}\right)$$

(4)

The objective of employing an MPC is to predict the capacitor voltages and the output current in order to switch the PUC inverter accordingly. Here, the term (k + 1) is the representation of the next state; thus, the next state of the voltage levels dc₂, dc₃, and dc₄ in terms of the current ‘i’ and switching states are found by applying the Euler Approximation; they are given by Equations (5)–(8)

$${\mathrm{dc}}_2\left(\mathrm{k}+1\right)={ \mathrm{dc}}_2\left(\mathrm{k}\right)+\frac{{\mathrm{T}}_{\mathrm{s}}}{{\mathrm{c}}_2}\left({\mathrm{sw}}_3-{\mathrm{sw}}_2\right)\mathrm{i}\left(\mathrm{k}\right)$$

(5)

$${\mathrm{dc}}_3\left(\mathrm{k}+1\right)={ \mathrm{dc}}_3\left(\mathrm{k}\right)+\frac{{\mathrm{T}}_{\mathrm{s}}}{{\mathrm{c}}_3}\left({\mathrm{sw}}_4-{\mathrm{sw}}_3\right)\mathrm{i}\left(\mathrm{k}\right)$$

(6)

$${\mathrm{dc}}_4\left(\mathrm{k}+1\right)={ \mathrm{dc}}_4\left(\mathrm{k}\right)+\frac{{\mathrm{T}}_{\mathrm{s}}}{{\mathrm{c}}_4}\left({\mathrm{sw}}_4-{\mathrm{sw}}_3\right)\mathrm{i}\left(\mathrm{k}\right)$$

(7)

$$\mathrm{i}\left(\mathrm{k}+1\right)= \mathrm{i}\left(\mathrm{k}\right)+\frac{{\mathrm{T}}_{\mathrm{s}}}{\mathrm{L}}\left({\mathrm{sw}}_1-{\mathrm{sw}}_2\right){\mathrm{dc}}_1\left(\mathrm{k}\right)+\left({\mathrm{sw}}_2-{\mathrm{sw}}_3\right){\mathrm{dc}}_2\left(\mathrm{k}\right)+\left({\mathrm{sw}}_3-{\mathrm{sw}}_4\right){\mathrm{dc}}_3\left(\mathrm{k}\right)+\left({\mathrm{sw}}_4-{\mathrm{sw}}_5\right){\mathrm{dc}}_4\left(\mathrm{k}\right)-{ \mathrm{V}}_{\mathrm{g}}\left(\mathrm{k}\right)$$

(8)

The maximum allowable error between the actual measurement and the prediction values of different state variables for the model predictive controller is formulated. The maximum state variations are used to obtain the normalized state variables, as in Equations (9)–(12), and the cost function is given by Equation (13).

$$\Delta {\mathrm{dc}}_{2\max }=\frac{2\mathrm{i}}{{\mathrm{C}}_2}{ \mathrm{T}}_{\mathrm{s}}$$

(9)

$$\Delta {\mathrm{dc}}_{3\max }=\frac{2\mathrm{i}}{{\mathrm{C}}_3}{ \mathrm{T}}_{\mathrm{s}}$$

(10)

$$\Delta {\mathrm{dc}}_{4\max }=\frac{2\mathrm{i}}{{\mathrm{C}}_4}{ \mathrm{T}}_{\mathrm{s}}$$

(11)

$$\Delta {\mathrm{i}}_{\max }=\frac{2{\mathrm{dc}}_1}{\mathrm{L}}{ \mathrm{T}}_{\mathrm{s}}$$

(12)

$$\mathrm{g}={ \mathsf{\lambda }}_{\mathrm{v}}\frac{{\mathrm{dc}}_2^{*}-{\mathrm{dc}}_2\left(\mathrm{k}+1\right)}{\Delta {\mathrm{dc}}_{2\max }}+{ \mathsf{\lambda }}_{\mathrm{v}} \frac{{\mathrm{dc}}_3^{*}-{\mathrm{dc}}_3\left(\mathrm{k}+1\right)}{\Delta {\mathrm{dc}}_{3\max }}+{ \mathsf{\lambda }}_{\mathrm{v}}\frac{{\mathrm{dc}}_4^{*}-{\mathrm{dc}}_4\left(\mathrm{k}+1\right)}{\Delta {\mathrm{dc}}_{4\max }}+{\mathsf{\lambda }}_{\mathrm{i}}\frac{{\mathrm{i}}^{*}-\mathrm{i}\left(\mathrm{k}+1\right)}{\Delta {\mathrm{i}}_{\max }}$$

(13)

Once the cost function is minimized, the prediction represented by (k + 1) and the reference values given by (*) will be very close to each other; furthermore, the output is given, i.e., the switching pulses to trigger the power devices are generated and given to the inverter.

3. Results

3.1. Simulation Results

3.1.1. Simulation of 9-Level MLI

The inputs used for the simulation of the nine-level MLI and the corresponding outputs are depicted below. Figure 4a–c represents the input current sources one, two, and three of the nine-level multi-level inverter. The ranges of the different input sources used are: (i) current sources one, two, and three, ranging up to 3.24 Amps; (ii) current source two, ranging up to 3.24 Amps; and (iii) input current source three, which is 3.24 Amps.

3.1.2. Output Voltage and Current

The simulation output of the nine-level MLI is as given below; Figure 5a represents the output voltage of the nine-level MLI, and it is approximately equal to 325 V. Figure 5b represents the output current whose value is 3.24 A. The

Table 3. Input and output of 9-level MPUC inverter.

Input Current (Peak) in Amps			Output (Peak Values)
Source 1	Source 2	Source 3	Voltage in V	Current in I
3.24	3.24	3.24	325	3.24

shows the Input and output values of 9-level MPUC inverter.

3.2. Simulation Result for the Proposed System

3.2.1. Input Sources

The inputs used for the simulation of the 31-level MPUC ML inverter are as given below. Figure 6a–d represents the input current sources one, two, three, and four of the 31-level MPUC MLI. The improvement in level shifting demands additional input sources in the circuit, and their corresponding values are: (i) current source one requires 3.24 A; (ii) input current source two ranges up to 1.5 A; (iii) current source three is approximately 2.3 A; and (iv) input current source four ranges up to 2.8 A. A varied range of input currents aids in providing performance improvement.

3.2.2. Output Voltage and Current

The simulation output of the 31-level MPUC multi-level inverter is as given below in Figure 7a,b. Figure 7a represents the output voltage of the 31-level multi-level inverter, and Figure 7b represents the output current. The 31-level MLI has an output voltage of 325 V with reduced switching loss and harmonic distortion. The overall output current for the 31-level MLI is 3.24 A. The

Table 4. Input and output of 31-level MPUC inverter.

Input Current (Peak) in Amps				Output (Peak Values)
Source 1	Source 2	Source 3	Source 4	Voltage in V	Current in I
3.24	1.5	2.3	2.8	325	3.24

shows the Input and output values of 31-level MPUC inverter.

3.3. Total Harmonic Distortion Study by FFT Analysis

The simulation results of the FFT Analysis of the 31-level packed U-cell multi-level inverter for different modulation indices (say, 1, 0.8, 0.6, and 0.4) are depicted by Figure 8a–d.

Table 5. MI and THD for 9-level and 31-level multi-level inverters.

Si. No.	Modulation Index	9-Level THD%	31-Level THD%
1	0.4	28.51%	6.37%
2	0.6	16.71%	4.31%
3	0.8	11.54%	3.27%
4	1.0	9.36%	2.61%

represents the comparison table of the THD Analysis of the MLI. And, Figure 8e represents the comparison of the THD Analysis chart.

The simulation results reveal the output voltage current, which proves the efficiency of the 31-level MPUC MLI over its 9-level MLI counterpart. The FFT analysis proves that the harmonic distortions of the 31-level MPUC MLI for various modulation indices outperform its 9-level counterpart. The THD for the lowest modulation index of 0.4 for the 31-level MPUC MLI is 6.37%, whereas for the 9-level MLI, it is 28.51%. This proves the efficient harmonic reduction of the proposed design.

3.4. Hardware Results

Considering the simulation results and the FFT analysis, it is found that the designed 31-level MPUC multi-level inverter performs better than the 9-level MLI. As a next step, a hardware prototype for the proposed model is designed, and the various input and output results are obtained. The model predictive control algorithm is implemented on a PIC microcontroller, and the hardware prototype results are obtained. The complete hardware setup of the 31-level MPUC MLI is given in Figure 9. Figure 10a–e shows the switching pulses that trigger that inverter circuit. Figure 11a–d represents the four inputs at the inverter circuit. The output of the inverter is given in Figure 12.

3.4.1. Switching Pulses

The modulation signals given to switches, their switching carried out, and their switching output pulses are observed. There are five switches, and their switching pulses are given by Figure 10a–e.

3.4.2. Input Source Voltage

The DC source voltage is given to the inverter as input after the rectification, several inputs are taken, and the system is operated. Thus, the conversion of source to input voltage is taken with the help of the rectifier circuit.

3.4.3. Multi-Level Inverter Output

Inverters convert the DC input voltage to AC voltage for utilization. The 31-level MPUC multi-level inverter output voltage with level shifts and improved efficiency with a minimum amount of THD is taken out with the help of DSO (Digital storage Oscilloscope), and the output is as shown by Figure 12.

4. Discussion

Solar energy is an abundant source for renewable energy generation. Still, the major limiting factor is the efficiency of the harvesting systems. In order to obtain maximum power from the solar generation units, almost every harvesting system tracks the maximum power point to achieve greater efficiencies. However, due to challenges in tracking, such as losses, oscillatory system behavior, sluggish system response, and low accuracy, the efficiency of the maximum power point tracking system is affected. Reducing the associated harmonics and minimizing oscillatory system responses are the two major areas of research that gain importance when it comes to optimizing distributed solar generation. The drawbacks are mainly related to the efficiency of the solid-state power converters used with the solar power generation unit; thus, efficient gating of these power devices plays a major role in determining the efficiency of the solar power generation system. Different control techniques have been used for this purpose, and the model predictive control method is one of the frequently used techniques due to its advantages. MPC-based switching techniques help improve power quality as they are devoid of filters, which are the major sources that affect the quality of power. Such MPC controllers, in addition to switching inverters, can be used to work along with maximum power point tracking for efficient and quick tracking. Thus, in this paper, a Variable Switching Model Predictive Controller implementation for a 31-level PUC multi-level inverter is presented with the objective of reducing the harmonics and improving power quality control. A model predictive controller is implemented using a PIC controller, and this is capable of providing a faster response under dynamic environmental conditions. Both the simulation and hardware results show a reduction in total harmonic distortion with increased step levels. The FFT analysis reveals that the total harmonic distortion for the lowest modulation index of 0.4 for the 31-level MPUC MLI is 6.37%, whereas for the 9-level MLI, it is 28.51%. Also, for a nominal modulation index of 0.8, the THD level is 11.54% and 3.27% for the 9-level MLI and the 31-level MPUC MLI, respectively. This depicts the reduction in total harmonic distortion achieved by the 31-level MPUC Inverter with model predictive control.

5. Conclusions

The modified multi-level PUC inverter (MPUC) can generate the output waveform in 31 steps, which helps reduce the low harmonic content in the output. Conventional MLIs have many demerits, which include: (i) implementation cost; (ii) complexity of design with increase in voltage levels; and (iii) the number of solid-state devices, which increases with voltage levels. Unlike the other available PUC topology, the proposed 31-level MPUC inverter uses a minimal number of power switches at the same time; therefore, it is capable of producing quality output voltage in terms of harmonic content. Also, the output power is greater, as it sums up the DC bus amplitudes. The efficiency of the system is attributed to the Variable Switching Model Predictive Control algorithm used for the generation of modulating pulses that switch the power devices in the inverter circuit efficiently. The significance of this design resides in the use of a reduced number of solid-state devices, capacitors, and filters; hence, this aids in compact and low-cost installations. The primary merit of using less switching and charging devices is to offer better power quality and reduced distortions. The FFT analysis results reveal that the total harmonic distortion THD is reduced for the 31-level design. This design can be further studied by (i) using different power switches, and (ii) using advanced prediction algorithms for switching inverters.