Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Round 1

Reviewer 1 Report

The paper is well organized and described. The proposed methodology seems to affect positively the process of screening defects in 3D flash memories. The only comment I may have is that it is a niche application so it probably does not meet the interest of a great majority of the scientists of the field.

Reviewer 2 Report

This paper presents a new method for detecting defects in the fabrication of 3D VNAND structures. The topic is very advanced and the article is of high quality. Its structure meets the requirements of scientific publications, the English is good, and there are essentially no typos or spelling mistakes.

The introduction provides an adequate introduction to the subject area and the background to the research. 

Section 2 describes the working principle of NAND flash memories, from 2D structures to 3D structures. The text and figures are excellent, easy to follow and textbook quality.  

Section 3 describes the different types of chanel hole defects in detail, in a very easy to follow manner.

Section 4 describes the new defect inspection method. The presentation is sufficiently detailed.

Section 5 summarises the results of 160 flash chip tests (although 320 chips are mentioned once at the beginning of the paper, in the Introduction section). The results presented are convincing as to the effectiveness of the method. Two comments on this section:
- "in the programming language of Visual C++" 400 => Visual C++ is a development environment and not a programming language.
- "measured wihie varying" 406 => while

Overall, the article is excellent in all aspects and I recommend its publication.