Hardware and Software Co-optimisations for Machine Learning

Dear Colleagues,

Machine learning has emerged as a transformative technology with applications spanning a wide range of fields, including healthcare, finance, autonomous systems, natural language processing, computer vision, and many others. It involves training algorithms on large datasets to recognize patterns, make predictions, and perform complex tasks with increasing levels of accuracy. As the demand for machine learning continues to grow, there is a pressing need to optimise the hardware and software components that support these algorithms.

Hardware and software co-optimisations for machine learning focus on improving the efficiency, performance, and scalability of machine learning systems. This research area aims to develop innovative techniques that enable faster training and inference times, reduce energy consumption, and overcome the limitations of traditional computing resources. By exploring new hardware architectures, software frameworks, and algorithmic optimisations, researchers aim to unlock the full potential of machine learning algorithms and address the challenges posed by increasingly large and complex datasets.

This Special Issue, entitled “Hardware and Software Co-optimisations for Machine Learning”, aims to provide a comprehensive platform for researchers, academics, and industry professionals to disseminate and exchange cutting-edge research and advancements in the field of hardware and software optimisations for machine learning. This Special Issue focuses on the intersection of hardware design, software development, and machine learning algorithms, with the goal of improving the efficiency, performance, and scalability of machine learning systems.

In this Special Issue, original research articles and reviews are welcome. Research areas may include (but not limited to) the following:

1. Hardware Optimisation Techniques:

   - Novel hardware architectures and accelerators for machine learning

   - FPGA (Field-Programmable Gate Array) and ASIC (Application-Specific Integrated Circuit) designs for ML;

   - Hardware-software co-design for ML systems;

   - Memory hierarchy optimisation and data movement reduction techniques;

   - Energy-efficient hardware designs for ML workloads;

   - Specialized processors and hardware architectures for specific ML tasks (e.g., neural network inference, training).

2. Software Optimisation Techniques:

   - Algorithmic optimisations for improved computational efficiency;

   - Parallelisation and concurrency techniques for ML algorithms;

   - Memory management and data locality optimisations;

   - Software frameworks and libraries for efficient machine learning;

   - Integration of software optimisations with hardware accelerators.

3. System-Level Optimisations:

   - System-level optimisations for distributed machine learning;

   - Network and interconnect optimisations for ML clusters;

   - Scalability and performance optimizations for large-scale ML deployments;

   - Resource allocation and scheduling techniques for ML workloads;

   - Performance monitoring, profiling, and debugging tools for ML systems.

I look forward to receiving your contributions.

Dr. Khoa Dang Pham
Guest Editor

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• hardware architecture
• system-level optimisation
• machine learning systems