Influence of Parasitic Parameters on DC–DC Converters and Their Method of Suppression in High Frequency Link 35 kV PV Systems

Abstract

Photovoltaic (PV) power generation has shown a trend towards large-scale medium- or high-voltage integration in recent years. The development of high-frequency link PV systems is necessary for the further improvement of system efficiency and the reduction of system cost. In the system, high-frequency high-step-up ratio LLC converters are one of the most important parts. However, the parasitic parameters of devices lead to a loss of zero-voltage switching (ZVS) in the LLC converter, greatly reducing the efficiency of the system, especially in such a high-frequency application. In this paper, a high-frequency link 35 kV PV system is presented. To suppress the influences of parasitic parameters in the LLC converter in the 35 kV PV system, the influence of parasitic parameters on ZVS is analyzed and expounded. Then, a suppression method is proposed to promote the realization of ZVS. This method adds a saturable inductor on the secondary side to achieve ZVS. The saturable inductor can effectively prevent the parasitic elements of the secondary side from participating in the resonance of the primary side. The experimental results show that this method achieves a higher efficiency than the traditional method by reducing the magnetic inductance.

1. Introduction

Since PV power generation systems can alleviate the energy crisis and reduce environmental pollution, they have found broad application worldwide [1,2,3,4]. Traditional large-scale PV medium-voltage (MVAC) grid-connected systems mostly adopt centralized large-capacity inverters and line frequency transformers because of their simple structure and low installation cost [5,6,7]. The traditional structure of PV systems has achieved high efficiency and low cost. However, there are many problems in traditional systems, including mismatch power losses due to the limitations of single maximum power point tracking (MPPT) [8], magnetic loss and reactive power loss due to the line frequency transformer [9], and a massive consumption of material resources. As a result, the efficiency of traditional systems is difficult to improve any further. Although DC–DC converters can be introduced into the system, as described in [10], and additional power converters will allow each photovoltaic array to operate at its maximum power point (MPP), the remaining problems still cannot be solved, due to the use of the centralized inverter and line frequency transformer. With the development of wide band gap devices, high frequency isolation is possible, and PV systems with higher efficiency and power density are expected. To this end, many improved architectures have been proposed. In [11,12], a modular multilevel converter (MMC) was used to replace the line frequency transformer and central inverter in MVAC grid-connected systems. The MMC was able to easily achieve a medium voltage level, but it could not provide galvanic isolation of the photovoltaic array, and was not found to be suitable for PV systems. In [13], an isolated quasi-z-source DC–DC converter was employed in constructing a medium-voltage level DC bus and providing galvanic isolation for MMC. Nevertheless, controlling the whole system became more complex. Then, in [14], a cascaded H-bridge (CHB) multilevel converter was used to replace the MMC, and an isolated DC–DC converter was used to replace the line frequency transformer. In this architecture, the isolated DC–DC converter and the CHB module could easily be integrated into the PV system to improve the power-density of the system. Since the isolated DC–DC converter needs to undertake MPPT, its voltage gain may vary over a wide range, and its efficiency is difficult to improve. Furthermore, large-scale photovoltaic medium-voltage DC (MVDC) or high-voltage DC (HVDC) grid-connected systems are another promising direction in system structures [15,16]. In [17], a single-stage isolated DC–DC converter was used in an MVDC system, and the line frequency transformer was removed. This single-stage MVDC system was able to reduce system cost, power losses, and system bulk. However, its overall efficiency would be decreased by partial shading [18]. Hence, a two-stage DC–DC converter was used in an HVDC system in order to achieve higher frequency [19]. This paper is based on the high frequency link 35 kV PV system. The introduction of a high-frequency high-voltage isolated DC–DC converter is able to replace the line frequency transformer and save non-renewable resources. Therefore, the high-frequency high-voltage isolated DC–DC converter is one of the core technologies in PV systems.

Isolated high-frequency DC–DC converters can provide a fixed step-up ratio and galvanic isolation [19], and they constitute an important technology in PV power generation systems. A dual active bridge (DAB) was used early in PV applications because of its modular symmetric topological structure and fast dynamic response characteristics [20]. However, its ZVS range is limited by its voltage conversion ratio and load conditions. Therefore, it is difficult to achieve soft-switching throughout the full load range, and it is difficult to improve the efficiency any further [21]. In [22], a current source series resonant converter (SRC) was used as a DC–DC transformer (DCX). However, similar to DAB converters, it is difficult to implement ZVS throughout the full load range using an SRC. Recently, the LLC and CLLC topologies have become attractive due to their desirable characteristics, which include high efficiency, full load range ZVS, and zero-current-switching (ZCS) commutation [23,24,25]. Since bidirectional power flow is not a prerequisite in PV systems, CLLC converters are not suitable for improving power density. Therefore, LLC converters are the best choice.

However, there are still some problems presented by high-frequency LLC converters. On the one hand, unlike traditional low-voltage and low-frequency transformers, the insulation pressure of transformers in the converters makes the design of transformers and the selection of core materials more complex and more difficult [26]. On the other hand, the parasitic parameters of high-frequency transformer are complex, and these may have negative influences on the circuit. Furthermore, in recent years, SiC-MOSFETs have been widely used in DC–DC converters to pursue higher efficiency and higher power density [27]. Many studies have shown that SiC-based converters have greater advantages in terms of efficiency and power density compared to Si-based converters, especially in high-voltage applications [28,29,30]. However, both SiC-MOSFETs and SiC diodes have parasitic parameters. With the increase of the switching frequency of the LLC converter, the negative influences of parasitic parameters on the primary side ZVS of the high-frequency LLC converter gradually emerge [31,32]. In [33], the parasitic capacitor was investigated, and an optimized dead band was provided. In [34], the negative impacts caused by the parasitic capacitors of rectifier diodes were discussed. However, this only indicated negative influences on the DC voltage gain. In [31] and [35], the influence mechanism of parasitic parameters was investigated, and a solution was given in which the dead band and magnetic inductance were adjusted. However, the means for accurately selecting the dead band and magnetic inductance were not mentioned in those papers. The use of wide band gap devices can further improve the efficiency and power density of converters in PV systems. Unfortunately, without ZVS, the large switching losses and the deterioration of EMI characteristics caused by high switching frequency greatly reduces the performance of high-frequency LLC converters [36].

Therefore, this paper presents an architecture for the high frequency link 35 kV PV system, as shown in Figure 1. The distributed three-level boost converters with photovoltaic strings execute the MPPT algorithm. Isolated high-frequency DC–DC converters are used as DCXs between the CBH modules and a common DC bus. This paper studies the influence of parasitic parameters and theirmethod of suppression in high-frequency LLC converters in the 35 kV PV system. This paper describes how the parasitic parameters of SiC devices affect the ZVS of high-frequency LLC converters. Then, a method for suppressing the influence of parasitic parameters is proposed. By adding a saturable inductor on the secondary side, the parasitic components of the secondary side are effectively blocked from participating in the resonance of the primary side, and primary-side ZVS can be ensured. Finally, a multiple-pulse test (MPT) is carried out and a 2000 W small-scale experimental prototype is built to verify the theoretical analysis and suppression method. The experimental results show the proposed suppression methods are effective and the performance of the high-frequency LLC converter can be significantly improved.

Compared with the existing study, this work has some advantages:

• The influence of the parasitic parameters of SiC devices in high-frequency LLC converters is analyzed step by step, which is more accurate.
• The mechanism of influence of parasitic parameters on the resonance process is discussed systematically. The paper reveals how different parameters can affect the resonance process with respect to the parasitic parameters.
• The proposed method is completely different from previous studies, and achieves better performance. Since the proposed method is able to achieve ZVS without a reduction in magnetic inductance and extension of the dead band, the efficiency can be further improved.

This paper is organized as follows. In Section 2, the high-frequency isolated cascaded MVAC grid-connected system is introduced. A downscaled system and its control method are provided. In Section 3, the analysis of influences of parasitic parameters are given, and the conventional suppression method by reducing magnetic inductance is analyzed. In Section 4, the proposed suppression method and its theoretical analysis are given. In Section 5, the theoretical analysis and proposed method are verified using the experimental prototype. Section 6 concludes the paper.

2. Architecture of High Frequency Link 35 kV PV System

The architecture of the presented high frequency link 35 kV PV system is shown in Figure 1. The system can be divided into three stages, including a distributed MPPT stage (non-isolated DC–DC converter), a DC–DC step-up stage (isolated DC–DC converter), and an inverter stage (cascaded inverter). The three-level boost topology is applied in the distributed MPPT stage. The three-level boost is responsible for MPPT, and is directly connected to the PV array. The output terminal of each converter is connected to the DC bus. The isolated DC–DC step-up stage uses a high-frequency LLC converter that works as DCX to provide galvanic isolation and a high step-up ratio. The inverter stage has a cascaded inverter topology. The CHB is used in this stage, which is directly connected to the MVAC grid.

In the presented system, a high-frequency isolated DC–DC converter is used to replace the line frequency transformer. The efficiency and power density can be increased. Additionally, copper consumption can be greatly reduced. The cascaded inverter replaces the centralized inverter. Thus, the switches can operate with lower frequency, lower switching losses and higher conversion efficiency.

The presented system is oriented towards 35 kV large-scale PV power generation. A 6 MW/35 kV PV system is designed based on the presented structure. The parameters of the system are shown in

Table 1. Parameters of designed 6 MW/35 kV system.

Symbol	Description	Parameters
Vbus	DC bus voltage	800 V
Vgrid	Grid voltage	35 kV
P	Power	6 MW
NCHB	Number of CHB in one phase	40
Lg	Inductance of grid side	8 mH

. To pursue higher efficiency and higher power density, SiC devices are used in the designed system because of their lower conduction loss and better performance under high temperature conditions, even though the switching frequency of CHB is very low. Then, according to the voltage level of the grid and devices, the number of CHB is determined to be 40. For high-frequency LLC converters, SiC devices are also used to achieve higher switching frequency and higher efficiency. In addition, in order to reduce the losses associated with single diodes, several diodes are connected in parallel on the secondary side of the LLC converter. For three-level boost, the devices can be selected to be the same as the LLC converter to reduce the number of different types of device. Besides, since there are a lot of symbols in the paper, all the symbols has been listed in the Appendix C as well.

The control scheme of the system is shown in Figure 2. Since an isolated DC–DC converter operates as the DCX, its voltage gain remains unchanged. As long as the output voltage remains stable, the DC bus voltage will be stabilized. Therefore, for controlling the cascaded inverter, the DC side voltage and the AC side power factor are the main control objectives, as shown in Figure 2a.

In Figure 2a, v_dc(ki) (k = a, b, c and i = 1, 2, …, n) is the DC side voltage of unit(i) in phase k. The power reference of each CHB module p_ki is obtained by comparing v_dc(ki) with the common reference v_dc*. In the presented system, v_dc* remains constant, despite the power variation required for controlling the DC bus voltage. Hence, it is possible to achieve a standard multilevel waveform with an equal and constant voltage level. The PI controller is used to control the power in the dq. When load imbalance or asymmetric faults occur, the grid voltage will be unbalanced. In this case, in addition to decoupling the power control, the cascade inverter also needs to control the balance of the current. In Figure 2a, v_d, v_d-, v_q, v_q- are the d-axis and q-axis components of the positive and negative sequence of the grid voltage respectively, and i_d, i_d-, i_q, i_q- are the d-axis and q-axis components of the positive and negative sequence of the grid current. These parameters can be obtained by using the phase-locked loop (PLL) based on the decouple double synchronous reference frames (DDSRF). Then, the three-phase current can be balanced by suppressing negative sequence current by feedforward negative sequence voltage of grid. For the MPPT stage, non-isolated DC–DC carries out MPPT shown in Figure 2b to improve the utilization of solar energy.

To verify the architecture and control scheme of the system, a downscaled system is built. The waveforms and the control effect of the 40 kW/380 V downscaled system are shown in Figure 3. Figure 3a shows the process of connection to the grid. It can be seen that the cascaded inverter can be connected to the grid quickly. Figure 3b shows the control effect of the control scheme discussed above. It is obvious that the control scheme of the system is able to suppress the negative sequence current and ensure the output current balance.

Although the downscaled system is able to operate well, there are still some problems that need to be solved in the experiment. The influence of parasitic parameters under high step-up ratio conditions is more serious, leading to the loss of ZVS. To achieve higher efficiency in high-frequency situations, it is necessary to study the influence of parasitic parameters and their suppression methods.

3. Influences of Parasitic Parameters on the Resonance Process

3.1. Operation Principle of the Ideal High-Frequency High Step-Up Ratio LLC Converter

The topology, fundamental equivalent circuit, and theoretical waveforms of the ideal LLC converter are shown in Figure 4. In Figure 4a, M₁~M₄, D₁~D₄ and C_oss1~C_oss8 represent the channels, body diodes and parasitic capacitor of the devices, respectively. C_r is the resonant capacitor, L_r is the resonant inductor, L_m is the magnetic inductor, and D₅~D₈ are the secondary-side rectifier diodes. The turn ratio of transformer is 1:n.

When the parasitic capacitance of the secondary side is very small and can be ignored, the operation of the LLC converter can be analyzed as being under ideal conditions. Figure 4c shows the theoretical waveforms of the ideal LLC converter, in which V_dri,_M1 and V_dri,_M2 are the drive signals of M₁ and M₂, V_ds,M1 is the drain-source voltage of M₁, and i_r and i_m represent the resonant current and magnetic current, respectively. At t₁, as the current drops to zero, the secondary diodes turn off naturally and achieve ZCS because of lower di/dt. Since the magnetic inductance of the ideal LLC converter can be considered to be large enough, i_m remains unchanged and i_r remains the same as i_m. At t₂, M₁ and M₄ are turned off and i_r start to charge or discharge parasitic capacitors of devices. Because i_r is always maintained at the peak value of i_m, the commutation of primary side can be completed in a very short time. Thus, the achievement of ZVS can be ensured at t₄.

When the dead band and parasitic capacitance of secondary side are ignored, according to Figure 4b, the DC voltage gain G can be deduced from the fundamental equivalent circuit and can be expressed as:

$$G=\frac{V_{out}}{V_{in}}=\frac{1}{\sqrt{{\left(1+\frac{1}{k}-\frac{1}{k{{\Omega }}^2}\right)}^2+Q^2{\left({\Omega }-\frac{1}{{\Omega }}\right)}^2}},$$

(1)

where V_out is the output voltage, V_in is the input voltage, k is the ratio of L_m to L_r, Ω is the normalized frequency, the ratio of switching frequency f_s to resonant frequency f_r and Q is the quality factor of the fundamental equivalent circuit, in which R_eq is the equivalent resistance of the secondary side of the transformer. The DC voltage gain of LLC has been shown in Figure 5. According to Figure 5, when f_s > f_r, there is no ZCS in the secondary side because of the high di/dt; however, when f_s << f_r, the LLC converter will operate in the capacitive zone and there is no ZVS. Therefore, the operation zone shown in Figure 5 is the best choice and f_s < f_r. Since the high-frequency ratio LLC converter operates as DCX, the larger k is preferred to resist the frequency disturbance because of its flatter DC voltage gain curve according to Figure 5b. It is obvious that the gain of the LLC converter changes by less than 10% with the changing of the load, even under the condition that f_s = 0.9f_r.

3.2. Analysis of the Operation Principle of the LLC Converter Considering Parasitic Parameters

In the practical application of the high-frequency LLC converter, the parasitic capacitor of the secondary diodes cannot be ignored. The topology of the LLC converter in consideration of the parasitic parameters is shown in Figure 6a. C_oss5~C_oss8 represent the junction capacitors of the rectifier diodes. The reference direction of i_r, i_m and i_s are the same as the directions shown in Figure 6a.

In general, the LLC converter is designed in consideration of ideal conditions. Nevertheless, with the increase in the magnetic inductance of the LLC converter, the influence of the magnetic current becomes weaker, and the equivalent parasitic parameters of the secondary devices becomes much greater compared with LLC converters in traditional step-down applications. The parasitic parameters have a negative influence on the primary-side ZVS. The theoretical waveforms of the LLC converter considering parasitic parameters are shown in Figure 6c. V_dri,_M1 and V_dri,_M2 are the drive signals of M₁ and M₂, V_ds,M1 is the drain-source voltage of M₁, V_D5 represents the voltage of the secondary rectifier diode D₅, and i_r and i_m represent the resonant current and magnetic current, respectively. In the first half cycle, the LLC converter can be divided into four states, as shown in Figure 7.

In Stage3, the parasitic capacitance of both sides participates in the resonance process, as shown in Figure 7c. The equivalent circuit of Stage3 between t₂ and t₃ is shown in Figure 6b. C_oss,p and C_oss,s represent the parasitic capacitance of the primary and secondary devices, respectively. According to the equivalent circuit, the secondary-side parasitic capacitance was changed by n², and the influence on the resonance process was changed as well. Additionally, with the extensive use of SiC devices, the switching frequency of the LLC converters is continuously improved, and the loss increase caused by the loss of ZVS is more serious.

Since the waveform of the LLC converter is completely symmetrical in every half cycle, only the former half cycle is analyzed.

Stage 1 (t₀~t₁): As shown in Figure 7a, both M₁/M₄ and D₅/D₈ are conductive. The voltage of L_m is clamped by the output voltage, and the i_m increases linearly. Because the resonant elements L_r and C_r form a band-pass filter, only the current near the resonant frequency is able to pass through the resonant network. Therefore, i_r varies as a resonant frequency sinusoidal curve.

Stage 2 (t₁~t₂): As shown in Figure 7b, M₁ and M₄ are still conductive, while D₅ and D₈ are naturally turned off, because the current drops to zero with a low di/dt. Thus, ZCS is achieved on the secondary side. Then, the secondary-side parasitic capacitors C_oss5~C_oss8 are introduced into the resonant network. A higher frequency resonance occurs in both V_D5 and i_r. In this stage, i_r fluctuates near i_m.

Stage 3 (t₂~t₃): As shown in Figure 7c, M₁ and M₄ are turned off and i_r starts to charge or discharge the parasitic capacitors C_oss1~C_oss4. In this stage, both C_oss1~C_oss4 and C_oss5~C_oss8 are involved in the resonance process. This stage is very important, because the resonance process has a great influence on the primary-side ZVS. In this stage, according to the Kirchhoff voltage laws (KVL), i_r should meet:

$$\{\begin{array}{l}{u}_{cq}+u_{cr}+L_r\frac{d{i}_r}{dt}+L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}=u_{cd}\end{array}$$

(2)

Furthermore,

$$\{\begin{array}{l}{i}_r=C_q\frac{d{u}_{cq}}{dt}=C_r\frac{d{u}_{cr}}{dt}\\ i_m=i_r-C_d\frac{d{u}_{cd}}{dt}\end{array}$$

(3)

where C_q, C_r and C_d are capacitances of C_oss1~C_oss4, the resonant capacitor and C_oss5~C_oss8, respectively. U_cq, u_cr and u_cd are the voltage of corresponding capacitor, and i_r and i_m represent the current of the resonant inductor L_r and magnetic inductor L_m. The initial values are the final values of Stage 2.

Stage 4 (t₃~t₄): As shown in Figure 7d, primary-side commutation is completed and D₂ and D₃ are turned on naturally. At the same time, D₆ and D₇ are turned on as well. The voltage of L_m is clamped by the output voltage, and the i_m increases linearly. i_r varies as a resonant frequency sinusoidal curve. At t₄, M₂ and M₃ are turned on, and the ZVS is achieved.

Obviously, with the addition of secondary-side parasitic capacitors, the resonance process in Stage 3 is changed dramatically, according to Equations (2) and (3). This change may mean that the ZVS cannot be achieved. Usually, the achievement of ZVS needs to meet:

$$\{\begin{array}{l}{i}_r(t)\ge 0\\ {\displaystyle {\int }_0^{T_{dead}}{i}_r(t)}dt\ge 2C_q{V}_{in}\end{array}$$

(4)

where T_dead is the dead band of the converter. In Equation (4), the first condition ensures that the voltage of the primary side devices can achieve ZVS, and the second condition ensures that i_r can provide sufficient charge to achieve ZVS in the dead band. Therefore, i_r(t) is very important for the realization of primary-side ZVS. According to Equations (2) and (3), the i_r(t) in Stage 3 can be plotted by MATLAB. Then, the influence of secondary parasitic capacitance on ZVS can be obtained according to Figure 8. Figure 8 presents the change of V_ds,M1 during the transient with different C_d and L_m or L_r. When C_d = 0, the equivalent circuit becomes the circuit of the ideal LLC converter and V_ds,M1 change linearly.

As shown in Figure 8, with the increase of C_d, i_r is shared by the parasitic capacitors of the secondary side, which increases the time required to fully charge the primary-side capacitors. To ensure that ZVS can be achieved, the dead band must be longer than the time needed to charge C_oss1 and C_oss4. Furthermore, since the switch turns off after i_r is equal to i_m, i_r(t₂) = i_m(t₂) is assumed.

According to Figure 8a, the L_m influences the resonance process and ZVS. It is obvious that the smaller Lm is, the larger initial i_r(t₂) is and the shorter the time needed to achieve ZVS under the same parasitic parameter conditions. However, smaller L_m will lead to larger conduction loss and switching loss. Therefore, a careful tradeoff has to be made.

Additionally, according to Figure 8b, L_r also influences ZVS. The change of L_r leads to the change of resonant frequency and impedance in the resonance process. Then, the time to achieve ZVS is changed. It is obvious that the larger the L_r is, the more serious the influence of parasitic capacitance on the ZVS will be.

The above analysis shows that when parasitic capacitance can be extracted, to achieve ZVS, L_m, L_r and T_dead should be carefully designed in the high-frequency LLC converter.

In the traditional design method for LLC converters, to achieve ZVS, L_m is usually limited by:

$$L_m\le \frac{n{V}_o{T}_{dead}}{8V_{in}{C}_q{f}_s}$$

(5)

However, Equation (5) ignores the secondary-side parasitic capacitors and resonance process in the dead band. According to the above analysis, there are two ways of ensuring the realization of ZVS via careful parameter design. The first is that i_r is always larger than zero. This means that ZVS can be achieved only by adjusting the dead band (of course, the dead band must be within acceptable limits). The second is that the charge or discharge of primary-side parasitic capacitors can be completed before i_r drops to zero. To achieve ZVS, generally the L_m is selected as a small value compared to the theoretical value calculated by Equation (5). However, L_m is an important parameter in high-frequency LLC converters, because it not only affects the realization of soft switching, but also the power loss of the converter. In the LLC converter, the resonant current i_r, magnetic current i_m, primary-side current of transformer i_p and secondary-side current of transformer i_s can be derived as:

$$\{\begin{array}{l}{i}_r(t)=I_r\sin (2\pi f_{s}t-\phi )\\ i_m(t)=\{\begin{array}{cc}\frac{n{V}_{out}t}{L_m}-I_m\hfill & 0\le t\le \frac{1}{2f_s}\\ -\frac{n{V}_{out}\left(t-\frac{1}{2f_s}\right)}{L_m}+I_m\hfill & \frac{1}{2f_s}<t\le \frac{1}{f_s}\end{array}\\ i_p(t)=i_r(t)-i_m(t)\\ i_s(t)=-n{i}_p(t)\end{array}$$

(6)

$$\{\begin{array}{l}{I}_m=\frac{n{V}_{out}}{4L_m{f}_s}\\ I_r=\sqrt{{\left(\frac{\pi P}{2n{V}_{out}}\right)}^2+I_m^2}\\ \phi =\arcsin (\frac{I_m}{I_r})\end{array}$$

(7)

Thus, the conduction loss and switching loss of LLC can be calculated, and the relationship between the total loss P_loss and L_m is shown in Figure 9. There is an obvious demarcation point in Figure 9, namely, L_m.min. When L_m is smaller than L_m.min, the P_loss increases rapidly with the decrease of L_m, no matter at light load condition or at heavy load condition, which will lead to a lower efficiency in the full load range. Therefore, a new method to suppress the influence of parasitic parameters in the LLC converter without efficiency loss is very important to improve the efficiency of the PV system.

4. Suppression Method of the Influence of Parasitic Parameters Based on the Saturable Inductor

In the PV system, LLC converters based on SiC devices have a higher switching frequency, which can further improve the system efficiency and the power density of the system. However, parasitic parameters lead to the loss of ZVS, the increase in power loss, and the deterioration of EMI characteristics at high frequencies. Although the methodological analysis above is able to suppress the influence of secondary parasitic parameters by reducing the L_m, the increase in power loss is still inevitable. To ensure the implementation of ZVS and improve the efficiency of the LLC converter, a structure for an LLC converter with a saturable inductor, as shown in Figure 10a, is proposed. In addition, its theoretical waveforms are shown in Figure 10b.

In Figure 10a, L_s is the initial inductance of the saturable inductor, and I_c is the current when L_s becomes saturated. The L_s is added to the secondary side. Since the I_c is very small, the L_s is saturated for most of the time in a cycle, and the circuit structure is the same as that of the traditional LLC converter. When the secondary current i_s is near to zero, the L_s gradually withdraws from the saturated state, and is added into the secondary circuit as an inductor. Therefore, L_s blocks the parasitic capacitance of the secondary side to participate in the resonance process and ensures the achievement of ZVS of the primary side. According to Figure 10b, the operation of the LLC converter with the saturable inductor can be divided into five stages.

4.1. Analysis of the Operation Principle of the LLC Converter with the Saturable Inductor

The five stages of the LLC converter with the saturable inductor are shown in Figure 11.

Stage 1 (t₀~t₁): As shown in Figure 11a, both M₁/M₄ and D₅/D₈ are conductive. The voltage of L_m is clamped by the output voltage, and the i_m increases linearly. Because the resonant elements L_r and C_r form a band-pass filter, only the current near the resonant frequency is able to pass through the resonant network. Therefore, i_r varies as a resonant frequency sinusoidal curve. In this stage, according to KVL:

$$\{\begin{array}{l}{V}_{in}-u_{cr}-L_r{C}_r\frac{d^2{u}_{cr}}{dt}-L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}=V_o\end{array}$$

(8)

Stage 2 (t₁~t₂): As shown in Figure 11b, M₁ and M₄ are still conductive, and |i_s| < I_c. Thus, the L_s participates in the operation of the LLC converter and D₅ and D₈ remain conductive. Therefore, i_r decreases slowly and linearly. In this stage, according to KVL:

$$\{\begin{array}{l}{V}_{in}-u_{cr}-L_r\frac{d{i}_r}{dt}-L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}=V_o+L_s\frac{d{i}_s}{dt}\end{array}$$

(9)

According to Kirchhoff current laws (KCL):

$$i_r=i_m+i_s=C_r\frac{d{u}_{cr}}{dt}$$

(10)

Stage 3 (t₂~t₃): As shown in Figure 11c, M₁ and M₄ are still conductive, while D₅ and D₈ are still conductive because of the presence of L_s. Then, i_r starts to charge or discharge parasitic capacitors C_oss1~C_oss4. At this stage, i_r decreases slowly and C_oss1 and C_oss4 are fully charged in a short time. Therefore, according to KVL, i_r meet:

$$\{\begin{array}{l}{u}_{cq}+u_{cr}+L_r\frac{d{i}_r}{dt}+L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}=V_o+L_s\frac{d{i}_s}{dt}\end{array}$$

(11)

According to KCL and voltage-current relationship (VCR):

$$i_r=i_m+i_s=C_r\frac{d{u}_{cr}}{dt}=C_q\frac{d{u}_{cq}}{dt}$$

(12)

Stage 4 (t₃~t₄): As shown in Figure 11d, D₂ and D₃ naturally become conductive, because C_oss2 and C_oss3 were fully discharged in Stage 3. Then, i_s drops to zero, D₅ and D₈ are turned off and ZCS can be achieved because of lower di/dt. After that, C_oss5~C_oss8 participate in the resonance process and are charged or discharged. In this stage, according to KVL:

$$\{\begin{array}{l}{V}_{in}-u_{cr}-L_r\frac{d{i}_r}{dt}-L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}=u_{cd}+L_s\frac{d{i}_s}{dt}\end{array}$$

(13)

According to KCL and VCR:

$$\begin{array}{l}{i}_r=i_m+i_s=C_r\frac{d{u}_{cr}}{dt}=C_q\frac{d{u}_{cq}}{dt}\\ i_s=C_d\frac{d{u}_{cd}}{dt}\end{array}$$

(14)

Stage 5 (t₄~t₅): As shown in Figure 11e, both D₂/D₃ and D₆/D₇ are conductive and L_s becomes saturated. The voltage of L_m is clamped by the output voltage, and the i_m decreases linearly and i_r varies as a resonant frequency sinusoidal curve. At t₅, the M₂ and M₃ are turned on, and primary side ZVS is achieved. In this stage, according to Figure 11e:

$$\{\begin{array}{l}{V}_{in}+u_{cr}+L_r{C}_r\frac{d^2{u}_{cr}}{dt}+L_m\frac{d{i}_m}{dt}=0\\ L_m\frac{d{i}_m}{dt}+V_o=0\end{array}$$

(15)

Besides, some s-domain analysis has been shown in the Appendix B.

4.2. Analysis and Design of the Saturable Inductor

The inductance and energy storage of the ideal saturable inductor are shown in Figure 12.

In Stage 2 and Stage 3, L_s maintains i_s greater than zero, which causes the rectifier diodes to be continuously conductive. At these two stages, secondary-side parasitic capacitance will not participate in the operation of the circuit. In Stage 3, L_s causes the i_r to remain basically unchanged, which leads to a shorter time for the primary side until commutation. Then, the secondary side voltage of the transformer can be approximated as:

$$V_s\approx V_{in}+V_c+L_r\frac{d{i}_r(t)}{dt}$$

(16)

where the V_c is the peak value of the resonant capacitor voltage, so the i_s(t) can be expressed as:

$$i_s(t)=I_c-\frac{V_o-V_s}{L_s}t$$

(17)

To ensure the completion of primary-side commutation, i_s should always be greater than zero at t₃, that is:

$$I_c{L}_s\ge (V_o-V_s)(t_3-t_1)$$

(18)

In Stage 4, the L_s causes the i_s to be less than zero. After the secondary diodes are turned off and ZCS is achieved, the parasitic capacitors participate in the resonance process. At t₄, i_s decreases to −I_c and D6 and D7 become conductive. Then, the L_s becomes saturated and no longer participates in the operation of the circuit. In Stage 5, the resonant current i_r(t) can be expressed as:

$$i_r(t)\approx I_m-I_c+\frac{V_o+V_c-V_{in}}{L_r}t$$

(19)

where I_m is the peak value of i_m. To ensure that the primary-side body diode is conductive in these two stages, the i_r(t) must be greater than zero; therefore,

$$I_c\le I_m+\frac{V_o+V_c-V_{in}}{L_r}(t_5-t_4)$$

(20)

According to the constraints of (19) and (21), the values of I_c and L_s for the saturable inductor can be designed.

5. Experimental Verification and Analysis

To verify the influence of parasitic parameters on ZVS, as well as to validate the two suppression methods proposed in this paper, a 2000 W down-scale prototype is built.

Since the system is based on SiC devices, the driving circuit and protection constitute an important technology. In comparison with Si-MOSFET, SiC-MOSEFET has some significant differences in terms of its characteristics, due to its different material and structure. SiC-MOSEFET has the advantages of low on-state resistance and fast switching speed. However, due to the low gate threshold voltage, it is more likely to suffer from interference and erroneous conduction. Therefore, the driving circuit of SiC-MOSFET cannot be simply replaced by that of Si-MOSFET.

In the LLC converter, SiC devices are mainly used as full-bridge switching devices on the primary side. Usually the switching on and off of SiC devices is affected by their output capacitance under soft-switching conditions, and the crosstalk problem is not serious. However, because the switching speed of SiC devices is very fast and the transient dv/dt is very large, once the ZVS has been lost, the crosstalk problem becomes very serious. Subsequently, the increase in gate voltage caused by crosstalk will be threatening to SiC-MOSFET during this period. Therefore, effective driving and protection circuits are also the focus of the driving design of the SiC devices.

CREE, ROHM and other companies have successively introduced commercial SiC device driving circuits, but few of these circuits involve solutions to driving protection problems. In this paper, C2M0080120D is used as the primary side switch in the experiment. To meet the high reliability requirement of the PV system, short-circuit protection is considered in the design of the driving circuit, as shown in Figure 13. SiC devices are driven by a 24 V isolated power supply, and a BROADCOM ACPL-339J-000E optocoupler driver chip is used to achieve isolation and protection. This chip provides a user-setup desaturation protection circuit scheme, which is able to provide effective protection for the devices and improve system reliability when a short-circuit occurs. In the driving circuit, the gate parallel resistor and capacitor of SiC-MOSFET are able to reduce the influence of crosstalk. In the short-circuit protection circuit, C_blank and Z_DESET are designed according to the actual needs, whereby C_blank determines the allowable blank time of driving protection and Z_DESET determines the corresponding current value of protection. When short-circuit protection is triggered, V_GMOS will increase to a high level. The soft turn-off time is determined by the series resistance of Q₃ and the input capacitance C_iss of SiC-MOSFET.

As shown in Figure 14a, the parasitic capacitance of the SiC-MOSFET and SiC diodes is usually nonlinear. Therefore, the time-related equivalent parasitic capacitance C_oss(tr) is very important. Generally, the MPT circuit shown in Figure 14b can be used to measure the equivalent parasitic capacitance. Figure 14c shows the hard switching process of the SiC MOSFET. V_DS is the drain-source voltage of the device, I_LOAD is the load current, I_D is the drain current of the device, and Q_oss is the charge caused by C_oss. According to the characteristics of the capacitor, the C_oss(tr) can be calculated as

$$C_{oss(tr)}=\frac{{\displaystyle {\int }_{t_1}^{t_2}{i}_D(t)dt}}{V_{DS}}$$

(21)

where i_D(t) is the expression of drain current between t₁ and t₂.

The waveforms of the MPT are shown in Figure 15. V_M is the drain-source voltage, i_M is the drain current, i_D is the current of the diode and V_D is the voltage of the diode. The test voltage is 400 V, and the final current is 20 A. According to the results of MPT, the driving circuit was verified. The Q_oss was calculated, and the C_oss(tr) obtained by (21) was 1.6 nF. Additionally, the switching loss of SiC-MOSFET under hard-switching conditions can be calculated.

According to the analysis above, in consideration of parasitic parameters, the parasitic capacitance of primary- and secondary-side devices is very important for the parameter design of high-frequency LLC converters. However, the parasitic capacitance is not a fixed value. It is related to the voltage of the device. Generally, the values of parasitic capacitance are replaced by time-related equivalent capacitance. The equivalent capacitances of C2M0080120D and IDH10G65C5XKSA1, which are used in the experiment, are shown in

Table 2. Experiment parameters of the 2000 W prototype.

Symbol	Description	Parameters
		Dead Band Extended	Reduce Magnetic Inductance	Add Saturable Inductor
Vin	Input voltage	400 V	400 V	400 V
Vo	Output voltage	400 V	400 V	400 V
Po	Output Power	2000 W	2000 W	2000 W
Lr	Resonant inductance	20 μH	20 μH	20 μH
Lm	Magnetic inductance	300 μH	80 μH	300 μH
Cr	Resonant capcitance	156 nF	156 nF	156 nF
M	Primary side devices	C2M0080120D	C2M0080120D	C2M0080120D
D	Secondary side devices	IDH10G65C5XKSA1 (6 parallel)	IDH10G65C5XKSA1 (6 parallel)	IDH10G65C5XKSA1 (6 parallel)
Cossm	Capacitance of primary side devices	1.6 nF	1.6 nF	1.6 nF
Cossd	Capacitance of secondary side devices	6 × 40 pF	6 × 40 pF	6 × 40 pF
Ls	Inductance of the saturable inductor			300 μH (Ic = 1 A)

. The parameters of the experimental prototype are also listed in Table 2.

Figure 16 shows the waveform of the LLC converter using the traditional magnetic inductance limitation. According to Equation (5), the maximum inductance value of L_m is 500 μH when the dead band is extended from 500 ns to 700 ns, in accordance with [31]. To ensure that ZVS can be achieved, considering a margin of 1.5 times, the 300 μH is selected as the experimental inductance in the experiment. In Figure 16, i_r is the resonant current, V_M1 is the voltage of M₁, V_D5 is the voltage of D₅, and V_dri is the driving signal of M₁. Although the margin is considered in the design, the ZVS still cannot be realized under full-load conditions. Hard switching increases the interference in the driving signals and reduces the efficiency of the converter. In addition, since there is some interference in the driving signals, this experimental method cannot be used in the actual system. In Figure 16, Stage 1~3 correspond to the stages in the theoretical analysis. In Stage 1, i_r is part of a sinusoidal waveform and M₁ has been turned off. At the beginning of Stage 2, i_r begins to oscillate instead of being maintained near the magnetic current because of the participation of parasitic capacitors of the secondary-side diodes. Since the f_s is only slightly smaller than f_r, this stage is very short. At the beginning of Stage 3, the parasitic parameters of the primary- and secondary-side devices participate in a resonance process together until the dead band ends or the ZVS has been achieved. It is noteworthy that the secondary diodes become conductive before the ZVS is achieved. Then, i_r begins to transmit power to the load, causing the realization of ZVS to become impossible. Therefore, even though the dead band is extended, the ZVS cannot be achieved, as shown in Figure 16.

Figure 17 shows the waveform of the LLC converter, where the magnetic inductance is reduced according to [31,35]. The parasitic capacitance is measured by MPT, and 80 μH is finally selected as the experimental inductance according to a simulation. In Figure 17, it can be seen that ZVS can be achieved under full-load conditions. Additionally, there is no interference in the driving signal. However, the magnetic current clearly increases because of the reduction of the magnetic inductance, which leads to the increase of conduction loss and switching loss. In Figure 17, Stage 1~4 correspond to the stages in the theoretical analysis. Stage 1 and Stage 2 are similar to the stages in Figure 16. At the beginning of Stage 3, the parasitic parameters of the primary- and secondary-side devices also participate in the resonance process together until the dead band ends or ZVS has been achieved. However, since the magnetic inductance is reduced and the magnetic current is increased, the primary-and secondary-side commutation finish almost simultaneously. Then the load will be supported by source instead of by resonant inductor. Therefore, in Stage 4, the primary side ZVS is achieved.

Figure 18 shows the experimental waveform of the LLC converter with the saturable inductor on the secondary side. 300 μH is selected as the magnetic inductance for comparison. It can be seen that ZVS can be realized under full-load conditions. Additionally, there is no interference in the driving signal. Since the magnetic current has hardly increased, the loss is obviously reduced compared with the method of reducing the magnetic inductance. In Figure 18, Stage 1~5 correspond to the stage in theoretical analysis. In Stage 1, i_r is part of sinusoidal waveform and M₁ has been turned off. As the |i_r| decreases, the saturated inductor gradually exits out of the saturated state, and then the Stage 2 begins. Thereafter, the i_r varies linearly. At the beginning of state 3, the primary device begins to commutate, which is different from the two experiments mentioned above. Since the saturable inductor keeps the secondary current constantly below 0, the parasitic capacitance of the secondary-side diodes no longer p in this stage. Then the problem of the secondary side completing the commutation before the primary side can be avoided. At the beginning of Stage 4, the primary side commutation is completed and ZVS-on is realized. When the current i_s exceeds 0, the secondary diodes begin to commutate. If the primary switch is not fully turned on and the secondary commutation is finished, the secondary diodes enter Stage 5. It is obvious the resonant current of this experiment is much lower than that shown in Figure 17. This means that higher efficiency can be obtained.

Figure 19 shows the efficiency curves and loss breakdowns of three experiments under full load conditions. It is obvious that the proposed method is able to achieve the highest efficiency across the full load range compared with the others. The full load efficiency of the proposed method is able to achieve 98.6%. Although the efficiency of the experimental parameters designed by traditional method with the extended dead band is only slightly lower than the proposed method, it is still not suitable for practical application due to its terrible driver conditions, as shown in Figure 16. The converter with reduced magnetic inductance is clearly able to achieve ZVS. However, according to the theoretical analysis shown in Appendix A, from the point of view of power loss, the loss of the primary-side devices is significantly increased. Compared with the former, the method based on the saturable inductor is able to reduce the conduction loss by 56.74% and the switching loss by 73%. Then, the full-load efficiency can be increased by 0.7%. Obviously, the suppression method based on the saturable inductor is better.

6. Conclusions

This paper presents the architecture of a high frequency link 35 kV PV system and studies the influence of the parasitic parameters of the high-frequency high-voltage isolated DC–DC converter. This paper reveals how the parasitic parameters affect the realization of ZVS of the LLC converter in high-frequency situations, and proposes a method for suppressing the influences of parasitic parameters and promoting the realization of ZVS. The method effectively prevents parasitic elements of the secondary side from participating in the resonance of the primary side by adding a saturable inductor on the secondary side to ensure that ZVS can be achieved.

This paper has some advantages compared to the existing research,

• The influence of the parasitic parameters of SiC devices on the high-frequency LLC converter is analyzed step by step, which is more accurate.
• The mechanism of influence of the parasitic parameters on the resonance process is discussed systematically. This paper reveals how different parameters are able to affect the resonance process with respect to parasitic parameters.
• Compared to the extended dead band, the proposed suppression method is able to cause ZVS to be realized and to eliminate the driving interference.
• Compared to the reduced magnetic inductance, the proposed suppression method can significantly decrease the power loss caused by magnetic inductance. The conduction loss can be reduced by 56.74% and the switching loss by 73%. The efficiency can be improved by 0.7%.

Compared with the conventional method, which involves reducing magnetic inductance, the proposed method does not need to reduce the magnetic inductance, and this is beneficial for reducing the magnetic current of the transformer and improving the efficiency of the LLC converter. The experimental verification shows that the theoretical analysis is consistent with the actual situation. The proposed parasitic parameter suppression method is able to significantly improve the efficiency of the LLC converter. Furthermore, the proposed method is able to improve the efficiency and performance of the MVAC PV system.