Modular Isolated DC-DC Converters for Ultra-Fast EV Chargers: A Generalized Modeling and Control Approach ^†

Abstract

Electric Vehicles (EVs) play a significant role in the reduction of CO₂ emissions and other health-threatening air pollutants Accordingly, several research studies are introduced owing to replacing conventional gasoline-powered vehicles with battery-powered EVs. However, the ultra-fast charging (UFC) of the battery pack or the rapid recharging of the battery requires specific demands, including both: the EV battery and the influence on the power grid. In this regard, advanced power electronics technologies are emerging significantly to replace the currently existing gas station infrastructures with the EV charging stations to move from conventional charging (range of hours) to UFC (range of minutes). Among these power electronics conversion systems, the DC-DC conversion stage plays an essential role in supplying energy to the EV via charging the EV’s battery. Accordingly, this paper aims to present possible architectures of connecting multiple Dual Active Bridge (DAB) units as the DC-DC stage of the EV fast charger and study their Small-Signal Modeling (SSM) and their control scheme. These are, namely, Input-Series Output-Series (ISOS), Input-Series Output-Parallel (ISOP), Input-Parallel Output-Parallel (IPOP), and Input-Parallel Output-Series (IPOS). The control scheme for each system is studied through controlling the output filter inductor current such that the current profile is based on Reflex Charging (RC). The main contribution of this paper can be highlighted in providing generalized SSM as well as providing a generalized control approach for the Input-Series Input-Parallel Output-Series Output-Parallel (ISIP-OSOP) connection. The generalized model is verified with three different architectures. The control strategy for each architecture is studied to ensure equal power sharing, where simulation results are provided to elucidate the presented concept considering a three-module ISOS, IPOP, ISOP, and IPOS DC-DC converters.

1. Introduction

Due to high fossil fuel prices, CO2 emissions and other health-threatening emissions, environmental awareness has shown a high interest in Electric Vehicles (EVs) [1]. Replacing conventional gasoline-powered vehicles with battery-powered EVs is expected to reduce fuel consumption significantly [2]. As a response to the ecological issues, a movement towards electrification is taking place in the transport sector. Many research studies have been provided to support this movement in [3,4,5,6]. To compete with conventional combustion engine vehicles and ensure the wide adoption of EVs, significant efforts are still needed. One of the main issues limiting the widespread penetration of EVs is the long charging duration that usually exceeds 30 min [7]. In other words, one of the challenging problems limiting EVs’ utilization is the lack of efficient and fast charging capabilities. Accordingly, Ultra-Fast Charging (UFC) is a necessary concept to be investigated to allow massive integration for EVs in the market, particularly when concerning long-distance travel [2]. In this regard, industrial and academic fields have been pushed to explore the Ultra-Fast EV Charging (UF-EVC) concept. This is due to the fact that fast-charging stations allow the recharging process to be done in a few minutes and hence overcoming EVs limitation problem. Studies have shown that the charging process affects EVs’ adoption significantly. Therefore, future EV charging stations should have the capability of charging EVs from 10% State-of-Charge (SoC) to $90\%$ SoC in few minutes [8,9,10]. Nowadays, battery technologies are evolving, enabling the EV’s battery to be charged at higher power levels. Currently, offboard fast-charging stations are provided to speed up the charging process [10,11,12,13,14].

Conventionally, the charging methods are categorized based on the charging speed and power into three different levels, which are: level 1, level 2, and level 3 (also termed as the DC fast charging) [15]. Shortly, a new battery technology that reduces the charging time to 3 min is expected to be commercialized [15]. This introduces a new charging level termed the ultra-fast/super-fast charging level, which is different from the present DC fast charging that is commonly used in industrial and academic fields 15.

Table 1. Electrical vehicle (EV) charging stations’ electrical specifications.

Charging Level	Input Voltage	Phase	Power	Time
Level 1	$120 \mathrm{VAC}$	(Single) AC	$1.5–2 \mathrm{kW}$	$10–14$ h
Level 2	$208/240\mathrm{VAC}$	(Single) AC	$7–20 \mathrm{kW}$	$1–3$ h
Level 3 (DC Fast Charging)	$480 \mathrm{VAC}$	(Three) DC	$50–100 \mathrm{kW}$	$12–24$ min
Ultra-fast/Super-fast Charging	$400 \mathrm{VAC}$ or Medium Voltage ranging from $10-40 \mathrm{kV}$	(Three) DC	$300–700 \mathrm{kW}$	$<3$ min

shows the electrical specifications for the EV charging stations [15].

To enable UFC for EVs, advanced power electronics converter technologies play an essential role in terms of both flexibility and efficiency. Accordingly, this paper focuses on high-power DC-DC converters that can be employed in UFC stations. As mentioned earlier, one of the main obstacles limiting the broad adoption of EVs is the long charging time. To avoid this problem, UFCs should be designed at a higher power level. Toward this direction, BMW and Porsche, as a part of the Fast Charge Consortium (a group of industrial companies engaged in the “Fast Charge” research project), have demonstrated the latest super-fast EV charger that can considerably charge EVs faster than the present charging methods [16]. Similar systems are demoed by the two companies, where the electric prototype for Porsche is capable of charging at a power level of $400 \mathrm{kW}$ in less than $3$ min for the first $100 \mathrm{km}$ with a battery capacity of $90 \mathrm{kWh}$. While the experimental system for BMW is capable of charging at a power level of $350 \mathrm{kW}$ in $15$ min ($10\%$ to $80\%$ SoC) [16]. The charging process is done using a DC-DC converter that converts a charging station input voltage of $800 \mathrm{V}$ to a lower voltage of $400 \mathrm{V}$ [17]. The latest prototypes by both companies can work up to $900$ and $500 \mathrm{A}$, meaning that it can charge at a power level of $450 \mathrm{kW}$, which is three to nine times the capacity of the existing up-to-date DC fast-charging stations [16,17]. This capacity increase significantly reduces the duration of the charging time. Tesla has shown significant efforts to introduce fast charging for EVs. However, the current cars presented by Tesla can only charge at a maximum of $120 \mathrm{kW}$. Tesla will add enhanced superchargers in 2020. Nonetheless, the charging speed of those cars is boosted to double the charging rate of the current vehicles [16].

The Fast Charge research group is investigating the required technical specifications in terms of the fast charging infrastructure and the EV to match the high charging capacities. Siemens, as a part of the research group, has provided an energy supply system to be used in the project, allowing researchers to examine the fast-charging capacity limits demonstrated by the EV’s batteries. The system can handle high voltage that reaches up to $920\mathrm{V}$, which is the voltage level predicted for the future EVs [17]. The controller of the charger makes sure that the output is modified automatically according to the EV, allowing different EVs to be charged using a single infrastructure. To illustrate, the UFC station can be used with battery systems rated at $400$ and $800\mathrm{V}$, where the charging capacity is adapted automatically to the maximum charging capacity on the EV side. The system is characterized by its flexibility and modularity, allowing multiple EVs to be charged at the same time instant [17].

Such fast-charging stations require DC-DC converters of high-power to be designed to achieve high reliability and high efficiency for the system. One of the fast-charging stations’ requirements is to develop the DC-DC converters in a modular structure since such configuration can provide redundancy, easier maintenance, as well as scalability, and ride-through capability [18].

To further illustrate, to meet the requirements of the high-voltage high-power fast charger, two approaches are established. The first approach is through semiconductor devices with high-voltage and high-current ratings to be integrated into the two-level converter topologies with series/parallel connections. However, the series connection of power switches results in the unsymmetrical sharing of voltage among the switching devices because of the switches’ unequal parameters, such as the switching delays, leakage inductance, and collector-to-emitter capacitance. Accordingly, voltage balancing methods are required to avoid any failure [19].

In the second approach, power electronic converters are usually pursued to be built in a modular manner in fast-charging stations [20]. Modular converters contain several numbers of smaller modules. Building converters in a modular way is a cost-effective solution. Besides, smaller modules can be hot swapped in failure cases, which makes the maintenance of such converters easier. Moreover, the number of modules can be scaled up according to the power rating of the system.

Furthermore, by installing more modules, the concept of redundancy can be established. In other words, in modular structure-based DC-DC converters, each cell handles a small portion of the total input power. Consequently, the selected power switches are of lower voltage ratings, hence, higher switching frequency capability. Therefore, the converter efficiency is improved due to lower losses, and the transformer size is reduced due to the increase in the switching frequency [21,22]. To avoid the demerits associated with the first approach, modular converters’ topologies, such as Multimodule Converters and Modular Multilevel Converters, are used to provide the modularity feature and achieve high-voltage and high-power requirements [23]. Nonetheless, the multimodule DC-DC converters are considered in this paper since the modularity concept is not limited only to the power electronics but also is extended to include the magnetics. Moreover, higher switching frequencies can be achieved in the AC link, which results in reduced weight and size of the overall power converter. Although the high-frequency transformer employment allows for a reduction in the overall converter size and weight, the overall system cost is increased, especially with the power increase. Multimodule converters are applicable for EV UFC since scalability, reliability, redundancy, and ride-through capability can be provided. Besides, such converters utilize low-power modules where each module handles only a fraction of the total required power. However, the system complexity increases with the increase in the number of modules. Moreover, the impact of EVs UFC on the grid should be considered. Therefore, coordinated charging should be devised to address challenges that might be encountered with uncoordinated EVs UFC, particularly when multiple batteries are charged through UFC mode. Furthermore, the on-going technology development in the batteries’ industry supports the proliferation of EVs UFC through introducing high capacity batteries that can accept such mode of charging.

Multimodule DC-DC converters can offer a bidirectional power flow through utilizing submodules that contain Dual Active Bridge (DAB), Dual Half Bridge (DHB), or series resonant converters, where each configuration has its pros and cons [24,25]. In multimodule converters, soft switching operation, as well as higher switching frequency, can be achieved, resulting in a significant reduction in the component volume without sacrificing the efficiency [24]. The possible architectures of connecting multimodule-based DAB units are classified into four main categories, which are: Input-Series Output-Series (ISOS), Input-Parallel Output-Parallel (IPOP), Input-Series Output-Parallel (ISOP), Input-Parallel Output-Series (IPOS) [26].

A typical fast charger is usually connected to a $400\mathrm{V}$AC grid ($570VDC$ rectified) [27]. However, this low voltage results in high current and causes high losses in the magnetic components, bus bars, and switching devices [28]. Accordingly, connecting the fast charger to a higher input voltage level $\left(10–40\mathrm{kV}\right)$ will reduce the current and conduction losses in the DC-DC converter. In [29,30], a DC link with a voltage of $1000\mathrm{V}$ has been proposed to the high power, while, in [31], the fast charger is connected to a medium voltage connection of $2.4\mathrm{kV}$. In [28], a multiport converter for EVs’ fast chargers has been proposed, where the charging process is done via a $6$ to $10\mathrm{kV}$ supply grid.

In [15], a power architecture for the upcoming super-fast EV charging stations has been proposed. The presented architecture in [15], is interfaced with a medium voltage grid with a voltage level of $4.8\mathrm{kV}$. It supports the grid functionality since it can allow bidirectional power flow and can reduce during the EV charging the conduction energy loss of the grid. However, in [7], DC-DC converters for high-power EV UFC stations have been presented. The semiconductor devices voltage ratings are reduced through splitting the DC input voltage. In addition, a modulation scheme named triangular current modulation is applied to achieve Zero Voltage Switching for all the switching devices. This accordingly increases the efficiency of the system. The converter in [7] can achieve an efficiency of $99.5\%$. To reduce the ripple content of the output current and achieve a high power density, multiple modules are parallel interleaved. In [2], reactive power operation is investigated using an offboard charging station. In [32], two different converter architectures for UF-EVC stations are presented. The first architecture is based on low-frequency isolation (non-isolated DC-DC converter), while the second approach is based on high-frequency isolation (galvanic isolated DC-DC converter). Technical evaluation for the two architectures is carried out where the pros and cons of each topology are highlighted. Besides, simulation results elaborating on the impact of the DC fast charging station on the grid are also provided in [32]. In [1], to realize medium-voltage UF-EVC stations, a multiport power converter has been proposed. A cascaded H-bridge is utilized at the grid side. Besides, to reduce the charging station effect on the grid, the battery energy storage elements are integrated in a split manner on the level of each submodule. Talking about the DC-DC conversion stage presented in [1], multiple Dual Half Bridge units are connected in parallel, where the multiport concept at the output side is achieved by selecting different submodule configurations. This is done to charge multiple EVs at the same time instant without the need for extra chargers. Operation modes, as well as the control techniques, have been addressed in [1].

In [33], a Full-Bridge Phase-Shifted DC-DC converter that combines the features of the double inductor rectifier and the conventional hybrid switching converter has been proposed for EV DC fast chargers. The principle of operation, as well as the characteristics and design specifications, are provided. The presented DC-DC converter in [33], can achieve both: zero voltage switching and zero current switching in the leading and the lagging legs, respectively. In [31], a medium-voltage high-power isolated DC-DC converter for EVs fast chargers have been presented. The employed DC-DC converter is a modular-based structure utilizing silicon carbide switching devices to convert a single-phase rectified input voltage of $2.4\mathrm{kV}$ to a variable DC output. It is a unidirectional converter that is connected in series from the input side and connected in parallel from the output side.

In [34], the AC-DC and DC-DC stages of an EV charger have been studied. The DC-DC stage utilizes interleaved DC-DC converters to be connected to a high-voltage network $\left(13.8\mathrm{kV}\right)$. The interleaved DC-DC converters are accompanied with several advantages that can be highlighted in lower input ripple and lower inductors cost and size. The charger presented in [34] allows for bidirectional power flow so that it can support renewable energy sources and smart grid applications. It is suitable for a high-power fast charger of $400\mathrm{kW}$ with an EV battery with a rated voltage level of $500\mathrm{V}.$ However, in [35], a fast charger that is based on a single stage has been proposed. In other words, the power factor correction and zero voltage switching are achieved in one single AC-DC stage. The charger utilizes DAB units that are connected in series and parallel at the input and output sides, respectively. The use of one stage resulted in the DC link capacitor elimination, allowing for higher efficiency and higher power density to be achieved. In [18], a fast-charging system for EVs is proposed. The system consists of a $15\mathrm{kW}$ multimodule converter that utilizes a three-phase rectifier and a Full-Bridge DC-DC converter. Multiple units are used in a modular manner and connected in parallel at the input side and series or parallel at the output side. To clarify, modules are connected in IPOS to provide a higher voltage that reaches up to $\left(1000\mathrm{V}\right)$ or connected in IPOP to provide higher output current at a voltage level of $\left(500\mathrm{V}\right)$.

In [36], a power converter that interfaces a three-phase medium-voltage grid with EV batteries has been proposed. The AC-DC stage utilizes a cascaded H-Bridge converter, in which the battery energy storage systems are integrated in a split manner to reduce the effect of the charging station on the grid. Modular DC-DC converters utilizing the Full-Bridge Phase-Shifted topology are employed to charge the EV battery. The DC-DC converters are connected in parallel to provide high currents.

According to the latest technical specifications for fast charging stations, the charging process can be done through a $400\mathrm{VAC}$ or it can be done through a medium voltage grid supply that ranges from $10$ to $40\mathrm{kV}$ to avoid high current and high losses. Assuming a fast charger rated at $350\mathrm{kW}$ and EV battery rated at a high voltage level $\left(400–920\mathrm{V}\right)$. Different scenarios of the mentioned specifications result in the four different architectures of the multimodule DC-DC converters, which are ISOS, IPOP, ISOP, and IPOS. In this paper, these scenarios are discussed along with the control strategy for each architecture. To support the power converter controller design, the Small-Signal Model (SSM) for the four architectures is studied in detail. Moreover, to ensure equal power sharing among the employed modules, the control scheme for the four architectures is investigated. Moreover, a generalized SSM for any multimodule DC-DC converters’ connection, including Input-Series Input-Parallel Output-Series Output-Parallel (ISIP-OSOP), is provided. This is achieved by studying the SSM of Full-Bridge Phase-Shift (FB-PS) DC-DC converter, two-module IPOS, three-module ISOP, and four-module Input-Series Input-Parallel Output-Series (ISIPOS) presented in [37,38,39,40,41,42], respectively. After deriving the generalized model, the model is verified with the multimodule configurations presented in [38,39,40,41,42].

The main contribution of the paper can be summarized as follows:

• A generalized model for the multimodule ISIP-OSOP DC-DC converter is provided. It is worth mentioning that the work presented in [40] is extended to include the SSM as well as the control schemes for the three other multimodule configurations, which are ISOS, IPOP, and IPOS. In addition to a generalized SSM applicable for all the basic architectures for multimodule DC-DC converters.
• Detailed SSM for the four architectures of the multimodule converter, which are ISOS, ISOP, IPOP, and IPOS, is provided in detail.
• The control strategy to guarantee uniform power distribution among the modules is studied. The strategies are based on current control Reflex Charging (RC) considering high-power-level UFC stations.

This paper is organized such that: Section 2 presents the ISOS circuit configuration as well as the ISOS SSM. Section 3 presents the ISOP multimodule DC-DC converter referring to the work that has been previously published in [40]. Section 4 and Section 5 provide the circuit configuration and SSM for the IPOP and IPOS DC-DC converter, respectively. Section 6 addresses the generalized SSM for the ISIP-OSOP multimodule DC-DC converter along with its verification. Section 7 provides the control scheme for the four architectures to achieve equal power sharing among the employed modules. Finally, Section 8 presents the conclusion.

2. Input-Series Output-Series (ISOS) DC-DC Converter

In this section, the ISOS DC-DC converter circuit diagram, as well as the ISOS DC-DC converter SSM, are discussed in detail. The analysis carried out in this section, as well as the following sections, is not restricted to unidirectional power flow and can be applied for bidirectional power flow. In addition, a three-module based DAB topology is considered. Such configurations are employed when galvanic isolation is required.

To reduce the SSM in terms of complexity, it is assumed that all the modules of the ISOS, ISOP, IPOP, and IPOS DC-DC converter have an equal turns ratio and effective duty cycle as well as the same inductor and capacitor values. In other words, the SSM for the four architectures is derived, assuming ideal conditions. The SSM, carried out in this section and the following sections, is used in Section 7 to support the controller design for each configuration.

2.1. ISOS Circuit Diagram

An ISOS DC-DC converter is employed in high input voltage and high output voltage applications [43]. The ISOS converter configuration is shown in Figure 1, where modules are connected in series at the input and the output sides. The ISOS DC-DC converter shown in Figure 1 is needed for a high step-up ratio. This configuration is employed in high-voltage applications where neither the input side voltage nor the output side voltage is within the semiconductor devices voltage ratings. Such configuration enables low-voltage rating switches utilization.

By ensuring equal Input Voltage Sharing (IVS) and Output Voltage Sharing (OVS), the input voltage per module is $\frac{{\mathrm{V}}_{\mathrm{in}}}{3}$, and the output voltage per module is $\frac{{\mathrm{V}}_{\mathrm{o}}}{3}$. In which, ${\mathrm{V}}_{\mathrm{in}}$ and ${\mathrm{V}}_{\mathrm{o}}$ are the ISOS input voltage and ISOS output voltage, respectively. The features of the ISOS converter can be summarized in reduced voltage stress as well as the reduced power level per module, which facilitates the design of the converter. In the following Section, the SSM of the ISOS converter is studied using the FB-PS DC-DC converter.

2.2. ISOS Small-Signal Analysis

The SSM for the ISOS converter shown in Figure 2 is derived, using the SSM presented in [37].

Since the input voltage per module is $\frac{V_{in}}{3}$, and the output voltage per module is $\frac{V_o}{3}$, accordingly, the load resistance per module is $\frac{R}{3}$. Therefore, ${\widehat{d}}_{ij}$ and ${\widehat{d}}_{v\mathrm{j}}$, which are the effect of changing the filter inductor current and the effect of changing the input voltage on the duty cycle modulation, as well as $I_{eq}$ presented in Figure 2 can be expressed as follows, where the subscript $j=1,2, \mathrm{and} 3$:

$${\widehat{d}}_{ij}=-\frac{12 L_{lk}{f}_s}{K{V}_{in}}{\widehat{i}}_{Lj}$$

(1)

Equation (1) can be rewritten in terms of $R_d$, where; $R_d=\frac{4L_{lk}{f}_s}{k^2}$ as:

$${\widehat{d}}_{ij}=-\frac{3K{R}_d}{V_{in}}{\widehat{i}}_{Lj}$$

(2)

$${\widehat{d}}_{vj}=\frac{36 L_{lk}{f}_s{D}_{eff}}{k^{2}R{V}_{in}}{\widehat{v}}_{cdj}$$

(3)

Similarly, Equation (3) can be rewritten as:

$${\widehat{d}}_{vj}=\frac{9 R_d{D}_{eff}}{R{V}_{in}}{\widehat{v}}_{cdj}$$

(4)

$$I_{eq}=\frac{V_{in}}{KR}$$

(5)

The following equations are obtained from Figure 2:

$$\{\begin{array}{c}\begin{array}{c}\frac{D_{eff}}{K}{\widehat{v}}_{cd1}+\frac{V_{in}}{3K}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)=sL{\widehat{i}}_{L1}+{\widehat{v}}_{out1}\\ \frac{D_{eff}}{K}{\widehat{v}}_{cd2}+\frac{V_{in}}{3K}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)=sL{\widehat{i}}_{L2}+{\widehat{v}}_{out2}\\ \frac{D_{eff}}{K}{\widehat{v}}_{cd3}+\frac{V_{in}}{3K}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)=sL{\widehat{i}}_{L3}+{\widehat{v}}_{out3}\end{array}\end{array}$$

(6)

$$\{\begin{array}{c}\begin{array}{c}\frac{K}{D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{cd1}\right)=I_{eq}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)+{\widehat{i}}_{L1}\\ \frac{K}{D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{cd2}\right)=I_{eq}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)+{\widehat{i}}_{L2}\\ \frac{K}{D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{cd3}\right)=I_{eq}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)+{\widehat{i}}_{L3}\end{array}\end{array}$$

(7)

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L1}=sC{\widehat{v}}_{out1}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L2}=sC{\widehat{v}}_{out2}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L3}=sC{\widehat{v}}_{out3}+\frac{{\widehat{v}}_{out}}{R}\end{array}\end{array}$$

(8)

Summing Equations in (8) would result in (9):

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}={\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)$$

(9)

where

$${\widehat{v}}_{out1}+{\widehat{v}}_{out2}+{\widehat{v}}_{out3}={\widehat{v}}_{out}$$

(10)

$${\widehat{v}}_{cd1}+{\widehat{v}}_{cd2}+{\widehat{v}}_{cd3}={\widehat{v}}_{in}\mathrm{or}{{\displaystyle \sum }}_{j=1}^3{\widehat{v}}_{cdj}={\widehat{v}}_{in}$$

(11)

2.2.1. Control-to-Output Voltage Transfer Function

The output voltage and the duty cycle relationship is found by summing up the Kirchhoff’s voltage law (KVL) Equations in (6), assuming ${\widehat{v}}_{in}=0$, and ${\widehat{d}}_k=0$, where $k=1,2,$ and $3$, and $k\ne j$, and substituting (2), (4), (9)–(11).

$$\frac{V_{in}}{3K}{\widehat{d}}_1-R_d\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)\right)=sL\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)\right)+{\widehat{v}}_{out}$$

(12)

Simplifying (12) would result in (13):

$$G_{vd}=\frac{{\widehat{v}}_{out}}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{3K}}{\left(s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3R_d}{R}+1\right)}$$

(13)

2.2.2. Control-To-Filter Inductor Current Transfer Function

The filter inductor current and the duty cycle relationship is found by substituting ${\widehat{v}}_{out}$ in (12) in terms of ${\widehat{i}}_{Lj}$ using (9), and considering the same assumptions as in Section 2.2.1.

$$\frac{V_{in}}{2K}{\widehat{d}}_1-R_d{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}=sL{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}+\frac{{{\displaystyle \sum }}_{j=1}^3{\widehat{i}}_{Lj}}{\left(sC+\frac{3}{R}\right)}$$

(14)

Simplifying (14) would result in (15):

$$G_{id}=\frac{{\widehat{i}}_L}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{3K}\left(3+sRC\right)}{R\left(s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3}{R}+1\right)}$$

(15)

2.2.3. Control-To-Module Input Voltage Transfer Function

The module input voltage and the duty cycle relationship is found as follows:

Subtracting the 3rd Equation in (6) from the 1st Equation in (6):

$$\frac{D_{eff}}{K}\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)+\frac{V_{in}}{3K}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1-{\widehat{d}}_{i2}-{\widehat{d}}_{v2}-{\widehat{d}}_2\right)=sL\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)+{\widehat{v}}_{out1}-{\widehat{v}}_{out2}$$

(16)

Substituting (2) and (4) in (16):

$$\frac{D_{eff}}{K}\left(1+\frac{3R_d}{R}\right)\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)+\frac{V_{in}}{3K}\left({\widehat{d}}_1-{\widehat{d}}_2\right)=\left(sL+R_d\right)\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)+{\widehat{v}}_{out1}-{\widehat{v}}_{out2}$$

(17)

Subtracting the 2nd Equation in (7) from the 1st Equation in (7), and substituting (5):

$$\frac{K}{D_{eff}}\left(s{C}_d{\widehat{v}}_{cd2}-s{C}_d{\widehat{v}}_{cd1}\right)=\frac{V_{in}}{KR}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1-{\widehat{d}}_{i2}-{\widehat{d}}_{v2}-{\widehat{d}}_2\right)+\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)$$

(18)

Substituting (2) and (4) in (18) and rearranging the equation:

$$\left(\frac{3R_d}{R}-1\right)\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)=\frac{V_{in}}{KR}\left({\widehat{d}}_1-{\widehat{d}}_2\right)+\left(\frac{9R_d{D}_{eff}}{K{R}^2}+\frac{sK{C}_d}{D_{eff}}\right)\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)$$

(19)

Substituting ${\widehat{v}}_{out}$ by ${\widehat{v}}_{out1}+{\widehat{v}}_{out2}+{\widehat{v}}_{out3}$ in (8):

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L1}=\left(sC+\frac{1}{R}\right){\widehat{v}}_{out1} +\frac{1}{R}{\widehat{v}}_{out2}+\frac{1}{R}{\widehat{v}}_{out3}\\ {\widehat{i}}_{L2}=\frac{1}{R}{\widehat{v}}_{out1} +\left(sC+\frac{1}{R}\right){\widehat{v}}_{out2}+\frac{1}{R}{\widehat{v}}_{out3}\\ {\widehat{i}}_{L3}=\frac{1}{R}{\widehat{v}}_{out1} +\frac{1}{R}{\widehat{v}}_{out2}+\left(sC+\frac{1}{R}\right){\widehat{v}}_{out3}\end{array}\end{array}$$

(20)

The three Equations in (20) can be represented as:

$$\left[\begin{array}{c}{\widehat{i}}_{L1}\\ {\widehat{i}}_{L2}\\ {\widehat{i}}_{L3}\end{array}\right]=\left[\begin{array}{ccc}sC+\frac{1}{R}& \frac{1}{R}& \frac{1}{R}\\ \frac{1}{R}& sC+\frac{1}{R}& \frac{1}{R}\\ \frac{1}{R}& \frac{1}{R}& sC+\frac{1}{R}\end{array}\right]\left[\begin{array}{c}\begin{array}{c}{\widehat{v}}_{out1}\\ {\widehat{v}}_{out2}\\ {\widehat{v}}_{out3}\end{array}\end{array}\right]$$

(21)

Solving for the output voltages in (21) would give:

$$\{\begin{array}{c}\begin{array}{c}{\widehat{v}}_{out1}=g_1{\widehat{i}}_{L1}-g_2\left({\widehat{i}}_{L2}+{\widehat{i}}_{L3}\right)\\ {\widehat{v}}_{out2}=g_1{\widehat{i}}_{L2}-g_2\left({\widehat{i}}_{L1}+{\widehat{i}}_{L3}\right)\\ {\widehat{v}}_{out3}=g_1{\widehat{i}}_{L3}-g_2\left({\widehat{i}}_{L1}+{\widehat{i}}_{L2}\right)\end{array}\end{array}$$

(22)

where

$$g_1=\frac{2+sRC}{s^{2}R{C}^2+3sC}\hspace{1em}\mathrm{and}\hspace{1em}{g}_2=\frac{1}{s^{2}R{C}^2+3sC}$$

Accordingly;

$${\widehat{v}}_{out1}-{\widehat{v}}_{out2}=\left(g_1+g_2\right)\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)$$

(23)

Substituting (23) in (17):

$$\frac{D_{eff}}{K}\left(1+\frac{3R_d}{R}\right)\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)+\frac{V_{in}}{3K}\left({\widehat{d}}_1-{\widehat{d}}_2\right)=\left(sL+R_d+g_1+g_2\right)\left({\widehat{i}}_{L1}-{\widehat{i}}_{L2}\right)$$

(24)

Substituting (19) in (24):

$$\begin{array}{c}\frac{D_{eff}}{K}\left(1+\frac{3R_d}{R}\right)\left(\frac{3R_d}{R}-1\right)\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)+\frac{V_{in}}{3K}\left(\frac{3R_d}{R}-1\right)\left({\widehat{d}}_1-{\widehat{d}}_2\right)=\\ \frac{3\left(sL+R_d+g_1+g_2\right)}{KR}\left({\widehat{d}}_1-{\widehat{d}}_2\right)+\left(sL+R_d+g_1+g_2\right)\left(\frac{9R_d{D}_{eff}}{K{R}^2}+\frac{sK{C}_d}{D_{eff}}\right)\left({\widehat{v}}_{cd1}-{\widehat{v}}_{cd2}\right)\end{array}$$

(25)

Simplifying (25) would result in (26):

$$\left({\widehat{v}}_{cd2}-{\widehat{v}}_{cd1}\right)=\left(-\frac{D_{eff}\left(R^2\frac{V_{in}}{2}+2R{V}_{in}\left(g_1+g_2\right)+2sLR{V}_{in}\right)}{\begin{array}{c}{R}^2{D}_{eff}^2+16R_d{D}_{eff}^2\left(g_1+g_2\right)+16sL{R}_d{D}_{eff}^2\\ +K^2{R}^2{C}_d\left(s\left(R_d+g_1+g_2\right)+s^{2}L\right)\end{array}}\right)\left({\widehat{d}}_2-{\widehat{d}}_1\right)$$

(26)

Equation (26) can be written as:

$$\left({\widehat{v}}_{cd2}-{\widehat{v}}_{cd1}\right)=A\left(s\right)\left({\widehat{d}}_2-{\widehat{d}}_1\right)$$

(27)

where

$$A\left(s\right)=-\left(\frac{D_{eff}\left(R^2\frac{V_{in}}{2}+2R{V}_{in}\left(g_1+g_2\right)+2sLR{V}_{in}\right)}{\begin{array}{c}{R}^2{D}_{eff}^2+16R_d{D}_{eff}^2\left(g_1+g_2\right)+16sL{R}_d{D}_{eff}^2\\ +K^2{R}^2{C}_d\left(s\left(R_d+g_1+g_2\right)+s^{2}L\right)\end{array}}\right)$$

Rearranging (27) would result in (28):

$${\widehat{v}}_{cd2}={\widehat{v}}_{cd1}+A\left(s\right)\left({\widehat{d}}_2-{\widehat{d}}_1\right)$$

(28)

Assuming ${\widehat{v}}_{in}=0$, hence ${\widehat{v}}_{cd1}+{\widehat{v}}_{cd2}+{\widehat{v}}_{cd3}=0$,

Equation (28) can be generalized as follows:

$${\widehat{v}}_{cdj}={\widehat{v}}_{cd1}+A\left(s\right)\left({\widehat{d}}_j-{\widehat{d}}_1\right)$$

(29)

Setting ${\widehat{v}}_{in}=0$, and substituting (29) in (11) would result in:

$${\displaystyle \sum }_{j=1}^3{\widehat{v}}_{cd1}+A\left(s\right)\left({\widehat{d}}_j-{\widehat{d}}_1\right)=0$$

(30)

$$3{\widehat{v}}_{cd1}-3A\left(s\right){\widehat{d}}_1+{\displaystyle \sum }_{j=1}^{3}A\left(s\right){\widehat{d}}_j=0$$

(31)

Therefore,

$${\widehat{v}}_{cd1}=A\left(s\right){\widehat{d}}_1+\frac{A\left(s\right)}{3}{\displaystyle \sum }_{j=1}^3{\widehat{d}}_j$$

(32)

Substituting (32) in (29) would result in:

$${\widehat{v}}_{cdj}=A\left(s\right){\widehat{d}}_j+\frac{A\left(s\right)}{3}{\displaystyle \sum }_{j=1}^3{\widehat{d}}_j$$

(33)

Presenting (33) in a matrix form would give:

$$\left[\begin{array}{c}{\widehat{v}}_{cd1}\\ {\widehat{v}}_{cd2}\\ {\widehat{v}}_{cd3}\end{array}\right]=\left[\begin{array}{ccc}\frac{2A\left(s\right)}{3}& \frac{-A\left(s\right)}{3}& \frac{-A\left(s\right)}{3}\\ \frac{-A\left(s\right)}{3}& \frac{2A\left(s\right)}{3}& \frac{-A\left(s\right)}{3}\\ \frac{-A\left(s\right)}{3}& \frac{-A\left(s\right)}{3}& \frac{2A\left(s\right)}{3}\end{array}\right]\left[\begin{array}{c}{\widehat{d}}_1\\ {\widehat{d}}_2\\ {\widehat{d}}_3\end{array}\right]$$

(34)

2.2.4. Converter Output Impedance

As studied in the SSM presented in [39,40], the ISOS converter output impedance can be found by modifying (8), such that:

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L1}+{\widehat{i}}_{out}=sC{\widehat{v}}_{out1}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L2}+{\widehat{i}}_{out}=sC{\widehat{v}}_{out2}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L3}+{\widehat{i}}_{out}=sC{\widehat{v}}_{out3}+\frac{{\widehat{v}}_{out}}{R}\end{array}\end{array}$$

(35)

Accordingly, Equation (9) is modified as follows:

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}={\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)-3{\widehat{i}}_{out}$$

(36)

The output voltage and the output current relationship is found by assuming ${\widehat{v}}_{in}=0$, and ${\widehat{d}}_j=0,j=1,2,\mathrm{and}3$, summing the KVL Equations in (6), and substituting (2), (4), (10), (11), and (36).

$$\left(\left(sL+R_d\right)\left(sC+\frac{3}{R}\right)+1\right){\widehat{v}}_{out}=3\left(R_d+sL\right){\widehat{i}}_{out}$$

(37)

Simplifying (37) would result in (38):

$$Z_{out}=\frac{{\widehat{v}}_{out}}{{\widehat{i}}_{out}}=\frac{3\left(R_d+sL\right)}{s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3R_d}{R}+1}$$

(38)

2.2.5. Converter Gain

The output voltage and the input voltage relationship is found by assuming ${\widehat{d}}_j=0,j=1,2,\mathrm{and}3$, summing the KVL Equations in (6), and substituting (2), (4), (9)–(11) in the added equation.

$$\frac{D_{eff}}{K}\left(1+\frac{R_d}{3R}\right){\widehat{v}}_{in}=\left(\frac{\left(sL+R_d\right)\left(sRC+1\right)}{R}+3\right){\widehat{v}}_{out}$$

(39)

Simplifying (39) would result in (40):

$$G_{vg}=\frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}=\frac{\frac{D_{eff}}{K}\left(1+\frac{R_d}{3R}\right)}{s^{2}LC+s\left(\frac{L}{R}+R_{d}C\right)+\frac{R_d}{R}+3}$$

(40)

3. Input-Series Output-Parallel (ISOP) DC-DC Converter

All the related work in for the ISOP DC-DC converter, including system configuration, detailed SSM, and control strategy, has been previously published in [40].

4. Input-Parallel Output-Parallel (IPOP) DC-DC Converter

In this section, the IPOP DC-DC converter circuit diagram, as well as the IPOP DC-DC converter SSM, are discussed in detail.

4.1. IPOP Circuit Diagram

IPOP DC-DC converters are employed in high-current and high-power applications [44]. The IPOP converter configuration is shown in Figure 3, where the modules connected in parallel at the input and the output sides. This architecture is employed when the input side and the output side current are higher than the semiconductor devices’ current rating.

By ensuring equal Input Current Sharing (ICS) and Output Current Sharing (OCS), the input current per module is $\frac{I_{in}}{3}$, and the output current per module is $\frac{I_o}{3}$. In which, $I_{in}$ and $I_o$, are the IPOP input current and the IPOP output current, respectively. The merits of the IPOP DC-DC converter can be highlighted in more accessible semiconductor devices selection due to the low current stress per module. Besides, a higher switching frequency can be achieved and accordingly lowering the size of the magnetic components.

4.2. IPOP Small-Signal Analysis

The SSM for the IPOP converter shown in Figure 4 is derived using the SSM presented in [37].

Since the input current per module is $\frac{I_{in}}{3}$, and the output current per module is $\frac{I_o}{3}$, accordingly, the load resistance per module is $3R$. Therefore, ${\widehat{d}}_{ij}$, ${\widehat{d}}_{v\mathrm{j}}$ and $I_{eq}$ presented in Figure 4 can be expressed as follows, where the subscript $j=1,2, and 3$:

$${\widehat{d}}_{ij}=-\frac{4 L_{lk}{f}_s}{K{V}_{in}}{\widehat{i}}_{Lj}$$

(41)

Rewriting (41) in terms of $R_d$ would result in:

$${\widehat{d}}_{ij}=-\frac{K{R}_d}{V_{in}}{\widehat{i}}_{Lj}$$

(42)

$${\widehat{d}}_{vj}=\frac{4L_{lk}{f}_s{D}_{eff}}{3 k^{2}R{V}_{in}}{\widehat{v}}_{in}$$

(43)

Similarly, rewriting (43) in terms of $R_d$ would result in:

$${\widehat{d}}_{vj}=\frac{R_d{D}_{eff}}{3 R{V}_{in}}{\widehat{v}}_{in}$$

(44)

$$I_{eq}=\frac{V_{in}}{3KR}$$

(45)

The following equations are obtained from Figure 4:

$$\{\begin{array}{c}\begin{array}{c}\frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)=sL{\widehat{i}}_{L1}+{\widehat{v}}_{out}\\ \frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)=sL{\widehat{i}}_{L2}+{\widehat{v}}_{out}\\ \frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)=sL{\widehat{i}}_{L3}+{\widehat{v}}_{out}\end{array}\end{array}$$

(46)

$$\{\begin{array}{c}\begin{array}{c}\frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)+{\widehat{i}}_{L1}\\ \frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)+{\widehat{i}}_{L2}\\ \frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)+{\widehat{i}}_{L3}\end{array}\end{array}$$

(47)

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}={\widehat{v}}_{out}\left(sC+\frac{1}{R}\right)$$

(48)

4.2.1. Control-To-Output Voltage Transfer Function

The output voltage and the duty cycle relationship are found by summing up the KVL equations in (46), considering the same assumptions as in Section 2.2.1, and substituting (42), (44), and (48).

$$\frac{V_{in}}{K}\left(-\frac{K{R}_d}{V_{in}}\left({\widehat{v}}_{out}\left(sC+\frac{1}{R}\right)\right)+{\displaystyle \sum }_{j=1}^3\frac{R_d{D}_{eff}}{3 R{V}_{in}}{\widehat{v}}_{in}+{\widehat{d}}_1\right)=sL\left({\widehat{v}}_{out}\left(sC+\frac{1}{R}\right)\right)+3{\widehat{v}}_{out}$$

(49)

Simplifying (49) would result in (50):

$$G_{vd}=\frac{{\widehat{v}}_{out}}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{K}}{s^{2}LC+s\left(\frac{L}{R}+R_{d}C\right)+\frac{R_d}{R}+3}$$

(50)

4.2.2. Control-To-Filter Inductor Current Transfer Function

The filter inductor current and the duty cycle relationship is found by substituting ${\widehat{v}}_{out}$ in terms of ${\widehat{i}}_{Lj}$ using (48) in (49), and considering the same assumptions as in Section 2.2.1.

$$\frac{V_{in}}{K}{\widehat{d}}_1-R_d{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}=sL{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}+\frac{3R}{sRC+1}{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}$$

(51)

Simplifying (51) would result in (52):

$$G_{id}=\frac{{\widehat{i}}_L}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{K}\left(1+sRC\right)}{R\left(s^{2}LC+s\left(\frac{L}{R}+R_{d}C\right)+\frac{R_d}{R}+3\right)}$$

(52)

4.2.3. Control-To-Module Filter Inductor Current Transfer Function

The module filter inductor current and the duty cycle relationship is found by substituting (42), (44), and (48) in (46) assuming ${\widehat{v}}_{in}=0$.

$$\{\begin{array}{c}\begin{array}{c}\left(sL+R_d+\frac{R}{sRC+1}\right){\widehat{i}}_{L1}+\frac{R}{sRC+1}{\widehat{i}}_{L2}+\frac{R}{sRC+1}{\widehat{i}}_{L3}=\frac{V_{in}}{K}{\widehat{d}}_1\\ \frac{R}{sRC+1}{\widehat{i}}_{L1}+\left(sL+R_d+\frac{R}{sRC+1}\right){\widehat{i}}_{L2}+\frac{R}{sRC+1}{\widehat{i}}_{L3}=\frac{V_{in}}{K}{\widehat{d}}_2\\ \frac{R}{sRC+1}{\widehat{i}}_{L1}+\frac{R}{sRC+1}{\widehat{i}}_{L2}+\left(sL+R_d+\frac{R}{sRC+1}\right){\widehat{i}}_{L3}=\frac{V_{in}}{K}{\widehat{d}}_3\end{array}\end{array}$$

(53)

Subtracting the 2nd Equation in (53) from the 1st Equation in (53):

$${\widehat{i}}_{L2}={\widehat{i}}_{L1}-\frac{V_{in}}{K\left(sL+R_d\right)}\left({\widehat{d}}_1-{\widehat{d}}_2\right)$$

(54)

Similarly, subtracting the 3rd Equation in (53) from the 1st Equation in (53):

$${\widehat{i}}_{L3}={\widehat{i}}_{L1}-\frac{V_{in}}{K\left(sL+R_d\right)}\left({\widehat{d}}_1-{\widehat{d}}_3\right)$$

(55)

Substituting (54) and (55), in the first Equation in (53):

$$\begin{array}{c}\left(sL+R_d+\frac{3R}{sRC+1}\right){\widehat{i}}_{L1}=\\ \frac{V_{in}}{K}\left[\left(\frac{2R}{\left(sL+R_d\right)\left(sRC+1\right)}+1\right){\widehat{d}}_1-\frac{R}{\left(sL+R_d\right)\left(sRC+1\right)}{\widehat{d}}_2-\frac{R}{\left(sL+R_d\right)\left(sRC+1\right)}{\widehat{d}}_3\right]\end{array}$$

(56)

Rearranging (56), the following equation is obtained:

$${\widehat{i}}_{L1}=A\left(s\right){\widehat{d}}_1+B\left(s\right){\widehat{d}}_2+B\left(s\right){\widehat{d}}_3$$

(57)

where

$$A\left(s\right)=\frac{V_{in}\left(s^{2}LCR+s\left(L+C{R}_{d}R\right)+R_d+2R\right)}{K\left(sL+R_d\right)\left(s^{2}LCR+s\left(L+C{R}_{d}R\right)+3R\right)}$$

(58)

$$B\left(\mathrm{s}\right)=\frac{-V_{in}R}{K\left(sL+R_d\right)\left(s^{2}LCR+s\left(L+C{R}_{d}R\right)+3R\right)}$$

(59)

Similar steps can be done for the filter inductor current for module 2 and module 3 such that:

$$\{\begin{array}{c}{\widehat{i}}_{L1}=A\left(s\right){\widehat{d}}_1+B\left(s\right){\widehat{d}}_2+B\left(s\right){\widehat{d}}_3\\ {\widehat{i}}_{L2}=B\left(s\right){\widehat{d}}_1+A\left(s\right){\widehat{d}}_2+B\left(s\right){\widehat{d}}_3\\ {\widehat{i}}_{L3}=B\left(s\right){\widehat{d}}_1+B\left(s\right){\widehat{d}}_2+A\left(s\right){\widehat{d}}_3\end{array}$$

(60)

4.2.4. Converter Output Impedance

Similarly, the IPOP converter output impedance can be found by modifying (48) such that:

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}+{\widehat{i}}_{out}={\widehat{v}}_{out}\left(\frac{sRC+1}{R}\right)$$

(61)

The output voltage and the output current relationship is found by considering the same assumptions as in Section 2.2.4, summing Equations in (46), and substituting (42), (44), and (61).

$$-R_d\left({\widehat{v}}_{out}\left(\frac{sRC+1}{R}\right)-{\widehat{i}}_{out}\right)=sL\left({\widehat{v}}_{out}\left(\frac{sRC+1}{R}\right)-{\widehat{i}}_{out}\right)+3{\widehat{v}}_{out}$$

(62)

Simplifying (62) would result in (63):

$$Z_{out}=\frac{{\widehat{v}}_{out}}{{\widehat{i}}_{out}}=\frac{\left(R_d+sL\right)}{s^{2}LC+s\left(\frac{L}{R}+R_{d}C\right)+\frac{R_d}{R}+3}$$

(63)

4.2.5. Converter Gain

The output voltage and the input voltage relationship is found by assuming ${\widehat{d}}_j=0,j=1,2,\mathrm{and}3$, summing Equations in (46), and substituting (42), (44), and (48) in the added equation.

$$\frac{3D_{eff}}{K}\left(1+\frac{R_d}{3R}\right){\widehat{v}}_{in}=\left(\frac{\left(sL+R_d\right)\left(sRC+1\right)}{R}+3\right){\widehat{v}}_{out}$$

(64)

Simplifying (64) would result in (65):

$$G_{vg}=\frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}=\frac{\frac{3D_{eff}}{K}\left(1+\frac{R_d}{3R}\right)}{s^{2}LC+s\left(\frac{L}{R}+R_{d}C\right)+\frac{R_d}{R}+3}$$

(65)

5. Input-Parallel Output-Series (IPOS) DC-DC Converter

In this section, the IPOS DC-DC converter circuit diagram, as well as the IPOS DC-DC converter SSM, are discussed in detail.

5.1. IPOS Circuit Diagram

IPOS DC-DC converters are employed in high input current and high output voltage applications [38]. The IPOS converter configuration is shown in Figure 5, where modules are connected in parallel and series at the input side and the output side, respectively. The IPOS DC-DC converter shown in Figure 5 is required for a high step-up ratio. This architecture is utilized when the output side current is within the semiconductor devices’ current rating.

By ensuring equal ICS and OVS, the input current per module is $\frac{I_{in}}{3}$, and the output voltage per module is $\frac{V_o}{3}$. In which, $I_{in}$ and $V_o$, are the IPOS input current and the IPOS output voltage, respectively.

5.2. IPOS Small-Signal Analysis

The SSM for the IPOS converter shown in Figure 6 is derived using the SSM presented in [37].

Since the input current per module is $\frac{I_{in}}{3}$, and the output voltage per module is $\frac{V_o}{3}$, accordingly, the load resistance per module is $\frac{\mathrm{R}}{3}$. Therefore, ${\widehat{d}}_{ij}$, ${\widehat{d}}_{v\mathrm{j}}$ and $I_{eq}$ presented in Figure 6 can be expressed as follows, where the subscript $j=1,2, and 3$:

$${\widehat{d}}_{ij}=-\frac{4 L_{lk}{f}_s}{K{V}_{in}}{\widehat{i}}_{Lj}$$

(66)

Rewriting (66) in terms of $R_d$ would result in:

$${\widehat{d}}_{ij}=-\frac{K{R}_d}{V_{in}}{\widehat{i}}_{Lj}$$

(67)

$${\widehat{d}}_{vj}=\frac{12 L_{lk}{f}_s{D}_{eff}}{ k^{2}R{V}_{in}}{\widehat{v}}_{in}$$

(68)

Similarly, rewriting (68) in terms of $R_d$ would result in:

$${\widehat{d}}_{vj}=\frac{3 R_d{D}_{eff}}{ R{V}_{in}}{\widehat{v}}_{in}$$

(69)

$$I_{eq}=\frac{3 V_{in}}{KR}$$

(70)

The following equations are obtained from Figure 6:

$$\{\begin{array}{c}\begin{array}{c}\frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)=sL{\widehat{i}}_{L1}+{\widehat{v}}_{out1}\\ \frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)=sL{\widehat{i}}_{L2}+{\widehat{v}}_{out2}\\ \frac{D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)=sL{\widehat{i}}_{L3}+{\widehat{v}}_{out3}\end{array}\end{array}$$

(71)

$$\{\begin{array}{c}\begin{array}{c}\frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)+{\widehat{i}}_{L1}\\ \frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)+{\widehat{i}}_{L2}\\ \frac{K}{3D_{eff}}\left({\widehat{i}}_{in}-s{C}_d{\widehat{v}}_{in}\right)=I_{eq}\left({\widehat{d}}_{i3}+{\widehat{d}}_{v3}+{\widehat{d}}_3\right)+{\widehat{i}}_{L3}\end{array}\end{array}$$

(72)

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L1}=sC{\widehat{v}}_{out1}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L2}=sC{\widehat{v}}_{out2}+\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L3}=sC{\widehat{v}}_{out3}+\frac{{\widehat{v}}_{out}}{R}\end{array}\end{array}$$

(73)

Summing Equations in (73) would result in (74):

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}={\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)$$

(74)

where

$${\widehat{v}}_{out1}+{\widehat{v}}_{out2}+{\widehat{v}}_{out3}={\widehat{v}}_{out}$$

(75)

5.2.1. Control-To-Output Voltage Transfer Function

The output voltage and the duty cycle relationship is found by summing up Equations in (71), considering the same assumptions as in Section 2.2.1, and substituting (67), (69), and (74).

$$\frac{3D_{eff}}{K}{\widehat{v}}_{in}+\frac{V_{in}}{K}\left(-\frac{K{R}_d}{V_{in}}\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)\right)+{\displaystyle \sum }_{j=1}^3\frac{3 R_d{D}_{eff}}{ R{V}_{in}}{\widehat{v}}_{in}+{\widehat{d}}_1\right)=sL\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)\right)+{\widehat{v}}_{out}$$

(76)

Simplifying (76) would result in (77):

$$G_{vd}=\frac{{\widehat{v}}_{out}}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{K}}{s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3R_d}{R}+1}$$

(77)

5.2.2. Control-To-Filter Inductor Current Transfer Function

The filter inductor current and the duty cycle relationship is found by substituting ${\widehat{v}}_{out}$ in terms of ${\widehat{i}}_{Lj}$ using (74) in (76) and considering the same assumptions as in Section 2.2.1.

$$\frac{V_{in}}{K}{\widehat{d}}_1-R_d{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}=sL{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}+\frac{R}{sRC+3}{\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}$$

(78)

Simplifying (78) would result in (79):

$$G_{id}=\frac{{\widehat{i}}_L}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{K}\left(3+sRC\right)}{R\left(s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3R_d}{R}+1\right)}$$

(79)

5.2.3. Control-To-Module Filter Inductor Current Transfer Function

The filter inductor current and the duty cycle relationship is found by performing the following:

Substituting (75) in (76):

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L1}=\left(sC+\frac{1}{R}\right){\widehat{v}}_{out1} +\frac{1}{R}{\widehat{v}}_{out2}+\frac{1}{R}{\widehat{v}}_{out3}\\ {\widehat{i}}_{L2}=\frac{1}{R}{\widehat{v}}_{out1} +\left(sC+\frac{1}{R}\right){\widehat{v}}_{out2}+\frac{1}{R}{\widehat{v}}_{out3}\\ {\widehat{i}}_{L3}=\frac{1}{R}{\widehat{v}}_{out1} +\frac{1}{R}{\widehat{v}}_{out2}+\left(sC+\frac{1}{R}\right){\widehat{v}}_{out3}\end{array}\end{array}$$

(80)

Rewriting (80) in terms of the output voltages:

$$\{\begin{array}{c}\begin{array}{c}{\widehat{v}}_{out1}=g_1{\widehat{i}}_{L1}-g_2{\widehat{i}}_{L2}-g_2{\widehat{i}}_{L3}\\ {\widehat{v}}_{out2}=g_2{\widehat{i}}_{L1}-g_1{\widehat{i}}_{L2}-g_2{\widehat{i}}_{L3}\\ {\widehat{v}}_{out3}=g_2{\widehat{i}}_{L1}-g_2{\widehat{i}}_{L2}-g_1{\widehat{i}}_{L3}\end{array}\end{array}$$

(81)

where

$$g_1=\frac{2+sRC}{S^2{C}^{2}R+3sC} g_2=\frac{1}{S^2{C}^{2}R+3sC}$$

(82)

Rewriting (81) in a matrix form:

$$\left[\begin{array}{c}{\widehat{v}}_{out1}\\ {\widehat{v}}_{out2}\\ {\widehat{v}}_{out3}\end{array}\right]=\left[\begin{array}{ccc}{g}_1& -g_2& -g_2\\ -g_2& g_1& -g_2\\ -g_2& -g_2& g_1\end{array}\right]\left[\begin{array}{c}{\widehat{i}}_{L1}\\ {\widehat{i}}_{L2}\\ {\widehat{i}}_{L3}\end{array}\right]$$

(83)

Substituting (67), (69), and (81) in (71) and assuming ${\widehat{v}}_{in}=0$ would result in:

$$\{\begin{array}{c}\begin{array}{c}\frac{V_{in}}{K}{\widehat{d}}_1=\left(sL+R_d+g_1\right){\widehat{i}}_{L1}-g_2{\widehat{i}}_{L2}-g_2{\widehat{i}}_{L3}\\ \frac{V_{in}}{K}{\widehat{d}}_2=-g_2{\widehat{i}}_{L1}+\left(sL+R_d+g_1\right){\widehat{i}}_{L2}-g_2{\widehat{i}}_{L3}\end{array}\\ \frac{V_{in}}{K}{\widehat{d}}_3=-g_2{\widehat{i}}_{L1}-g_2{\widehat{i}}_{L2}+\left(sL+R_d+g_1\right){\widehat{i}}_{L3}\end{array}$$

(84)

Rearranging (84), the control-to-module filter inductor current can be represented as:

$$\left[\begin{array}{c}{\widehat{d}}_1\\ {\widehat{d}}_2\\ {\widehat{d}}_3\end{array}\right]=\left[\begin{array}{ccc}{g}_3& g_4& g_4\\ g_4& g_3& g_4\\ g_4& g_4& g_3\end{array}\right]\left[\begin{array}{c}{\widehat{i}}_{L1}\\ {\widehat{i}}_{L2}\\ {\widehat{i}}_{L3}\end{array}\right]$$

(85)

where

$$\mathrm{S}{g}_3=\frac{V_{in}\left(sL+R_d+g_1-g_2\right)}{K\left(g_1^2-g_1{g}_2+2g_1{g}_5-2g_2^2-g_2{g}_5+g_5^2\right)}$$

(86)

$$g_4=\frac{V_{in}{g}_2}{K\left(g_1^2-g_1{g}_2+2g_1{g}_5-2g_2^2-g_2{g}_5+g_5^2\right)}$$

(87)

$$g_5=sL+R_d$$

(88)

5.2.4. Converter Output Impedance

Similarly, the IPOS converter output impedance can be found by modifying (74) such that:

$${\displaystyle \sum }_{j=1}^3{\widehat{i}}_{Lj}+{\widehat{i}}_{out}={\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)$$

(89)

The output voltage and the output current relationship is found by considering the same assumptions as in Section 2.2.4, summing Equations in (71), and substituting (67), (69), (75) and (89).

$$-R_d\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)-{\widehat{i}}_{out}\right)=sL\left({\widehat{v}}_{out}\left(sC+\frac{3}{R}\right)-{\widehat{i}}_{out}\right)+{\widehat{v}}_{out}$$

(90)

Simplifying (90) would result in (91):

$$Z_{out}=\frac{{\widehat{v}}_{out}}{{\widehat{i}}_{out}}=\frac{3\left(R_d+sL\right)}{s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+3\frac{R_d}{R}+1}$$

(91)

5.2.5. Converter Gain

The output voltage and the input voltage relationship is found by assuming ${\widehat{d}}_j=0,j=1,2,\mathrm{and}3$, summing Equations in (71) and substituting (67), (69), and (74) in the added equation.

$$\frac{3D_{eff}}{K}\left(1+\frac{3R_d}{R}\right){\widehat{v}}_{in}=\left(\frac{\left(sL+R_d\right)\left(sRC+3\right)}{R}+1\right){\widehat{v}}_{out}$$

(92)

Simplifying (92) would result in (93):

$$G_{vg}=\frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}=\frac{\frac{3D_{eff}}{K}\left(1+\frac{3R_d}{R}\right)}{s^{2}LC+s\left(\frac{3L}{R}+R_{d}C\right)+\frac{3R_d}{R}+1}$$

(93)

6. Generalized Small-Signal Analysis for Dual Series/Parallel Input-Output (ISIP-OSOP) DC-DC Converter

In this section, the SSM for the four architectures is expanded to include a generalized SSM applicable for ISIP-OSOP configuration. In addition, after generalizing the model, the equations derived in this section are validated with the IPOS, ISOP, and ISIPOS presented in [38,39,40,41,42], respectively.

6.1. ISIP-OSOP Generic DC-DC Converter Circuit Diagram

The ISIP-OSOP generic DC-DC converter configuration shown in Figure 7 consists of $n$ modules that are connected in series and/or parallel at the input side, and in series and/or parallel at the output side, as shown in Figure 7.

By ensuring ICS and IVS, the input current per module is $\frac{I_{in}}{\mathit{\alpha }}$, and the input voltage per module is $\frac{V_{in}}{\mathit{\beta }}$. In which, $I_{in}$ is the input current and $V_{in}$ is the input voltage of the ISIP-OSOP DC-DC converter, and $\mathit{\alpha }$ is the number of modules connected in parallel, and $\mathit{\beta }$ is the number of modules connected in series at the input side. Similarly, by ensuring OCS and OVS, the output current per module is $\frac{I_o}{\mathit{a}}$, and the output voltage per module is $\frac{V_o}{\mathit{b}}$. In which $I_o$ is the output current and $V_o$ is the output voltage of the ISIP-OSOP DC-DC converter, and $\mathit{a}$ is the number of modules connected in parallel, and $\mathit{b}$ is the number of modules connected in series at the output side.

6.2. ISIP-OSOP Generic DC-DC Converter Small-Signal Analysis

The SSM for the ISIP-OSOP converter shown in Figure 8 is derived using the SSM presented in [37], and expanding the study of the presented multimodule DC-DC converters presented in [38,39,40,41,42].

Since the input current and voltage per module are $\frac{I_{in}}{\alpha }$ and $\frac{V_{in}}{\beta }$, respectively, and the output current and voltage per module is $\frac{I_o}{\mathit{a}}$ and $\frac{V_o}{\mathit{b}}$, respectively. Therefore, the load resistance per module is $\frac{\mathit{a}}{\mathit{b}}R$. Accordingly, ${\widehat{d}}_{ij}$ and ${\widehat{d}}_{v\mathrm{j}}$, which are the effect of changing the filter inductor current and the effect of changing the input voltage on the duty cycle modulation, as well as $I_{eq}$ presented in Figure 8 can be expressed as [39,42]:

$$\mathrm{S}{\widehat{d}}_{ij}=-\frac{4\mathit{\beta }{L}_{lk}{f}_s}{K{V}_{in}}{\widehat{i}}_{Lj}, j=1,2,\dots ,n$$

(94)

Equation (94) can be re-written as:

$${\widehat{d}}_{ij}=-\frac{\mathit{\beta }K{R}_d}{V_{in}}{\widehat{i}}_{Lj}, j=1,2,\dots ,n$$

(95)

where $R_d=\frac{4L_{lk}{f}_s}{k^2}$.

$${\widehat{d}}_{vj}=\frac{4\mathit{\beta }\mathit{b}{L}_{lk}{f}_s{D}_{eff}}{\mathit{a}{k}^{2}R{V}_{in}}{\widehat{v}}_{cdj}, j=1,2,\dots ,n$$

(96)

Equation (96) can be re-written as:

$${\widehat{d}}_{vj}=\frac{\mathit{\beta }\mathit{b}{R}_d{D}_{eff}}{\mathit{a}R{V}_{in}}{\widehat{v}}_{cdj}, j=1,2,\dots ,n$$

(97)

$$\mathrm{S}{I}_{eq}=\frac{\mathit{b}{V}_{in}}{\mathit{\beta }\mathit{a}KR}$$

(98)

The following equations are obtained from Figure 8:

$$\{\begin{array}{c}\begin{array}{c}\frac{D_{eff}}{K}{\widehat{v}}_{cd1}+\frac{V_{in}}{\mathit{\beta }K}\left({\widehat{d}}_{i1}+{\widehat{d}}_{v1}+{\widehat{d}}_1\right)=sL{\widehat{i}}_{L1}+{\widehat{v}}_{out1}\\ \frac{D_{eff}}{K}{\widehat{v}}_{cd2}+\frac{V_{in}}{\mathit{\beta }K}\left({\widehat{d}}_{i2}+{\widehat{d}}_{v2}+{\widehat{d}}_2\right)=sL{\widehat{i}}_{L2}+{\widehat{v}}_{out2}\\ ⋮\end{array}\\ \frac{D_{eff}}{K}{\widehat{v}}_{cdn}+\frac{V_{in}}{\mathit{\beta }K}\left({\widehat{d}}_{in}+{\widehat{d}}_{vn}+{\widehat{d}}_n\right)=sL{\widehat{i}}_{Ln}+{\widehat{v}}_{outn}\end{array}$$

(99)

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L11}+{\widehat{i}}_{L21}+\cdots +{\widehat{i}}_{L\mathit{a}1}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out1} +\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L12}+{\widehat{i}}_{L22}+\cdots +{\widehat{i}}_{L\mathit{a}2}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out2} +\frac{{\widehat{v}}_{out}}{R}\\ ⋮\end{array}\\ {\widehat{i}}_{L1\mathit{b}}+{\widehat{i}}_{L2\mathit{b}}+\cdots +{\widehat{i}}_{L\mathit{a}\mathit{b}}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{outn} +\frac{{\widehat{v}}_{out}}{R}\end{array}$$

(100)

Based on the feature of modularity, it is assumed that all the employed modules are ideal. Moreover, the Equivalent Series Resistance (ESR) of the output capacitance is considered in this model.

Summing Equations in (100):

$${\displaystyle \sum }_{i=1}^{\mathit{a}}{\displaystyle \sum }_{j=1}^{\mathit{b}}{\widehat{i}}_{Lij}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out}+\frac{\mathit{b}{\widehat{v}}_{out}}{R}$$

(101)

Equation (101) can be written as:

$${\displaystyle \sum }_{i=1}^{\mathit{a}}{\displaystyle \sum }_{j=1}^{\mathit{b}}{\widehat{i}}_{Lij}={\widehat{v}}_{out}\left(\frac{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{R\left(1+s{R}_{c}C\right)}\right)$$

(102)

Defining the summation terms of the module’s input and output voltage appearing after summing up Equations in (99):

$${\displaystyle \sum }_{j=1}^n{\widehat{v}}_{cdj}=\gamma {\widehat{v}}_{in}$$

(103)

where:

• $\gamma =1$, if all the modules at the input side are connected in series.
• $\gamma =\mathit{\alpha }$, if all the modules at the input side are connected in parallel.
• $\gamma =\left(1+\frac{\mathit{\alpha }}{\mathit{\beta }}\right)$, if the modules at the input side are connected in series and parallel.

$${\displaystyle \sum }_{j=1}^n{\widehat{v}}_{outj}=\mathit{c}{\widehat{v}}_{out}$$

(104)

where:

• $\mathit{c}=1$, if all the modules at the output side are connected in series.
• $\mathit{c}=\mathit{a}$, if all the modules at the output side are connected in parallel.
• $\mathit{c}=\left(1+\frac{\mathit{a}}{\mathit{b}}\right)$, if the modules at the output side are connected in series and parallel.

6.2.1. Control-To-Output Voltage Transfer Function

The output voltage and the duty cycle relationship is found by summing up Equations in (99), assuming ${\widehat{v}}_{in}=0$, and ${\widehat{d}}_k=0$, where $k=1,2,\dots ,n$ and $k\ne j$, and substituting (95), (97), (102), (103), and (104).

Summing Equations in (99):

$$\frac{D_{eff}}{K}{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{cdj}+\frac{V_{in}}{\mathit{\beta }K}\left({\displaystyle \sum }_{j=1}^n{\widehat{d}}_{ij}+{\displaystyle \sum }_{j=1}^n{\widehat{d}}_{vj}+{\displaystyle \sum }_{j=1}^n{\widehat{d}}_j\right)=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{outj}$$

(105)

$$\frac{D_{eff}}{K}{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{cdj}+\frac{V_{in}}{\mathit{\beta }K}\left({\displaystyle \sum }_{j=1}^n-\frac{\mathit{\beta }K{R}_d}{V_{in}}{\widehat{i}}_{Lj}+{\displaystyle \sum }_{j=1}^n\frac{\mathit{\beta }\mathit{b}{R}_d{D}_{eff}}{\mathit{a}R{V}_{in}}{\widehat{v}}_{cdj}+{\widehat{d}}_1\right)=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{outj}$$

(106)

$$\frac{D_{eff}}{K}\gamma {\widehat{v}}_{in}+\frac{V_{in}}{\mathit{\beta }K}\left({\displaystyle \sum }_{j=1}^n-\frac{\mathit{\beta }K{R}_d}{V_{in}}{\widehat{i}}_{Lj}+\frac{\mathit{\beta }\mathit{b}{R}_d{D}_{eff}}{\mathit{a}R{V}_{in}}\gamma {\widehat{v}}_{in}+{\widehat{d}}_1\right)=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+\mathit{c}{\widehat{v}}_{out}$$

(107)

Simplifying (107) would result in (108).

$$G_{vd}=\frac{{\widehat{v}}_{out}}{{\widehat{d}}_j}=\frac{\frac{V_{in}}{\mathit{\beta }K}\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{\mathit{b}{R}_c}{R}\right)+s\left(\frac{\mathit{b}L}{R}+R_{d}C\left(1+\frac{\mathit{b}{R}_c}{R}\right)+\mathit{c}{R}_{c}C\right)+\frac{\mathit{b}{R}_d}{R}+\mathit{c}}$$

(108)

6.2.2. Control-To-Filter Inductor Current Transfer Function

The filter inductor current and the duty cycle relationship is found by using (102) to find the following equation:

$${\widehat{v}}_{out}=\frac{R\left(1+s{R}_{c}C\right)}{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{\displaystyle \sum }_{i=1}^{\mathit{a}}{\displaystyle \sum }_{j=1}^{\mathit{b}}{\widehat{i}}_{Lij}$$

(109)

Substituting (109) in (107) and considering the same assumptions as in Section 7.2.

$$\frac{V_{in}}{\mathit{\beta }K}{\widehat{d}}_1-R_d{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+\frac{\mathit{c}R\left(1+s{R}_{c}C\right)}{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}$$

(110)

Simplifying (110) would result in (111).

$$G_{id}=\frac{{\widehat{i}}_L}{\widehat{d}}=\frac{\frac{V_{in}}{\mathit{\beta }K}\left(\mathit{b}+sRC+s\mathit{b}{R}_{c}C\right)}{R\left(s^{2}LC\left(1+\frac{\mathit{b}{R}_c}{R}\right)+s\left(\frac{\mathit{b}L}{R}+R_{d}C\left(1+\frac{\mathit{b}{R}_c}{R}\right)+\mathit{c}{R}_{c}C\right)+\frac{\mathit{b}{R}_d}{R}+\mathit{c}\right)}$$

(111)

6.2.3. Output Impedance

Similarly, as studied in the SSM presented in [39,40], the ISIP-OSOP converter output impedance can be found by modifying (100), such that:

$$\{\begin{array}{c}\begin{array}{c}{\widehat{i}}_{L11}+{\widehat{i}}_{L21}+\cdots +{\widehat{i}}_{L\mathit{a}1}+{\widehat{i}}_{out}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out1} +\frac{{\widehat{v}}_{out}}{R}\\ {\widehat{i}}_{L12}+{\widehat{i}}_{L22}+\cdots +{\widehat{i}}_{L\mathit{a}2}+{\widehat{i}}_{out}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out2} +\frac{{\widehat{v}}_{out}}{R}\\ ⋮\end{array}\\ {\widehat{i}}_{L1\mathit{b}}+{\widehat{i}}_{L2\mathit{b}}+\cdots +{\widehat{i}}_{L\mathit{a}\mathit{b}}+{\widehat{i}}_{out}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{outn} +\frac{{\widehat{v}}_{out}}{R}\end{array}$$

(112)

Summing Equations in (112):

$${\displaystyle \sum }_{i=1}^{\mathit{a}}{\displaystyle \sum }_{j=1}^{\mathit{b}}{\widehat{i}}_{Lij}=\frac{sC}{s{R}_{c}C+1}{\widehat{v}}_{out}+\frac{\mathit{b}{\widehat{v}}_{out}}{R}-\mathit{b}{\widehat{i}}_{out}$$

(113)

Accordingly, (100) is modified as follows:

$${\displaystyle \sum }_{i=1}^{\mathit{a}}{\displaystyle \sum }_{j=1}^{\mathit{b}}{\widehat{i}}_{Lij}={\widehat{v}}_{out}\left(\frac{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{R\left(1+s{R}_{c}C\right)}\right)-\mathit{b}{\widehat{i}}_{out}$$

(114)

The output voltage and the output current relationship is found by considering the same assumptions as in Section 7.2, summing Equations in (99), and substituting (95), (97), (103), (104), and (114).

$$\frac{V_{in}}{\mathit{\beta }K}\left(-\frac{\mathit{\beta }K{R}_d}{V_{in}}\right){\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+\mathit{c}{\widehat{v}}_{out}$$

(115)

$$-R_d\left({\widehat{v}}_{out}\left(\frac{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{R\left(1+s{R}_{c}C\right)}\right)-\mathit{b}{\widehat{i}}_{out}\right)=sL\left({\widehat{v}}_{out}\left(\frac{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{R\left(1+s{R}_{c}C\right)}\right)-\mathit{b}{\widehat{i}}_{out}\right)+\mathit{c}{\widehat{v}}_{out}$$

(116)

Rearranging (116) would result in (117).

$$Z_{out}=\frac{{\widehat{v}}_{out}}{{\widehat{i}}_{out}}=\frac{\mathit{b}\left(R_d+sL\right)\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{\mathit{b}{R}_c}{R}\right)+s\left(\frac{\mathit{b}L}{R}+R_{d}C\left(1+\frac{\mathit{b}{R}_c}{R}\right)+\mathit{c}{R}_{c}C\right)+\frac{\mathit{b}{R}_d}{R}+\mathit{c}}$$

(117)

6.2.4. Converter Gain

The output voltage and the input voltage relationship is found by assuming ${\widehat{d}}_j=0,j=1,2,\dots ,n$, summing Equations in (99), and substituting (95), (97), (102)–(104) in the added equation.

$$\frac{D_{eff}}{K}{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{cdj}+\frac{V_{in}}{\mathit{\beta }K}\left({\displaystyle \sum }_{j=1}^n-\frac{\mathit{\beta }K{R}_d}{V_{in}}{\widehat{i}}_{Lj}+{\displaystyle \sum }_{j=1}^n\frac{\mathit{\beta }\mathit{b}{R}_d{D}_{eff}}{\mathit{a}R{V}_{in}}{\widehat{v}}_{cdj}\right)=sL{\displaystyle \sum }_{j=1}^n{\widehat{i}}_{Lj}+{\displaystyle \sum }_{j=1}^n{\widehat{v}}_{outj}$$

(118)

$$\frac{D_{eff}}{K}\gamma \left(1+\frac{\mathit{b}{R}_d}{\mathit{a}R}\right){\widehat{v}}_{in}=\left(sL+R_d\right)\left({\widehat{v}}_{out}\left(\frac{sRC+s\mathit{b}{R}_{c}C+\mathit{b}}{R\left(1+s{R}_{c}C\right)}\right)\right)+\mathit{c}{\widehat{v}}_{out}$$

(119)

Rearranging (119) would result in (120).

$$G_{vg}=\frac{{\widehat{v}}_{out}}{{\widehat{v}}_{in}}=\frac{\frac{D_{eff}}{K}\gamma \left(1+\frac{\mathit{b}{R}_d}{\mathit{a}R}\right)\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{\mathit{b}{R}_c}{R}\right)+s\left(\frac{\mathit{b}L}{R}+R_{d}C\left(1+\frac{\mathit{b}{R}_c}{R}\right)+\mathit{c}{R}_{c}C\right)+\frac{\mathit{b}{R}_d}{R}+\mathit{c}}$$

(120)

6.3. ISIP-OSOP DC-DC Converter SSM Verification

In this section, the generalized multimodule DC-DC converter SSM is verified using three different models presented in [38,39,40,41,42].

6.3.1. Generalized Model Verification with a Two-Module IPOS DC-DC Converter

The proposed configuration in [38] consists of two modules that are connected in parallel at the input side, and series, at the output side, where the modules are FB-PS-based DC-DC converters. In this model, the effect of the ESR $R_c$ is ignored, accordingly, when verifying the model presented in [34] with the generalized model, $R_c$ should be equated to zero.

By ensuring ICS and OVS, the input current per module is $\frac{I_{in}}{2}$. However, the input voltage per module is $V_{in}$. Regarding the output side, the output voltage per module is $\frac{V_o}{2}$. However, the output current per module is $I_o$. In which, $V_{in}$ is the IPOS input voltage, $I_{in}$ is the IPOS input current, $V_o$ is the IPOS output voltage, and $I_o$ is the IPOS output current. Accordingly, the values for the six parameters that are previously defined are known and shown in

Table 2. Values for the six parameters for a two-module Input-Parallel Output-Series (IPOS) power converter.

Defined Variables
Input Side	$\mathit{\alpha }$	2
	$\mathit{\beta }$	1
	$\gamma$	2 (same as $\mathit{\alpha }$)
Output Side	$\mathit{a}$	1
	$\mathit{b}$	2
	$\mathit{c}$	1

.

Substituting the six parameters with their values in Equations (109), (112), (117), and (120) and substituting the ESR $R_c$ with zero in the generalized transfer functions would result in the transfer functions presented in

Table 3. Generalized model verification with the two-module IPOS power converter.

Transfer Functions for Two-Module IPOS DC-DC Converter
${\mathit{G}}_{\mathit{v}\mathit{d}}$	$\frac{\frac{V_{in}}{K}}{s^{2}LC+s\left(\frac{\mathbf{2}L}{R}+R_{d}C\right)+\frac{\mathbf{2}{R}_d}{R}+1}$
${\mathit{G}}_{\mathit{i}\mathit{d}}$	$\frac{\frac{V_{in}}{K}\left(\mathbf{2}+sRC\right)}{R\left(s^{2}LC+s\left(\frac{\mathbf{2}L}{R}+R_{d}C\right)+\frac{\mathbf{2}{R}_d}{R}+1\right)}$
${\mathit{Z}}_{\mathit{o}\mathit{u}\mathit{t}}$	$\frac{\mathbf{2}\left(R_d+sL\right)}{s^{2}LC+s\left(\frac{\mathbf{2}L}{R}+R_{d}C\right)+\frac{\mathbf{2}{R}_d}{R}+1}$
${\mathit{G}}_{\mathit{v}\mathit{g}}$	$\frac{\frac{\mathbf{2}{D}_{eff}}{K}\left(1+\frac{\mathbf{2}{R}_d}{R}\right)}{s^{2}LC+s\left(\frac{\mathbf{2}L}{R}+R_{d}C\right)+\frac{\mathbf{2}{R}_d}{R}+1}$

.

As can be seen from Table 3, the derived generalized model matches the model presented in [38], where the $R_d$ term in the above transfer functions is substituted with its equivalence $\frac{4L_{lk}{f}_s}{K^2}$.

6.3.2. Generalized Model Verification with a Three-Module ISOP DC-DC Converter

In this Section, the generalized model is validated with the three-module ISOP power converter model-derived and presented in [39,40]. The three-module ISOP configuration consists of three modules that are connected in series at the input side, and parallel at the output side. In this model, the effect of the ESR $R_c$ is considered, accordingly, when verifying the model presented [39] with the generalized model, $R_c$ should not be ignored.

By ensuring IVS and OCS, the input voltage per module is $\frac{V_{in}}{3}$. However, the input current per module is $I_{in}$. Regarding the output side, the output current per module is $\frac{I_o}{3}$. However, the output voltage per module is $V_o$. Accordingly, the values for the six parameters that are previously defined are known and shown

Table 4. Values for the six parameters for a three-module Input-Series Output-Parallel (ISOP) power converter.

Defined Variables
Input Side	$\mathit{\alpha }$	1
	$\mathit{\beta }$	3
	$\gamma$	1
Output Side	$\mathit{a}$	3
	$\mathit{b}$	1
	$\mathit{c}$	3

.

Substituting the six parameters with their values in Equations (109), (112), (117), and (120) would result in the transfer functions presented in

Table 5. Generalized model verification with the three-module ISOP power converter.

Transfer Functions for Three-Module ISOP DC-DC Converter
${\mathit{G}}_{\mathit{v}\mathit{d}}$	$\frac{\frac{V_{in}}{\mathbf{3}K}\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{R_c}{R}\right)+s\left(\frac{L}{R}+R_{d}C\left(1+\frac{R_c}{R}\right)+\mathbf{3}{R}_{c}C\right)+\frac{R_d}{R}+\mathbf{3}}$
${\mathit{G}}_{\mathit{i}\mathit{d}}$	$\frac{\frac{V_{in}}{\mathbf{3}K}\left(1+sRC+s{R}_{c}C\right)}{R\left(s^{2}LC\left(1+\frac{R_c}{R}\right)+s\left(\frac{L}{R}+R_{d}C\left(1+\frac{R_c}{R}\right)+\mathbf{3}{R}_{c}C\right)+\frac{R_d}{R}+\mathbf{3}\right)}$
${\mathit{Z}}_{\mathit{o}\mathit{u}\mathit{t}}$	$\frac{\left(R_d+sL\right)\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{R_c}{R}\right)+s\left(\frac{L}{R}+R_{d}C\left(1+\frac{R_c}{R}\right)+\mathbf{3}{R}_{c}C\right)+\frac{R_d}{R}+\mathbf{3}}$
${\mathit{G}}_{\mathit{v}\mathit{g}}$	$\frac{\frac{D_{eff}}{K}\left(1+\frac{R_d}{\mathbf{3}R}\right)\left(1+s{R}_{c}C\right)}{s^{2}LC\left(1+\frac{R_c}{R}\right)+s\left(\frac{L}{R}+R_{d}C\left(1+\frac{R_c}{R}\right)+\mathbf{3}{R}_{c}C\right)+\frac{R_d}{R}+\mathbf{3}}$

.

As can be seen from Table 5, the derived generalized model matches the model presented in [39,40].

6.3.3. Generalized Model Verification with a Four-Module ISIPOS DC-DC Converter

In this section, the generalized model is validated with the four-module ISIPOS power converter model presented in [41,42].

The four-module ISIPOS configuration consists of four modules that are connected in series and parallel at the input side, and series at the output side. In this model, the effect of the ESR $R_c$ is ignored, accordingly, when verifying the model presented in [41] with the generalized model, $R_c$ should be equated to zero.

By ensuring IVS, ICS, and OVS, the input voltage per module is $\frac{V_{in}}{2}$ and the input current per module is $\frac{I_{in}}{2}$. Regarding the output side, the output voltage per module is $\frac{V_o}{4}$. However, the output current per module is $I_o$. Accordingly, the values for the six parameters that are previously defined are known and shown in

Table 6. Values for the six parameters for a four-module Input-Series Input-Parallel Output-Series (ISIPOS) power converter.

Defined Variables
Input Side	$\mathit{\alpha }$	2
	$\mathit{\beta }$	2
	$\gamma$	2 $=\left(1+\frac{\mathit{\alpha }}{\mathit{\beta }}\right)$
Output Side	$\mathit{a}$	1
	$\mathit{b}$	4
	$\mathit{c}$	1

.

Substituting the six parameters with their values in Equations (109), (112), (117), and (120) would result in the transfer functions presented in

Table 7. Generalized model verification with the four-module ISIPOS power converter.

Transfer Functions for Four-Module ISIPOS DC-DC Converter
${\mathit{G}}_{\mathit{v}\mathit{d}}$	$\frac{\frac{V_{in}}{\mathbf{2}K}}{s^{2}LC+s\left(\frac{\mathbf{4}L}{R}+R_{d}C\right)+\frac{\mathbf{4}{R}_d}{R}+1}$
${\mathit{G}}_{\mathit{i}\mathit{d}}$	$\frac{\frac{V_{in}}{\mathbf{2}K}\left(\mathbf{4}+sRC\right)}{R\left(s^{2}LC+s\left(\frac{\mathbf{4}L}{R}+R_{d}C\right)+\frac{\mathbf{4}{R}_d}{R}+1\right)}$
${\mathit{Z}}_{\mathit{o}\mathit{u}\mathit{t}}$	$\frac{\mathbf{4}\left(R_d+sL\right)}{s^{2}LC+s\left(\frac{\mathbf{4}L}{R}+R_{d}C\right)+\frac{\mathbf{4}{R}_d}{R}+1}$
${\mathit{G}}_{\mathit{v}\mathit{g}}$	$\frac{\frac{\mathbf{2}{D}_{eff}}{K}\left(1+\frac{\mathbf{4}{R}_d}{R}\right)}{s^{2}LC+s\left(\frac{\mathbf{4}L}{R}+R_{d}C\right)+\frac{\mathbf{4}{R}_d}{R}+1}$

.

As can be seen from Table 7, the derived generalized model matches the model presented in [41,42].

7. Power Balancing in ISIP-OSOP DC-DC Converters

To guarantee stable operation in the presence of parameter variations, a control strategy that ensures power balancing is essential to provide equal power distribution among the modules. In this section, the control strategy for each multimodule configuration is studied to ensure IVS, ICS, OVS, and OCS if needed.

The possible control strategies for the four configurations have been discussed in [45]. According to the study presented in [45], for input parallel-connected systems, OCS and OVS controllers are required for IPOP and IPOS DC-DC converters, respectively. However, for input series-connected systems, IVS and OVS are required for ISOS DC-DC converters, and IVS and OCS are required for ISOP DC-DC converters. To further illustrate, active power sharing control for input parallel-connected systems is achieved by designing ICS controllers that achieve OCS and OVS for IPOP and IPOS systems or by designing OCS controllers for IPOP systems and designing OVS controllers for IPOS systems that also achieves ICS between the employed modules. However, for input-series connected systems, IVS controllers are necessary to achieve OVS and OCS for ISOS and ISOP DC-DC converters. However, in [46], Cross Feedback OCS (CFOCS) has been proposed for ISOP systems to achieve OCS without the need for IVS controllers, hence simplifying the overall control design. This control strategy has been tested for a three-module ISOP DC-DC converter considering RC in [40] to achieve IVS and OCS.

Since this paper mainly focuses on multimodule DC-DC converters designed for EV fast chargers, the control scheme designed for the four DC-DC converters is current-controlled considering an RC technique that is termed as burp charging or negative pulse charging. This charging technique is based on applying a short negative pulse or a short discharge pulse during the charging cycle. Such an algorithm offers significant advantages that can be highlighted in shortening the charging time and lowering the rise in temperature. Generally, the RC technique consists of three charging sequences, which are: a positive charging pulse, a rest period where no charging occurs, and a negative charging pulse or a discharge pulse [47]. Accordingly, the designed control schemes are based on controlling the filter inductor current of the DC-DC converters such that the output current profile is based on RC. Consequently, for IPOP and IPOS DC-DC converters, active power sharing is achieved through controlling the filter inductor currents, as shown in Figure 9a, that accordingly achieves equal output current distribution for IPOP systems and equal voltage distribution for IPOS systems. However, active power sharing in the ISOP DC-DC converter is achieved through the CFOCS presented in [40,46] and shown in Figure 9b, which eliminates the need for IVS controllers and control the output currents of the converters. The difference between Figure 9a and b is that, in Figure 9b, the current feedback for the individual module is the summation of the other two output currents and not its output current. Unlike the three systems ISOP, IPOP, and IPOS, active power sharing in the ISOS system is achieved through the use of both IVS and OVS controllers. In other words, the control scheme for the ISOS DC-DC converter combines the control scheme presented in Figure 9a with an IVS control, resulting in Figure 9c. To clarify, three IVS controllers are designed for each module to achieve equal input voltage distribution between the employed modules. In addition, the filter inductor currents are controlled using a reference current with an RC profile to achieve equal OVS between the modules of the ISOS converter. Therefore, it can be said that the control scheme presented in Figure 9a is applicable for the four architectures with slight differences presented in Figure 9b,c.

7.1. ISOS Control Strategy

In this Section, the ISOS DC-DC converter overall control scheme is examined with the system parameters presented in

Table 8. Input-Series Output-Series (ISOS) converter parameters.

Parameters	First Module	Second Module	Third Module 3
Overall converter rated power	$350 \mathrm{kW}$
Rated power per module	$117 \mathrm{kW}$
Overall input voltage	$10 \mathrm{kV}$
Input voltage per module	$3.3 \mathrm{kV}$
Overall output voltage	$920 \mathrm{V}$
Output voltage per module	$307 \mathrm{V}$
Modules Number	$3$
Turns ratio	$8.696:1$	$8.152:1$	$7.609:1$
Leakage inductance	$1142.72 \mathsf{\mu }\mathrm{H}$	$1004.35 \mathsf{\mu }\mathrm{H}$	$874.89 \mathsf{\mu }\mathrm{H}$
Effective duty cycle	$0.8$	$0.75$	$0.7$
Input Capacitance	$50 \mathsf{\mu }\mathrm{F}$	$80 \mathsf{\mu }\mathrm{F}$	$60 \mathsf{\mu }\mathrm{F}$
Output filter inductor	$50 \mathrm{mH}$	$60 \mathrm{mH}$	$60 \mathrm{mH}$
Output capacitance	$300 \mathsf{\mu }\mathrm{F}$	$350 \mathsf{\mu }\mathrm{F}$	$300 \mathsf{\mu }\mathrm{F}$
Load resistance	$2.418\mathsf{\Omega }$
Switching frequency	$10 \mathrm{kHz}$

. To test the controller’s power balancing capability when handling uncertainties, the component parameters for each module are purposely assumed to be different, as presented in Table 8.

Talking about the simulation results, the control scheme presented in Figure 9c for the ISOS DC-DC converter is examined considering a reference current with a reflex-current profile to the total current flowing in the filter inductance. The charging pulse is applied, where the charging cycle begins at 0.2 s and ends at 0.6 s. After that, a rest period for 0.1 s is applied to the total filter inductor current reference signal. The results shown in Figure 10 demonstrate that the power-sharing controller presented in Figure 9c compensates for the negative influences resulting from the systems’ parameters mismatch. In which, the individual filter inductor currents are equally shared between the three modules. Moreover, the total filter inductor current of the ISOS system follows the reference signal applied based on RC. It is worth mentioning that the results in this section, as well as the following sections, involve the number of signals presented in the legend. However, the signals are coincident, meaning that power balance control is achieved. Consequently, it can be concluded that the control scheme is reliable and achieves equal power distribution between the modules.

7.2. ISOP Control Strategy

The overall control strategy for the ISOP system is examined and presented in [40] considering parameter mismatch for the three modules and a reference output current profile based on RC.

7.3. IPOP Control Strategy

In this Section, the IPOP DC-DC converter overall control scheme is examined with the system parameters presented in

Table 9. Input-Parallel Output-Parallel (IPOP) converter parameters.

Parameters	First Module	Second Module	Third Module 3
Overall converter rated power	$350 \mathrm{kW}$
Rated power per module	$117 \mathrm{kW}$
Overall input voltage	$570 \mathrm{V}$
Input voltage per module	$570 \mathrm{V}$
Overall output voltage	$400 \mathrm{V}$
Output voltage per module	$400 \mathrm{V}$
Modules Number	$3$
Turns ratio	$1.14:1$	$1.069:1$	$1.003:1$
Leakage inductance	$3.712 \mathsf{\mu }\mathrm{H}$	$3.262\mathsf{\mu }\mathrm{H}$	$2.871 \mathsf{\mu }\mathrm{H}$
Effective duty cycle	$0.8$	$0.75$	$0.7$
Input Capacitance	$50 \mathsf{\mu }\mathrm{F}$	$80 \mathsf{\mu }\mathrm{F}$	$60 \mathsf{\mu }\mathrm{F}$
Output filter inductor	$50\mathrm{mH}$	$60 \mathrm{mH}$	$60 \mathrm{mH}$
Output capacitance	$300 \mathsf{\mu }\mathrm{F}$	$350 \mathsf{\mu }\mathrm{F}$	$300 \mathsf{\mu }\mathrm{F}$
Load resistance	$0.457 \mathsf{\Omega }$
Switching frequency	$10\mathrm{kHz}$

. To test the controller’s power balancing capability when handling uncertainties, the component parameters for each module are purposely assumed to be different, as presented in Table 9.

For parallel connected systems, active power-sharing control is achieved through directing the control efforts toward the output filter inductor currents without the need for any additional controllers. After designing the control scheme for the output filter inductor currents, the input currents are monitored to ensure that ICS is achieved through OCS. The same reference signal based on RC is applied to assess the controller scheme shown in Figure 9a. It can be observed from Figure 11 that the control scheme for the three-module IPOP system can achieve equal power distribution among the modules under parameter mismatch. In which, the modular input currents, as well as the modular output currents, are equally shared between the three modules. In addition, the overall filter inductor current of the IPOP power converter follows the reference signal applied based on RC.

7.4. IPOS Control Strategy

In this Section, the IPOS DC-DC converter overall control scheme is examined with the system parameters presented in

Table 10. IPOS converter parameters.

Parameters	First Module	Second Module	Third Module 3
Overall converter rated power	$350 \mathrm{kW}$
Rated power per module	$117 \mathrm{kW}$
Overall input voltage	$570 \mathrm{V}$
Input voltage per module	$570 \mathrm{V}$
Overall output voltage	$920 \mathrm{V}$
Output voltage per module	$307 \mathrm{V}$
Modules Number	$3$
Turns ratio	$1.485:1$	$1.393:1$	$1.299:1$
Leakage inductance	$33.383 \mathsf{\mu }\mathrm{H}$	$29.341 \mathsf{\mu }\mathrm{H}$	$25.559 \mathsf{\mu }\mathrm{H}$
Effective duty cycle	$0.8$	$0.75$	$0.7$
Input Capacitance	$50 \mathsf{\mu }\mathrm{F}$	$80 \mathsf{\mu }\mathrm{F}$	$60 \mathsf{\mu }\mathrm{F}$
Output filter inductor	$50 \mathrm{mH}$	$60 \mathrm{mH}$	$60 \mathrm{mH}$
Output capacitance	$300 \mathsf{\mu }\mathrm{F}$	$350 \mathsf{\mu }\mathrm{F}$	$300 \mathsf{\mu }\mathrm{F}$
Load resistance	$2.421 \mathsf{\Omega }$
Switching frequency	$10 \mathrm{kHz}$

. To test the controller’s power balancing capability when handling uncertainties, the component parameters for each module are purposely assumed to be different, as presented in Table 10.

In IPOS, OVS is achieved through controlling the filter inductor currents of each module. This accordingly achieves ICS between the three modules. The reference signal for the overall filter inductor current is also based on RC. It can be observed from Figure 12 that the control scheme for the three-module IPOS DC-DC converter presented in Figure 9a can achieve equal ICS and equal OVS among the employed IPOS modules. In which, the modular input currents, as well as the modular output voltages, are equally shared between the three modules. In addition, the overall filter inductor current follows the same current profile of the reference signal.

8. Conclusions

In recent years, EVs have gained attention because of their significant role in reducing CO₂ emissions, minimizing noise pollution, avoiding the high price of fuel, and providing consumers with more efficient and environmentally friendly EVs. To allow for broader adoption of such EVs, diminishing the charging process would significantly increase the EV’s efficiency as well as their utilization. Towards this direction, advanced power electronics technologies are emerging significantly to achieve high efficiency as well as ensuring extended battery lifetime. Among these power electronics conversion systems, the DC-DC conversion stage plays a vital role in charging the EV’s battery. Consequently, this paper aims to present the four basic architectures for the modular DAB DC-DC converter with their SSM and control strategy to guarantee uniform power sharing among the modules. In addition, the main contribution of this paper can be summarized in providing generalized SSM for any multimodule connection, including ISIP-OSOP configurations to support in the design of the DC-DC stage control. In other words, the dynamic behavior of such multimodule converters is studied using the SSM to develop a generalized dual series/parallel input-output dual active bridge SSM applicable for EVs. The provided model is verified with three different models presented in the literature, which are: two-module IPOS converter, three-module ISOP converter, and four-module ISIPOS converter. Moreover, to assess the effectiveness of the control schemes, simulation results are presented where parameter mismatch is introduced between the modules to ensure power balancing in the overall converter system.