Design and Testing of a Low Voltage Solid-State Circuit Breaker for a DC Distribution System

Abstract

In this study, a low voltage solid-state circuit breaker (SSCB) was implemented for a DC distribution system using commercially available components. The design process of the high-side static switch was enabled through a voltage bias. Detailed functional testing of the current sensor, high-side switch, thermal ratings, analog to digital conversion (ADC) techniques, and response times of the SSCB was evaluated. The designed SSCB was capable of low-end lighting protection applications and tested at 50 V. A 15 A continuous current rating was obtained, and the minimum response time of the SSCB was nearly 290 times faster than that of conventional AC protection methods. The SSCB was implemented to fill the gap where traditional AC protection schemes have failed. DC distribution systems are capable of extreme faults that can destroy sensitive power electronic equipment. However, continued research and development of the SSCB is helping to revolutionize the power industry and change the current power distribution methods to better utilize clean renewable energy systems.

1. Introduction

Clean renewable energies have laid a platform for practical DC distribution systems in applications such as commercial buildings, data centers, microgrids, and shipboard power systems [1,2,3,4,5]. Solid-state circuit breakers (SSCBs) have been deemed the most ideal form of protection in developing DC systems due to inadequacies in standard AC protection methods. AC breakers work in connection with the zero crossing of the alternating voltage and current to mechanically extinguish a fault through arcing. Arcing in DC systems is indefinitely sustained unless larger airgaps are used for the same AC rating. Attempts have been made to reduce an AC breaker’s voltage and current ratings by as much as half for use in DC systems, but their overall effectiveness remains scrutinized due to the speed at which they operate [6,7,8,9,10]. DC microgrids rely on power electronic converters to operate and are often unable to sustain prolonged faults, making it necessary to reduce instantaneous trip ratings. The fastest SSCBs have reported clearing times of just a few microseconds, where the mechanical AC breaker operates in tens of milliseconds. The comparison of an SSCB and thermomagnetic circuit breaker can be found in Figure 1 [11].

Several methods of SSCB design have been researched using different types of semiconductor devices for various applications. Silicon insolated-gate bipolar transistor (IGBT) devices are the most commonly reported [12,13,14]. More expensive wide-bandgap semiconductors with higher voltage ratings and lower losses have also been investigated [15,16,17]. Figure 2 depicts the basic structure of a DC distribution system, illustrating a general protection scheme. The SSCB is built to operate in a unidirectional or bidirectional mode, depending on its placement in the distribution system due to multiple generation sources. The placement of the devices determines the system voltage level, which can range from 28 V for low-level systems, such as lighting, to 1 kV for general distributions [18].

At least two commercial SSCBs have been designed for use in a conventional three-phase AC distribution system, but, currently, the AC breaker remains the most widely used protection device in experimental DC systems. The development of new SSCB technology shows promise for the future of integrated power systems, but the cost associated with new technologies remains a hindrance in the growth of commercial DC systems. Continued research into affordable and reliable protection schemes is essential to the development of efficient clean energy systems. Expanding interests in the DC protection market provide a unique opportunity for the research and growth of future DC distribution systems. In this context, this article investigates the viability of a low voltage SSCB using commercially available low-cost off-the-shelf components.

The SSCB proposed in this article was used to provide the building blocks necessary to anyone interested in the subject, provide insight into possible improvements in the design, and further the research into effective low-cost solutions of SSCB implementation while highlighting the most troublesome areas of the design process, such as switching, thermal requirements, and speed.

The following section details the design process for a unidirectional low voltage SSCB using a silicon IGBT. The SSCB was designed for the low-end protection of lighting and/or other sensitive low current electronics. The device was tested in a laboratory setting, and the results were used to verify the SSCB voltage and current ratings. All external experiments were conducted using randomly generated test conditions to minimize error and improve the output reliability. The materials used in the creation of the device were purchased through an electronics vendor, and information and data sheets are available online.

2. Current Sensor Output

The ACS770ECB current sensor was selected for its continuous current rating of up to 200 A. The device features a high overcurrent rating and a rise time of 4.2 µs (0–60 A). The sensor is of the hall effect-type, and uses the magnetic field generated by the current to produce a linear output voltage. A test of the input current versus output voltage was conducted on the sensor using an omicron CMC 356 relay test set. The input current was varied from 0 to 45 A in 1 A increments and the output voltage was recorded (as shown in Figure 3).

A linear trendline was used to fit the collected data. The corresponding linear equation was found to be

V_a = 0.0204 ∗ I_in + 0.5211,

(1)

where, V_a is the analog voltage output from the sensor and I_in is the input current. The output voltage showed a 20.4 mV increase per amp passing through the sensor. The linear output is essential for the easy implementation of analog to digital conversion (ADC) settings of the SSCB and is further discussed in Section 5.

3. Static Switch Design

The static nature of an SSCB requires the use of a high-side switch capable of a continuous on-time. The most common high-side drive configuration is the bootstrap circuit as it has a low propagation delay. Furthermore, it is simple and inexpensive. However, without modifications, the bootstrap topology is incapable of the continuous on-time needed for SSCB applications [19].

The introduction of an isolated voltage bias to the bootstrap topology provides the continuous operation needed, improves isolation, and simplifies the overall circuit [20]. Several considerations for the voltage bias must be met for successful implementation, and a careful selection process should be adhered to. The bias must be isolated as the secondary voltage will swing with the voltage at the emitter of the IGBT. The converter must have high dv/dt tolerances to keep voltage spikes across the bootstrap capacitor below those that would damage the high-side driver. As the IGBT is a voltage-controlled device, the converter must also have a low voltage drift under no-load conditions, preferably under 10%, in order to maintain the desired output of the converter.

In essence, the converter’s main purpose is to maintain the charge lost due to the gate operation and leakage currents on the bootstrap capacitor, and the following equations found in [19] have been modified to reflect the voltage bias and the static nature of the SSCB. The capacitor is selected based on the gate charge of the transistor and is governed by the following equations:

C_g = Q_g/V_bias,

(2)

C_boot ≥ 10 ∗ C_g,

(3)

where, C_g is the total gate capacitance, Q_g is the gate charge of the transistor, V_bias is the voltage supplied by the converter, and C_boot is the capacitance value of the bootstrap capacitor. Likewise, the high-side gate driver source and sink requirements are dependent on Q_g and are expressed as

I_source = 1.5 ∗ Q_g/t_{sw_on},

(4)

I_sink = 1.5 ∗ Q_g/t_{sw_off},

(5)

where I_source and I_sink are the source and sink requirements of the high-side gate drive, respectively; 1.5 is an empirical constant; and t_{sw_on/}t_{sw_off} are the transition times experienced when switching the transistor on or off, respectively. Finally, a minimum gate resistance must be implemented to ensure that the source and sink currents do not exceed that of the maximum rating of the high-side gate drive and is governed by the following:

Rg_min ≥ Vbias/Isource/sink,

(6)

where R_{g_min} is the minimum gate resistance.

The simplified circuit diagram utilizing an isolated 15 V 1:1 REPCOM DC/DC converter, single output FAN7371MX high-side driver, and IXXH110N65C4 IGBT is shown in Figure 4.

The designed static switch circuit is capable of operating with voltages up to a maximum of 600 V, and the gate driver can supply up to 4 A for source and sink operations. The voltage bias runs at a 1:1 conversion and operates at 15 V and 1 W. The gate charge, Q_g, of the IXXH110N65C4 IGBT is 167 nC. A 0.1 uF ceramic capacitor was selected for C_boot, and a gate resistance of 4.7 ohms was implemented.

Static Switch Experimental Results

The static switch was tested to ensure the safe operation of the voltage bias under any foreseeable condition. The recommended maximum for the safe operating range for the voltage across V_c is 20 V, while the absolute maximum rating is listed at 25 V. It was found that the switch was fully capable of continuous on-time, and two experiments were conducted for the turning on and turning off of the switch to obtain the maximum safe operating region for the voltage bias.

The turn-off experiment shown in Figure 5 was conducted at 30 V/1 A, without a snubber. The voltage across V_c reached a maximum and minimum voltage of 15.9 and 15.1 V, respectively, and poses no threat to the safe operation of the device. The turn-on experiment was run under an open circuit condition to increase the dV/dt of the emitter to its maximum value.

The test voltage was increased until the maximum safe operating area of 20 V across V_c was reached, as shown in Figure 6. The switching period was completed in 50 ns, creating 6 kV/µs dV/dt at the emitter of the transistor. This effect, coupled with the need for voltage bias to recharge the capacitor, created a transient event with a maximum voltage of 19.7 V that lasted roughly 20 µs, before returning to a steady state operation. The test shows that the maximum safe operating area of the device was 300 V as the SSCB must be able to operate under any load, without fear of damage to the switch.

4. Heat and Power Loss

The IXXH110N65C4 IGBT has a high-power density capable of 235 to 110 A of continuous current at 25 and 110 °C, respectively. The short circuit safe operating areas are listed at 600 A for 1 ms and 220 A for 10 µs at 25 and 150 °C, respectively. The switch was heat-tested in open air using a R2A-CT4–38E heatsink to determine the maximum continuous current rating of the SSCB. The experiment was conducted using a DC power source supplying 50.9 V DC to the NHR 4760 DC load bank. The current level was varied from 0 to 10 A, and each level was maintained for a period of no less than 4 min. The maximum surface temperature of the heatsink was recorded via an infrared thermometer using an emissivity of 0.94, and the forward voltage drop was recorded at every step. The power loss of the switch was then calculated, and the results are shown in

Table 1. Experimental results of heat and power loss.

Amperage	Temperature	Forward Voltage Drop	Power Loss
0	23.8	0	0
1	27.2	0.76	0.76
2	32.5	0.825	1.65
3	38.3	0.862	2.586
4	43.3	0.895	3.58
5	47.9	0.925	4.625
6	52.9	0.935	5.61
7	57.6	0.955	6.685
8	64	0.973	7.784
9	69.9	0.99	8.91
10	74.5	1.005	10.05

.

The following equations, derived from Figure 7, were used to predict the on-time losses and temperature rise of the SSCB during a steady state operation:

P_d = 1.0347 ∗ I_c − 0.4667, where I_c ≥ 1 A,

(7)

T_sw = 5.2358 ∗ I_c + 22.013, where I_c ≥ 1 A,

(8)

where I_c is the continuous current of the SSCB, P_d is the power dissipated in the switch, and T_sw is the temperature of the switch. The slope of T_sw indicates that the temperature will increase 5.24 °C above the ambient per amp of continuous current. Combining Equations (7) and (8) reveals a temperature increase of 5.06 °C per watt consumed. The temperature analysis indicates that, under the current open-air conditions, the IGBT’s optimum safe current rating is between 8 and 15 A and a 41.92 °C to 78.6 °C rise above the ambient temperature is to be expected. However, alternate cooling techniques that could be used to improve the thermal performance are discussed in [21] and should be considered when additional current is needed or ambient temperatures are unpredictable.

5. Analog to Digital Conversion

The SSCB was tested using the MEGA 2560 R3 microcontroller. The controller has a 10-bit resolution ADC and operates with a 16 MHz clock. The ADC conversion rate was increased from 9600 Hz to 50 kHz, resulting in one read every 20 µs. The equation governing the output of the ADC converter is

V_a = R_v ∗ 5/1023,

(9)

where V_a is the analog voltage read by the converter and R_v is the integer return value seen by the controller. Equations (1) and (9) were combined to determine the current passing through the SSCB, resulting in the following equation:

I_in = 0.239 ∗ R_v − 25.544.

(10)

Equation (10) was multiplied by 1000 to avoid the use of floating-point numbers and coded as

I_input = 239 ∗ R_v − 25544,

(11)

where I_input = I_in ∗ 1000. The current will be incremented up or down by a minimum of 0.239 A due to the ADC integer return values from 0 to 1023. Therefore, it should be noted that a slight range in variation is to be expected at any given setpoint.

6. ADC-Based Pickup and Clearing Times

The block diagram in Figure 8 shows the SSCB configuration that was implemented in this experiment. The snubbing circuit used in this experiment was a simple RC snubber optimized for 10 A at 1.19 µH of line inductance, as described in [22]. Advanced snubbing circuits are a continuing point of research in SSCBs, as inductances are not always known and can be found in [23,24].

6.1. Experimental Setup

The experiment was conducted at a trip setting of 4 A, where I_input = 4000. The pickup (PU) time was defined as the time taken after the current reached the defined trip setting to the point that the gate drive control signal went from high to low. The total clearing time (TCT) was defined as the time taken for the current to stabilize within two percent of the zero value after reaching the rated trip setting, and the switching time (SWT) was the difference between the two measurements. The test bench and sensing equipment consisted of a Feedback 67–113 200-ohm variable-load resistor, KEYSIGHT AC6804A power supply, KEYSIGHT InfiniVision MSOX4104A oscilloscope, KEYSIGHT N7026A current probe, KEYSIGHT N2790A differential probe, KEYSIGHT N2790A passive probe, and Tektronix PWS2323 DC Power Supply. The AC6804A was used to provide the high-side voltage and current through the switch to the 200-ohm variable-load resistor. The PWS2323 DC power supply was used to power the low-side electronics. The KEYSIGHT oscilloscope and probes were used in all measurements. In total, 25 test inputs were formulated and randomized with varying current levels from 4 to 8 A, and the N7026A current probe was zeroed out at the start of each session. The MSOX4104A oscilloscope was then set to the plus or minus 100 µs range, and each waveform to be measured was set within the expected output levels. The trigger function was set to a negative slope, and the trigger point was set to 500 mA. The MEGA microcontroller was programmed to the designated trip setting, and the 67–113 variable resistor was set to the needed resistance determined by the current that would be delivered to the circuit. The oscilloscope was set to single-waveform capture and the voltage from the AC6804A power source was turned on. The switch was then activated, allowing current to flow through the circuit and the resulting trip was documented as follows.

Cursor Y1 was set to zero and Y2 was set to the trip setting amperage of 4 A, as shown in Figure 9. X1 was then set at the crossing point of Y2, and X2 was set at which the point microcontroller responded. The resulting PU measurement between X1 and X2 was recorded. X2 was then moved to the zero-crossing, as shown in Figure 10, and the resulting TCT measurement was recorded.

The SWT measurement was taken as the difference between the PU and TCT measuring the propagation delay of the high-side driver and the switching action of the circuit. The process was repeated until all 25 inputs were completed. Channel 1 depicts the current (yellow), channel 2 depicts V_CE as shown in Figure 4 (green), and channel 3 shows the logic control signal for the high-side switch from the microcontroller (blue).

6.2. Switching Results

The experimental results are shown in

Table 2. Total clearing time results.

Amperage (A)	Total Clearing Time (µs)					Average (µs)
4	48.33	46.34	46.34	45.75	45.35	46.422
5	47.26	47.3	47.29	47.5	47.31	47.332
6	47.86	47.88	47.85	47.88	47.68	47.83
7	48.44	47.84	48.03	48.02	48.02	48.07
8	48.03	48.04	48.02	48.03	48.03	48.03

,

Table 3. Pickup time results.

Amperage (A)	Pickup Time (µs)					Average (µs)
4	44.43	42.22	42.21	41.59	41.18	42.326
5	43.36	43.36	43.35	43.6	43.34	43.402
6	44.14	44.14	44.12	44.1	43.9	44.08
7	44.78	44.16	44.43	44.4	44.41	44.436
8	44.46	44.5	44.5	44.45	44.46	44.474

and

Table 4. Switching time.

Amperage (A)	Switching Time (µs)					Average (µs)
4	3.9	4.12	4.13	4.16	4.17	4.096
5	3.9	3.94	3.94	3.9	3.97	3.93
6	3.72	3.74	3.73	3.78	3.78	3.75
7	3.66	3.68	3.6	3.62	3.61	3.634
8	3.57	3.54	3.52	3.58	3.57	3.556

.

The overall average response and clearings times for PU, TCT, and SWT were 43.74, 47.53, and 3.79 µs, respectively. As the amperage increases, the TCT and PU have an increasing average, while the SWT shows a decreasing trend of nearly 100 ns/A due to the snubbing circuit’s overdamped response across V_ce at low current levels. The SSCB’s response time, when compared to the generalized curve of its mechanical circuit breaker (MCB) counterpart depicted in Figure 11, shows that the average TCT during an instantaneous fault is greatly reduced by a factor of 1000. Furthermore, slower MCBs often have an instantaneous trip time between 40 and 55 ms, faster units will trip within 16 ms or one 60 Hz cycle [25,26]. The resulting SSCB’s average TCT was 294.7 times faster than that of the single-cycle MCB using purely ADC techniques.

The PU time is the main contributing factor in the speed of the SSCB under test, resulting in 92% of the overall average TCT delay. The PU speed is governed by the speed of the ADC capabilities of the microcontroller used in the experiment. Further reduction of the SSCB response time is accomplished via improved external sensing or faster ADC equipment, but may come at an increased cost to the design. The TCT of the SSCB is important for the success of the overall design due to the lack of large inductances from transformers in DC systems. In many cases, the wire inductance will be the largest limiting factor in the DC system. The change in current over time from a DC source, di/dt, is governed by Equation (12).

di/dt = V_dc/L,

(12)

where V_dc is the system voltage and L is the system inductance. Therefore, a 10-m 8 AWG wire with roughly 13 µH of inductance and a bus voltage of 50 volts would result in a di/dt of 3.85 A/µs, producing a 180.8 A increase in just 47 µs if limited by wire inductance alone. The same fault sustained for 16 ms would reach an excess of 61 kA, causing extreme thermal and physical stress on the system. This problem is further compounded as voltages and wire diameters increase in higher-rated systems [11,18]. Fast, easily programmable SSCBs can be used in tandem with fault-limiting converters and advanced protection algorithms to minimize the effects of extreme faults in the DC system.

7. Conclusions

A unidirectional low voltage SSCB design process was framed, and then constructed and tested, in this study. The assembled SSCB is a viable option for the protection of low-level sensitive equipment in a DC distribution system as the circuit can operate at 50 V/15 A of continuous current, without failure.

The fault clearing speed of the design is limited to an average of 47.53 µs by the speed of the ADC, which is 294.7 times faster than a fast operating AC counterpart.