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Article

A Nonlinear Control Strategy for DC-DC Converter with Unknown Constant Power Load Using Damping and Interconnection Injecting

1
National Active Distribution Network Technology Research Center, Beijing Jiaotong University, Beijing 100044, China
2
School of Automation, Beijing Information Science and Technology University, Beijing 100192, China
*
Author to whom correspondence should be addressed.
Energies 2021, 14(11), 3031; https://doi.org/10.3390/en14113031
Submission received: 26 April 2021 / Revised: 18 May 2021 / Accepted: 20 May 2021 / Published: 24 May 2021
(This article belongs to the Special Issue DC-DC Converters Technologies, Applications and Optimization)

Abstract

:
DC-DC converters with constant power loads are mostly used in DC microgrids. Negative impedance and large disturbances of constant power loads may lead to the instability of DC-DC converters. To address this issue, a nonlinear control strategy consisting of an improved passivity-based controller and nonlinear power observer is proposed in this paper. First, an improved passivity-based controller is designed based on the port-controlled Hamiltonian with dissipation model. By proper damping and interconnection injecting, the fast dynamic response of output voltage and stability of the DC-DC converter is achieved. Second, the constant power load is observed by a nonlinear power observer, which is adopted to estimate the power variation of the constant power load within a small settling time and improve the adaptability of the DC-DC converter under power disturbance. Finally, the simulation and experimental results are presented, which illustrate the proposed control strategy not only ensures the stability of the DC-DC converter under large disturbances, but also can track the desired operating point with low voltage overshoot in no more than 10 milliseconds.

1. Introduction

With the development of the DC Microgrid (DM), the DM is becoming an effective way of distributing power supplies [1,2,3]. Meanwhile, the DC-DC converters (DDCs) are becoming increasingly common and play an important role in the DM due to their advantages in efficiency, flexibility, isolation, controllability, etc. [4].
The typical diagram of DM is shown in Figure 1; the DC sources and loads are commonly connected to DC BUS through the DDCs. The DDC is acting as a load from the input side and exhibits the constant power load (CPL) behavior. The negative impedance characteristic of CPL behavior [5,6] will lead to the instability of the DDC [7,8]. Therefore, it is necessary to develop some advanced control methods which can eliminate the influence of negative impedance on the DDC, achieve the fast dynamic response, and guarantee the DDC stability.
To solve the instability problem of the CPL, linear control methods have been introduced in the literature. In [9,10,11], the small signal model is established in order to analyze the influence of CPL on the stability of the DDC, and the virtual impedance method is proposed to realize the stability of the DDC with CPL. However, as the small signal model is only applicable to linear systems or linearized systems near the desired equilibrium point, the accuracy of the model will decrease in the case of large disturbances [12]. Furthermore, the traditional linear control strategy only provides an accurate control performance in close proximity to the desired equilibrium point and has a slow dynamic response when the CPL changes significantly [13,14]. In summary, research on the stability and control of the DDC using the small signal model has some limitations. Therefore, the numerous nonlinear control strategies are introduced based on large signal.
Based on the affine nonlinear model and feedback linearization control theory [15], the state feedback controller and input/output feedback linearization controller of the DDC with CPL are designed in [16,17], which improve the dynamic response of the converter and enhance the stability of DC voltage. However, they need full state measurement, and have complex controllers and a large dependence on parameters. In order to improve the disturbance rejection ability of the DDC, the active disturbance rejection controller (ADRC) [18] with CPL is designed in [19]; this improves the performance of the converter and has the robustness to face various disturbances and uncertain factors. Although satisfactory disturbance rejection performance of the DDC can be obtained by ADRC, there are many parameters of the controller which need to be determined, and the optimization of these parameters is difficult. The sliding-mode duty-ratio controller is proposed in [20], which can maintain the stability of the DDC in the operating domain under the significant changes in load power and input voltage, and it improves the dynamic response and steady performance of the DDC. However, the controller is very complex, and the output voltage fluctuation of the DDC is large. Moreover, the switching frequency of a sliding-mode controller is not fixed, and the filter design is difficult. In [21], the backstepping controller is designed in order to achieve better dynamic performance and robustness of the DDC. However, the virtual controller needs to be differentiated repeatedly, and becomes complex with the increase in system order.
The passivity-based controller (PBC) [22] has been widely employed in many physical systems [23,24] based on the energy function, and is an effective practical nonlinear control technique due to its simplicity, efficiency, and ease of implementation in comparison to the other nonlinear control techniques. The various types of PBC are designed in [25,26,27] based on the Euler-Lagrange (EL) model and the port-controlled Hamiltonian with dissipation (PCHD) model, which can ensure the large-range stability and reliability of the DDC. However, the output voltage has the steady-state error, and the transient stability of the DDC will be reduced under the variations and uncertainties of system parameters and operating conditions. In [28], the interconnection and damping assignment passivity-based controller (IDA-PBC) is designed based on the PCHD model with PI controller. It can guarantee the stability of the DDC under disturbance. However, the global stability of the DDC cannot be guaranteed, and its dynamic response is slow. In [29], the stability of the cascaded LC filter DDC is realized by the modified IDA-PBC based on the port-controlled Hamiltonian (PCH). However, the control law of this strategy is complex, and does not allow for the principle of parameters design.
To obtain excellent dynamic and steady characteristics of the DDC with CPL, this paper will utilize the DC-DC boost converter (DDBC) to study the stability and control based on the passivity. An improved passivity-based controller (IPBC) is proposed to realize the dynamic response and stability of DDBC based on the PCHD model, and the damping and interconnection injecting in IPBC is determined according to the dynamic energy storage function. Meanwhile, the nonlinear power observer (NPO) is used with IPBC, which can improve the adaptability of DDBC, and ensure the desired operating point tracking when CPL and input voltage change. In summary, the nonlinear control strategy which consists of the IPBC and NPO is proposed in this paper. Finally, the comparative study of the proposed control strategy with IDA-PBC and PBC is verified by detailed simulation and experimental results in this paper, suggesting that the DDBC has a better dynamic response characteristic while ensuring stability by using the proposed control strategy.
This paper is organized as follows. The stability analysis of DDBC with CPL based on passivity is analyzed in Section 2. The IPBC based on PCHD model is proposed in Section 3. The NPO of unknown CPL is designed and the selection principle of IPBC parameters is analyzed in Section 4. Subsequently, some realistic simulation and experimental results are given in Section 5. The conclusion of this paper appears in Section 6.

2. Stability Analysis of DDBC Converter with CPL

2.1. Constant Power Load Characteristic

The U-I characteristic of a CPL is illustrated in Figure 2.
The voltage-current characteristic of a CPL is given by:
i = P CPL u
where PCPL is the power of CPL, i and u are the instantaneous values of input current and voltage of the CPL. For a given operating point M (U I), the rate of change in current can be obtained from (1) as follows:
i u = P CPL U 2
Therefore, the curve representing the current versus voltage for a CPL can be approximated by a straight line tangent to the curve at the operating point. The equation for this line is as follows:
i = 2 P CPL U P CPL U 2 u
According to (3), at a given operating point, a CPL can be equivalent to a controlled current source ICPL in parallel with a negative resistance. RCPL, ICPL and RCPL are given by the following:
I CPL = 2 P CPL U R CPL = U 2 P CPL
From (4), the CPL has a negative impedance characteristic and this will pose negative impact on system performance [30].

2.2. Stability Analysis of DDBC with CPL Based on Passivity

2.2.1. Effect of CPL on Stability of DDBC

The power circuit of DDBC with CPL is shown in Figure 3, where uS is the input voltage; L and C are the inductance and capacitance in DDBC, respectively; iL and iC are the inductor and capacitor current, respectively; uC is the output voltage; iCPL is the current of CPL; T is insulated gate bipolar transistor; sg is the gate drive signal of T; and D is the diode. To facilitate the analysis, the components are considered as ideal devices.
According to the principle of volt-second balancing, the average switch model of DDBC [31] can be given as follows:
L d i L d t = ( σ 1 ) u C + u S C d u C d t = ( 1 σ ) i L P CPL u C
where σ is the duty ratio of sg.
According to (5), the phase portrait and simulation results of DDBC can be concluded when the desired average output voltage UCD = 60 V, desired average inductor current ILD = 2 A, switching frequency f = 10 kHz, PCPL = 60 W, σ = 0.5, L = 2 mH, C = 940 μF, and uS = 30 V.
As shown in Figure 4, the phase portrait displays clearly the characteristics of DDBC with a CPL. The blue line is the trajectory of the state variable (iL, uC); the blue arrow indicates the evolving direction of the trajectory. The state plane is divided into two regions by the separatrix: S. The region above the separatrix is a stable region, and the region below is an unstable region; the DDBC is unstable when the state variable is in the unstable region. Moreover, the trajectory will converge to a limit cycle when the state variable is in the stable region. Due to the existence of the limit cycle, the DDBC cannot operate stably at the desired voltage and current. As can be seen in Figure 5, the state variables oscillate in a periodic steady state. When the oscillation is significant, it is easy to damage the switching devices and capacitors, and result in the damage of the DDBC.

2.2.2. Passivity Analysis of DDBC with CPL

Consider the system with input u and output y as follows:
x ˙ = f ( x , u ) y = h ( x )
The system depicted in (6) exists a nonnegative storage function H(x) and a positive definite function Q(x) such that:
H ( x ( t ) ) H ( x ( 0 ) ) 0 t u T y d τ 0 t Q ( x ) d τ , t > 0
or
H ˙ ( x ) u T y Q ( x )
If H ˙ ( x ) < 0 when Q(x) > 0, the system is said to be strictly passive; it must be internally stable [32].
From (5), it is further changed to:
L i L d i L d t = ( σ 1 ) u C i L + u S i L C u C d u C d t = ( 1 σ ) u C i L P CPL
According to the characteristic of CPL, the PCPL = iCPL2RCPL and RCPL = -uC2/PCPL in DDBC with CPL, the following equation can be obtained by combining the two equations in (9).
L i L d i L d t + C u C d u C d t = u S i L i CPL 2 R CPL
The energy storage function can be expressed as:
H O ( t ) = H L ( t ) + H C ( t ) H L ( t ) = 1 2 L i L 2 ( t ) H C ( t ) = 1 2 C u C 2 ( t )
From (10) and (11), H ˙ O ( t ) can be written as:
H ˙ O ( t ) = u S i L i CPL 2 R CPL
Let the uS = u, iL = y, according to (8) and (12), Q(x) < 0, the DDBC with CPL is non-passive and is the reason why the DDBC cannot work at a constant stable state. Therefore, in order to eliminate the limit cycle in Figure 4 and realize the stable work of the DDBC, the DDBC needs to be passivated.

3. IPBC of DDBC Based on PCHD Model

3.1. PCHD Model of DDBC

In order to establish the PCHD model of DDBC, let inductive magnetic flux x1p = φL = LiL, capacitive charge x2p = qC = CuC, then take the vector as xp = [x1p x2p]T = [LiL CuC]T, the desired state vector is xDP = [x1DP x2DP]T = [LiLDP CuCDP]T, thus the error state vector xE = xPxDP, xE = [x1E x2E]T = [Lil Cuc]T, il and uc are the error of the inductor current and output voltage, respectively. Therefore, (5) can be changed to:
x ˙ 1 P = x ˙ 1 E = x 2 P C + σ x 2 P C + u S x ˙ 2 P = x ˙ 2 E = x 1 P L σ x 1 P L C P CPL x 2 P
According to (13), the PCHD model of DDBC is:
x ˙ E = ( J R ) H ( x P ) x P + J σ x P + u y = H ( x P ) x P
where J is a skew symmetric matrix and satisfies J = −JT, and J = 0 1 1 0 , xPTJxP = 0,
R = 0 0 0 C 2 P CPL x 2 P 2 ;   H ( x P ) = 1 2 L x 1 P 2 + 1 2 C x 2 P 2 ,   H ( x P ) x P = x 1 P L x 2 P C T ;   u = u S 0 ; J σ = 0 σ C σ L 0 .

3.2. IPBC Design of DDBC

In order to overcome the non-passivity and realize the stable work of the DDBC, interconnection and damping injecting are added in (16). If there is a dynamic energy storage function Hp(xP) and a skew symmetric matrix JP = J + Ja, where J a = 0 j a j a 0 , ja > 0, and a positive definite matrix RP = R + Ra, where R a = r a 0 0 g a , ra > 0, ga > 0, ra, ga are positive damping injecting and conductance injecting, the controller of DDBC is taken as
u = ( J P R P ) H P ( x P ) x P ( J R ) H ( x P ) x P J σ x P x ˙ E = ( J P R P ) H P ( x P ) x P
From (15), the dynamic energy storage function Hp(xP) can be written as
H p ( x P ) = H p ( x E ) = 1 2 x E T M P x E     = 1 2 L x 1 E 2 + 1 2 C x 2 E 2
where MP = diag(1/L 1/C).
According (15) and (16), H ˙ p ( x P ) can be obtained
H ˙ p ( x P ) = H ˙ p ( x E ) = x E T M P x ˙ E = H p ( x E ) x E T ( J P R P ) H P ( x E ) x E = r a i l 2 + ( g a + C 2 P CPL x 2 P 2 ) u c 2 < 0
According to (17), MP is a positive-definite matrix and H ˙ p ( x P ) < 0 , H ˙ p ( x P ) is qualified as a Lyapunov function [33], and the passivation of the DDBC with CPL is realized by (15). Therefore, (15) is the IPBC.
From (15), the duty cycle corresponding to the IPBC is represented by
u S = ( 1 + j a ) u c r a i l + ( 1 σ ) u C 0 = ( 1 + j a ) i l ( g a + P CPL u C 2 ) u c + P CPL u C ( 1 σ ) i L
According to the direction of energy flow, the iL should be established first, and the uC should be established later. It can be obtained from the first equation of Equation (19):
σ = 1 u S + ( 1 + j a ) u c + r a i l u C = 1 u S + ( 1 + j a ) ( u C U CD ) + r a ( i L I LD ) u C
where ILD = PCPL/USD.
From (19), duty ratio σ is associated with uC and iL, and a correlation degree is decided by ja and ra. Therefore, the good dynamic and steady state performance of DDBC is obtained by selecting proper ja and ra.

4. Unknown Nonlinear Power Observer and Preferences in IPBC

4.1. Nonlinear Power Observer of Unknown CPL

In practice, the power of CPL may be changed under the influences of various uncertain factors, and the operating point of DDBC may be changed. Therefore, the nonlinear power observer of CPL is introduced in the proposed control strategy to adjust the ILD in real time to ensure the operating point tracking. Learning from [34,35], the NPO of CPL for DDBC can be expressed as
P ^ CPL = 1 2 γ C x 2 2 + P ^ A P ^ ˙ A = γ x 1 x 2 ( 1 σ ) + 1 2 γ 2 C x 2 2 γ P ^ A
where P ^ CPL is the observed value of PCPL, γ is a NPO gain.
Let power observed error be:
P ˜ CPL = P ^ CPL P CPL
According to (21) and (5), P ˜ ˙ CPL is transformed as:
P ˜ ˙ CPL = P ^ ˙ CPL P ˙ CPL = P ^ ˙ CPL = γ ( P ^ CPL P CPL ) = γ P ˜ CPL
Equation (22) can be written compactly as:
P ˜ ˙ CPL + γ P ˜ CPL = 0 P ˜ CPL = e γ t P ˜ CPL ( 0 )
Equation (23) shows that P ˜ CPL goes to zero exponentially. How fast P ˜ CPL goes to zero depends on the magnitude of γ. The larger γ is, the faster P ˜ CPL goes to zero, and P ^ CPL = P CPL . Furthermore, the dynamic response of the NPO needs to be fast enough to adjust the ILD in real time, and ensure the CPL tracking, and the large NPO gain, is selected in general [36]. Therefore, an appropriate γ can be selected to realize effective real-time observation of P ^ CPL on unknown PCPL, and can ensure the operating point tracking when CPL changes.

4.2. Design of Damping Injecting and Conductance Injecting for IPBC

The convergence rate of the output voltage and inductor current is affected by the values of damping injecting ra and conductance injecting ga. Therefore, the parameters are designed from the perspective of energy conservation.
Combining (16) and (17), H ˙ p ( x ) can be expressed as:
H ˙ p ( x P ) = H ˙ p ( x E ) = 1 2 L d i l 2 d t + 1 2 C d u c 2 d t = r a i l 2 + ( g a + C 2 P CPL x 2 P 2 ) u c 2
Equation (24) is further changed to:
H ˙ p ( x E ) = β H p ( x E ) = r a i l 2 + ( g a + C 2 P CPL x 2 2 ) u c 2
where β > 0.
Equation (25) can be transformed as:
H ˙ p ( x E ) + β H p ( x E ) = 0
and
H p ( x E ) = H p ( 0 ) e β t
Equation (27) shows that HP(x) can approach zero exponentially, and the convergence rate of HP(x) depends on β. The larger β is, the faster HP(x) will approach zero. As the HP(x) goes to zero, desired output voltage and inductor current will be realized.
By substituting (16) into (25), it can be expressed as:
r a i l 2 + ( g a + C 2 P CPL x 2 P 2 ) u c 2 = β ( 1 2 L i l 2 + 1 2 C u c 2 )
Originating from (28), ra and ga satisfy:
1 2 L β = r a 1 2 C β = g a + P CPL u C 2
Further, β and ra are selected by:
β = 2 C ( g a + P CPL u C 2 ) r a = L C ( g a + P CPL u C 2 )
According to (30), α and ra depend on ga, PCPL and uC. In order to improve the robustness to the load and let HP(xE) rapidly approach zero, a large ga can be selected. ga is determined by:
g a P CPL u C 2 P CPL U CD 2
Therefore, ra is mainly determined by ga as ga > PCPL/(uC2) according to (30) and (31). This means the tuning of ra is not significantly affected by operating points to ensure the robustness to the load.

4.3. Design of Interconnection Injecting for IPBC

In order to analyze the ability of interconnection injecting ja to track UCD and ILD, substituting (19) into (5) results in a voltage equation of
L d i l d t + r a i l = ( 1 + j a ) u c
It can be seen from (32) that ja is mainly related to the voltage and current. According to (32), when uc > 0 and uC > UCD, il will become a negative incremental trend, which makes the iL and uC decrease; when uc < 0 and uC < UCD, il will become a positive incremental trend, which makes the iL and uC increase. From the dynamic perspective, the regulation speed depends on ja. The larger ja is, the faster the regulation is, which means smaller dynamic error and shorter regulation time. On the contrary, the smaller ja will have the slower adjustment speed and lead to greater dynamic error. Thus, ja can be selected according to the maximum change in CPL to obtain the desired transient response of DDBC.
In summary, the structure of the proposed control strategy is shown in Figure 6. The implementation procedures for the proposed control strategy are as follows:
(1)
First, the parameters γ, ra, and ja are designed according to (23), (30) and (31).
(2)
Second, the power of CPL is estimated according to (20), and ILD is calculated with the measured input voltage.
(3)
Finally, the duty cycle is calculated according to (19) with determined parameters and measured inductor current, output voltage, and input voltage.

5. Simulation and Experimental Results

5.1. Simulation Results

The proposed control strategy in Figure 6 is simulated in MATLAB/Simulink to validate its effectiveness. The system parameters are listed in Table 1. First, the procedure for tuning design parameters is illustrated, then the simulation results under different operating conditions will be presented.

5.1.1. Tuning of Design Parameters

  • NPO Gain
The proposed control strategy consists of NPO for the CPL estimation and IPBC for the output voltage regulation. The dynamic responses of the observed CPL variation and output voltage when the CPL steps from 60 W to 90 W and 90 W to 60 W at 0.5 s under different values of γ (γ = 50, 200, 500, 1000, and 2000) are shown in the following simulations.
It can be observed from Figure 7 and Figure 8 that the NPO and uC can track the CPL variation and UCD with fast dynamic response, and the larger γ will result in a faster convergence rate for output voltage and operating point tracking when the CPL changes. As the CPL steps, the power of the CPL and UCD need to be tracked quickly to maintain DDBC stability, and the large power observer gain is typically selected [37]. Therefore, γ can be selected as 2000 to ensure the faster dynamic response can be obtained. This set of the parameters will be used in the simulations and experiments below to verify the feasibility of the proposed control strategy, and show its advantage in terms of dynamic characteristics by comparing with other strategies.
2.
Positive Damping Injecting and Conductance Injecting
From (25), (30) and (31), the convergence rate of HP(xE) depends on ga and ra, and impacts on the dynamic response of the uC. The dynamic responses of the uC when the CPL steps from 60 W to 90 W and 90 W to 60 W at 0.5 s under different values of ga and ra (ga = 1, ra = 2.12; ga = 2, ra = 4.24; ga = 3, ra = 6.36; ga = 4, ra = 8.48; ga = 5, ra = 10.6) are shown in Figure 9.
It can be observed from Figure 9 that the larger ga and ra will lead to a faster convergence rate for HP(xE), and the uC can track the UCD within a short transition while the voltage fluctuation peak is lower. Thus, the proper values of ga and ra should be selected to obtain a fast dynamic response of uC while avoiding a large voltage overshoot.
3.
Interconnection Injecting
Figure 10 shows the simulation results of the output voltage dynamic response when the CPL steps from 60 W to 90 W and 90 W to 60 W at 0.5 s with different values of ja (ja = 3, 5, 7, 9 and 11).
It is clearly observed in Figure 10 that a larger ja will lead to a shorter settling time and a lower voltage fluctuation peak for the UCD tracking. Thus, ja can be selected at a larger value in order to obtain a better dynamic response of uC.
In order to further verify the influence of control parameters on DDBC stability, and guide the selection of parameters, the phase portraits of DDBC using IPBC under different value of parameters are shown in Figure A1 and Figure A2 (Appendix A). It can be observed that larger ga, ra, and ja will lead to a larger unstable region. According to the influence of control parameters on dynamic response and stability, the ga, ra and ja can each be made a compromise choice. Therefore, ga and ra can be selected as 3 and 6.36, respectively, and ja can be selected as 7; these parameters will be used in the following simulations and experiments.
Based on the selection of the above parameters, the phase portrait of DDBC by using IPBC as shown in Figure 11 is compared with Figure 4; the output voltage and inductor current can converge to the desired equilibrium point P and realize the stable work of the DDBC.

5.1.2. Simulation Verification

Simulations are carried out based on MATLAB/Simulink to validate the proposed control strategy. The simulation parameters are shown in Table 1 of DDBC with CPL, and used in the simulations for comparative purpose. To verify the advantages of the proposed control strategy, the IDA-PBC [28] and PBC [22] are implemented for the DDBC with the same simulation parameters. The uC is considered to operate into a steady state when it fluctuates at UCD ± 0.2 V.
  • Step Change in uS
Figure 12 shows the simulation results of the output voltage when uS steps from 30 V to 40 V at 0.5 s with different control strategies. The uC has approximately 21 V deviation from the UCD when the PBC is used, while the steady-state output voltage error is eliminated by using the proposed control strategy and IDA-PBC. Furthermore, the voltage overshoot of the proposed control strategy is less than 0.2 V, significantly smaller than the IDA-PBC under the uS steps, and it has the faster convergence rate for UCD.
2.
Step Change in PCPL
Figure 13 gives the comparison results of the output voltage when the CPL steps from 60 W to 90 W at 0.5 s and 90 W to 60 W at 1 s with different control strategies.
As shown in Figure 13, the output voltage performances of the proposed control strategy, IDA-PBC and PBC, can be obtained. Comparing the simulation results, the uC has approximately 3.5 V deviation from the UCD when the PBC is used, and the PBC cannot realize the operating point tracking when the CPL steps. Meanwhile, the steady-state output voltage error is eliminated by using the proposed control strategy and IDA-PBC, and the voltage overshoot of proposed control strategy is significantly smaller than the IDA-PBC. Moreover, the uC has the faster dynamic performance by using the proposed control strategy, and it can track the UCD accurately within a very short transition, which is much better than the IDA-PBC. Therefore, the proposed control strategy can realize the faster convergence rate of operating point tracking when the CPL steps.
Based on the simulation results of Table 2 and Table 3, the proposed control strategy can ensure the faster dynamic performance and stability of DDBC, and realize the accurate output voltage and operating point tracking.

5.2. Experimental Results

The experimental system setup is shown in Figure 14, and the experimental parameters are the same as Table 1. It consists of a boost converter, a DC source, an oscilloscope, and a DC electronic load which is used to emulate the CPL. The uC of the DDBC is considered to enter a steady state when the output voltage fluctuates at UCD ± 1 V.
  • Step Change in uS
The impact of the uS steps is shown in Figure 15. In Figure 15a, the uC has little or no overshoot, and quickly tracks the UCD when the uS steps from 30 V to 40 V by using the proposed strategy. In Figure 15b,c, the output voltage overshoots are much larger than the proposed control strategy, and the uC of PBC has approximately 23 V deviation from the UCD when the PBC is used. Therefore, compared to other control strategies, the proposed control strategy can track the UCD within a very short transition, and has better dynamic response when the uS changes.
2.
Step Change in PCPL
As shown in Figure 16a, when the CPL steps from 60 W to 90 W and 90 W back to 60 W, the output voltage has the overshoot below 1 V and then drops back to UCD by using the proposed strategy. However, in Figure 16b, the PBC cannot track the desired value and has approximately 8 V deviation from the UCD under the CPL steps. In Figure 16c, the overshoot of output voltage is much larger than the proposed control strategy, and the settling time is more than 350 milliseconds using IDA-PBC. Thus, the proposed control strategy can realize the faster convergence rate of uC and ensure the operating point tracking when the CPL changes significantly.
Based on the experiment results from Table 4 and Table 5, the proposed control strategy can ensure DDBC stability with a fast dynamic performance, and realize the accurate output voltage and operating point tracking under various disturbances. The dynamic response and overshoot for experimental cases are slightly slower and larger than the corresponding simulation results. This is acceptable, as in the simulation studies the ideal CPL with the step change is used, whereas in the experimental tests, the uS and CPL steps are restricted by their controller bandwidth. Moreover, the experimental results suffer from real-life system conditions such as Electro-Magnetic Interference (EMI), noise, delays, and various uncertainties disturbances which are not considered in the simulations.

6. Conclusions

The instability problem caused by the CPL for DDBC is addressed in this paper. To solve this problem, the stability of DDBC with CPL is studied based on passivity, and the nonlinear control strategy which consists of the IPBC and NPO is proposed. First, the IPBC is studied using damping and interconnection injecting based on the PCHD model and the parameters of IPBC are designed from the perspective of energy conservation. From the phase portraits of DDBC, the stability of DDBC is realized by IPBC. Second, the adaptability of the DDBC is improved as the CPL and input voltage change through the design of NPO. The NPO with large γ is employed to estimate load power with a fast dynamic response to ensure the accurate desired operating point tracking. Meanwhile, extensive numerical simulation and experimental results are given to verify the validity of the proposed control strategy. Under different large disturbances, both results indicate that the output voltage has the voltage overshoot below 1 V and can accurately track the UCD within 10 milliseconds by using the proposed strategy, which are significantly better than PBC and IDA-PBC. Furthermore, the consistency of simulation and experimental results is validated. Finally, the proposed control algorithm is also applicable to other DDC topologies.

Author Contributions

Conceptualization, J.W.; methodology, M.W. and F.T.; validation, M.W. and F.T.; formal analysis, M.W. and J.N.; investigation, M.W. and Y.Z.; writing—review and editing, M.W. and F.T.; supervision, X.W. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by National Natural Science Foundation, grant number 51777012, Natural Science Foundation of Beijing—Education Committee Joint Funding Project, grant number KZ201911232045, and Science and technology project of China Southern Power Grid Company Limited, grant number 090000KK52190002.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

The data presented in this study are available on request from the corresponding author. The data are not publicly available as the data also forms part of an ongoing study.

Conflicts of Interest

The authors declare no conflict of interest.

Appendix A

Figure A1. Phase portraits of DDBC with different ga and ra when feeding CPL. (a) ga = 1 and ra = 2.12; (b) ga = 2 and ra = 4.24; (c) ga = 3 and ra = 6.36; (d) ga = 4 and ra = 8.48; (e) ga = 5 and ra = 10.6.
Figure A1. Phase portraits of DDBC with different ga and ra when feeding CPL. (a) ga = 1 and ra = 2.12; (b) ga = 2 and ra = 4.24; (c) ga = 3 and ra = 6.36; (d) ga = 4 and ra = 8.48; (e) ga = 5 and ra = 10.6.
Energies 14 03031 g0a1aEnergies 14 03031 g0a1b
Figure A2. Phase portraits of DDBC with different ja when feeding CPL. (a) ja = 3; (b) ja = 5; (c) ja = 7; (d) ja = 9; (e) ja = 11.
Figure A2. Phase portraits of DDBC with different ja when feeding CPL. (a) ja = 3; (b) ja = 5; (c) ja = 7; (d) ja = 9; (e) ja = 11.
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Figure 1. Typical diagram of DM.
Figure 1. Typical diagram of DM.
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Figure 2. The U-I Characteristic Curve of CPL.
Figure 2. The U-I Characteristic Curve of CPL.
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Figure 3. Power Circuit of Boost Converter with CPL.
Figure 3. Power Circuit of Boost Converter with CPL.
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Figure 4. Phase portrait of DDBC.
Figure 4. Phase portrait of DDBC.
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Figure 5. Voltage and current of DDBC under open control. (a) output voltage and desired output voltage; (b) inductor current, CPL current, desired inductor current, and CPL current.
Figure 5. Voltage and current of DDBC under open control. (a) output voltage and desired output voltage; (b) inductor current, CPL current, desired inductor current, and CPL current.
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Figure 6. The structure of the proposed control strategy.
Figure 6. The structure of the proposed control strategy.
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Figure 7. Simulated CPL observation of the different γ when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
Figure 7. Simulated CPL observation of the different γ when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
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Figure 8. Simulated uC responses of the different γ when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
Figure 8. Simulated uC responses of the different γ when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
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Figure 9. Simulated uC responses of the different ga and ra when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
Figure 9. Simulated uC responses of the different ga and ra when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
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Figure 10. Simulated uC responses of the different ja when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
Figure 10. Simulated uC responses of the different ja when CPL steps up and down. (a) CPL: 60 W to 90 W; (b) CPL: 90 W to 60 W.
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Figure 11. Phase portrait of DDBC by using IPBC when feeding CPL.
Figure 11. Phase portrait of DDBC by using IPBC when feeding CPL.
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Figure 12. The simulation results of the different control strategies under input voltage mutation.
Figure 12. The simulation results of the different control strategies under input voltage mutation.
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Figure 13. The simulation results of the different control strategies under CPL steps. (a) 60 W to 90 W at 0.5 s; (b) 90 W to 60 W at 1 s.
Figure 13. The simulation results of the different control strategies under CPL steps. (a) 60 W to 90 W at 0.5 s; (b) 90 W to 60 W at 1 s.
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Figure 14. Experimental system setup.
Figure 14. Experimental system setup.
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Figure 15. uC and iL experiment results of the different control strategies when uS steps from 30 V to 40 V. (a) The proposed control strategy; (b) PBC; (c) IDA-PBC.
Figure 15. uC and iL experiment results of the different control strategies when uS steps from 30 V to 40 V. (a) The proposed control strategy; (b) PBC; (c) IDA-PBC.
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Figure 16. uC and iL experiment results of the different control strategies when CPL steps up and down (60 W to 90 W and 90 W to 60 W, respectively). (a) The proposed control strategy; (b) PBC; (c) IDA-PBC.
Figure 16. uC and iL experiment results of the different control strategies when CPL steps up and down (60 W to 90 W and 90 W to 60 W, respectively). (a) The proposed control strategy; (b) PBC; (c) IDA-PBC.
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Table 1. Simulation parameters of DDBC.
Table 1. Simulation parameters of DDBC.
SymbolsParameter NamesValues
uSInput voltage30 V
UCDDesired average output voltage60 V
ILDDesired average inductor current2 A
PCPLRated power60 W
CCapacitance940 μF
LInductance2 mH
fSSwitching frequency10 kHz
jaInterconnection injecting7
raPositive damping injecting6.36
gaConductance injecting3
γPower observer gain2000
Table 2. Simulation results for uC of DDBC under different control strategies and input voltage disturbances.
Table 2. Simulation results for uC of DDBC under different control strategies and input voltage disturbances.
Input Voltage DisturbanceControl StrategyFluctuation
Peak Value
of uC(V)
Transient Time
of uC (ms)
Steady State Error (V)
30 V to 40 VProposed control strategy≈0≈0≈0
PBC [22]21-21
IDA-PBC [28]3.133≈0
Table 3. Simulation results for uC of DDBC under different control strategies and CPL disturbances.
Table 3. Simulation results for uC of DDBC under different control strategies and CPL disturbances.
CPL
Disturbance
Control StrategyFluctuation
Peak Value
of uC(V)
Transient Time
of uC (ms)
Steady State Error (V)
60 W to 90 WProposed control strategy0.52≈0
PBC [22]3.9-3.5
IDA-PBC [28]0.816≈0
90 W to 60 WProposed control strategy0.52≈0
PBC [22]3.5-3.5
IDA-PBC [28]0.816≈0
Table 4. Experimental results for uC of DDBC under different control strategies and input voltage disturbances.
Table 4. Experimental results for uC of DDBC under different control strategies and input voltage disturbances.
Input Voltage DisturbanceControl StrategyFluctuation
Peak Value
of uC(V)
Transient Time
of uC (ms)
Steady State Error (V)
30 V to 40 VProposed control strategy ≈0≈0≈0
PBC [22]23-23
IDA-PBC [28]5500≈0
Table 5. Experimental results for uC of DDBC under different control strategies and CPL disturbances.
Table 5. Experimental results for uC of DDBC under different control strategies and CPL disturbances.
CPL
Disturbance
Control StrategyFluctuation
Peak Value
of uC(V)
Transient Time
of uC (ms)
Steady State Error (V)
60 W to 90 WProposed control strategy <1≈0≈0
PBC [22]8-8
IDA-PBC [28]7380≈0
90 W to 60 WProposed control strategy <1≈0≈0
PBC [22]8-8
IDA-PBC [28]6360≈0
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Wang, M.; Tang, F.; Wu, X.; Niu, J.; Zhang, Y.; Wang, J. A Nonlinear Control Strategy for DC-DC Converter with Unknown Constant Power Load Using Damping and Interconnection Injecting. Energies 2021, 14, 3031. https://doi.org/10.3390/en14113031

AMA Style

Wang M, Tang F, Wu X, Niu J, Zhang Y, Wang J. A Nonlinear Control Strategy for DC-DC Converter with Unknown Constant Power Load Using Damping and Interconnection Injecting. Energies. 2021; 14(11):3031. https://doi.org/10.3390/en14113031

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Wang, Mian, Fen Tang, Xuezhi Wu, Jingkai Niu, Yajing Zhang, and Jiuhe Wang. 2021. "A Nonlinear Control Strategy for DC-DC Converter with Unknown Constant Power Load Using Damping and Interconnection Injecting" Energies 14, no. 11: 3031. https://doi.org/10.3390/en14113031

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