1. Introduction
With the development of power electronic technology, the requirements for power electronic conversion circuits are constantly increasing. Power converters are widely used in the applications of electric vehicle charging [
1], photovoltaic systems [
2,
3], HVDC systems, and flexible ac transmission systems (FACTS) [
4]. From the perspective of safety and reliability, it is usually required that the converter has the function of galvanic isolation. Therefore, the three-phase isolated matrix converters with a high-frequency transformer (HFT) have drawn lots of attention due to their superior performance, such as power factor correction [
5,
6,
7], high power density, and low harmonic current distortion [
8,
9]. Therefore, three-phase isolated matrix converters have broad applications in the fields of electric vehicles, photovoltaic power generation systems, grid-connected converters [
10], micro grids [
11,
12], fuel cell power systems, and battery chargers [
13].
For three-phase isolated matrix converter circuits, the DC-link current ripple is one of the most important issues. Excessive DC-link current ripple not only increases the inductor loss and switching loss but also causes more electromagnetic interference and grid current distortion. In practice, the DC-link current ripple can be reduced by increasing the switching frequency or increasing the inductor size of the output filter [
14]. However, a higher switching frequency will result in higher switching losses, and a larger output inductor will increase the size and cost of the converter. At present, there are several methods based on the SVPWM algorithm that can reduce dc ripple [
15,
16,
17]. Additionally, therefore, optimizing the modulation control strategy is more attractive to address the above issue.
To deal with the problems caused by the DC-link current ripple, a method by setting the zero vector in a smart way is proposed for a three-phase converter in [
16]. Though this method can reduce the current ripple, it suffers high switching losses due to the increasing switching actions. Another way is presented in [
18,
19] for the Z-source converter to reduce the DC-link current ripple, which is implemented by selecting the vectors and adjusting shoot-through time. In this way, the inductor current changes alternately in each switching cycle, which effectively suppresses the DC-link current ripple.
For a back-to-back current-source converter, another interesting solution is presented in [
20] by coordinating the gating sequences of both the rectifier and inverter to reduce the current ripple. The idea is interesting, but it is only effective for the back-to-back current-source converters, which blocks its application.
The duty cycle loss and output current ripple of two different PWM schemes had been further studied and discussed in [
21]. The proposed “six-segment” PWM scheme has the characteristics of small output current ripple and low duty cycle loss, which means that a smaller output inductance can be used. Besides, an optimized PWM scheme is proposed to reduce the current ripple in [
22]. In addition, the proposed six-segment PWM scheme has lower switching loss and lower duty cycle loss, as well as a low THD with duty-cycle compensation.
In this paper, an optimized modulation control strategy for the three-phase isolated matrix converters is proposed to effectively reduce the DC-link current ripple. Moreover, the proposed scheme features potential benefits to increase power density. The rest of this paper is organized as below: in
Section 2, the inherent limitation of the conventional modulation scheme is revealed. Then, in
Section 3, the new optimal modulation scheme is proposed for the isolated matrix converters to reduce the current ripple by the optimal arrangement of vector sequences. Following that, the simulation and experiment results for three-phase isolated matrix converters are given to compare the performance of different SVPWM strategies in
Section 4 and
Section 5. Finally, conclusions are drawn in
Section 6.
3. Proposed Solution
As shown in the previous section, it is hard to reduce the DC-link current ripple with conventional SVPWM by synthesizing the reference vector with two adjacent active vectors
,
, and one zero vector. In order to reduce the DC-link current ripple effectively, the space vector is divided into 12 sectors, as shown in
Figure 6. In this section, an optimal scheme is proposed by employing six non-nearest vectors in each sector to synthesize the reference vector to solve the above problem.
Table 2 shows the current vectors, switching sequence, and the corresponding primary side voltage of the HFT. It indicates that the primary side voltage is determined by the current vectors and line voltage.
Figure 7 shows the relationship of the bridge output voltage
Udc, the amplitude of line–line voltage
Vi, and the vector angle
θ of the reference vector. From
Figure 7, the line–line voltage in each sector is monotonic. From (1), the DC-link current ripple Δ
i can be optimized depending on the bridge output voltage
Udc, which is determined by the switching states, as shown in
Table 2; that is, the DC-link current ripple would be high if
Udc steps from the highest to lowest one depending on the vector sequence.
Taking the range of −30° to 30° as an example, and assuming that the current reference is located in sector 1, which is shown in
Figure 8, the DC-link current ripple would be decided by the vector sequence. The vector sequence of the traditional modulation scheme is
, and the corresponding
Udc would be
Vab,
Vac, 0 and
Vac >
Vab > 0; consequently, the high current ripple would be caused by
Udc steps from the highest line-line voltage to 0 when
. In order to solve the problem, an optimum scheme with the main idea to synthesize the current reference vector with available non-nearest vectors is proposed. Instead of using zero vector and guaranteeing only one switch action when the vector changes, the proposed solution used the optimum vector sequence
, and the maximum step change of
Udc can be avoided. Therefore, compared with the conventional solution, the proposed scheme can significantly reduce the DC-link current ripple. Next, a detailed theoretical analysis will be derived.
Different from the conventional current source rectifier, the primary side voltage of the HFT must be alternating positive and negative to maintain the volt-sec balance. Therefore, taking reference vector located in sector 1, for example, three active vectors
I1,
I2, and
I3 are used in the positive half-cycle, and the active vectors
I4,
I5, and
I6 are used in the negative half-cycle. Based on the above analysis,
Table 3 shows the corresponding relationship between the 12 sectors and the vector sequence.
When the reference vector is located in the odd sector (1, 3, 5, 7, 9, 11), the dwell times of each vector can be calculated by
When the reference vector is located in the odd sector (2, 4, 6, 8, 10, 12), the dwell times of each vector can be calculated by
By combining (1) and (6)–(7), the DC-link current ripple can therefore be calculated in (8). Additionally,
Figure 5b shows the increasing/decreasing trend of the current ripple of the proposed scheme.
From (8) and
Figure 5b, the peak–peak value of the DC-link current ripple of the proposed scheme can be defined as
As shown in
Figure 5, it can be observed that the proposed solution can effectively mitigate the DC-link current ripple compared with the conventional solution.
Figure 9 shows the control algorithm, which can be summarized into the following seven steps:
4. Simulation Results
In order to verify the effectiveness of the theoretical analysis, comparative simulations in MATLAB/Simulink with the proposed SVPWM strategy and the conventional scheme for the three-phase isolated matrix converter are carried out. The MATLAB/ Simulink model consists of the main circuit and control module, where the IGBT is used for the main circuit of matrix converter, and the S-function is used to implement the control module of space vector modulation algorithm, as shown in
Figure 10. The simulation parameters are listed in
Table 4.
Figure 11 shows the rectifier bridge output voltage and DC-link current ripple waveforms under the different inductance values. It can be observed that the traditional modulation scheme produces a large DC-link current ripple when
Udc steps from the highest line voltage to 0. On the contrary, the proposed solution employs the optimum vector sequence, which can effectively avoid the maximum step change of
Udc. As a consequence, the DC-link ripple of the proposed solution is much lower than that of the conventional one.
Figure 12 shows the filter inductor current waveforms under the different inductance values. It can be clearly seen that the peak-to-peak current ripples of the traditional scheme are 2.07 A, 1.32 A, and 1 A at 1 mH, 1.5 mH, and 2 mH inductance values, respectively. From
Figure 12b, the peak-to-peak current ripple of the proposed scheme are 1.36 A, 0.9 A, and 0.68 A with corresponding inductance values; that is to say, the maximum DC-link ripple of the proposed scheme is much lower than that of the conventional one. It is also noted that the smaller the inductance, the better the current ripple reduction.
For analysis of simulation, it can be seen that compared with the traditional scheme, the new scheme can reduce the DC-side inductance current ripple only by changing the modulation strategy without increasing the inductance value and switching frequency.
For easier viewing, the peak-to-peak current ripple of the traditional scheme and the proposed scheme with different inductance values are summarized in
Figure 13. It can be observed that the proposed scheme can effectively reduce peak-to-peak current ripple compared with the conventional solution. In other words, for a given current ripple requirement, the DC-link inductor can be designed as a smaller size and lower inductance and cost.
5. Experimental Results
To verify the proposed SVPWM strategy for the three-phase isolated matrix converter, a lab prototype is built, as shown in
Figure 14. Texas Instruments DSP TMS320F28335 and FPGA XC6SLX9-2TQG144C are used to implement the control algorithm. Detailed parameters of the experiment are listed in
Table 5.
Figure 15 and
Figure 16 show the experimental waveforms of the conventional SVPWM. The overall and detailed enlarged waveforms of the primary and secondary voltages of the transformer are shown in
Figure 15, and it can be seen that the measured waveforms of the primary and secondary voltages of the transformer step from a higher voltage amplitude to a lower one and they are characterized by the alternatively positive and negative variations. It is also noted that the voltage amplitudes of the primary and secondary sides are approximately the same since the transformer ratio is designed to be 1:1.
Figure 16 shows the experimental waveforms of the output voltage and DC-link inductor current with the conventional solution. The current ripple is large since the SVPWM modulation is not optimized.
Figure 17 shows the experimental comparison of the conventional and proposed solutions from the viewpoint of the rectifier bridge output voltage and DC-link current ripple. The experimental parameters are listed in
Table 5. It can be seen that the DC-link current ripple has been reduced from 0.5 A (conventional scheme) to 0.3 A (proposed scheme), and the corresponding current ripple factors are 45.4% and 27.3%, respectively. Consequently, the experimental results verify the effectiveness of the proposed strategy that can significantly reduce the DC-link current ripple, which is in agreement with the theoretical analysis in
Figure 12.