Second Harmonic Current Reduction Control for Two-Stage Inverter with a New Inductor Current Feedback Path

Abstract

The instantaneous output power of the two-stage inverter pulsates at twice the output frequency, resulting in the second harmonic current (SHC) in the front-end dc-dc converter. To reduce the SHC in the inductance branch while maintaining good dynamic performance, this paper proposes a control scheme based on a new inductor current feedback path in the front-end buck converter. In the scheme, through the equivalent gain, the virtual resistor, and the bandpass filter, the inductor current is fed to the front of the voltage regulator. The feedback function simplification is studied and the implementation of the proposed scheme is illustrated. With considerations of both reducing the SHC and improving the dynamic performance, the parameter design approach for the feedback function is also presented for the proposed SHC reduction control scheme, and the performance analysis and comparison from the viewpoint of output impedance are provided. The simulation model and the prototype of a 10 kW two-stage inverter are constructed. The simulation and experimental results about the low SHC in the front-end buck converter and the fast dynamic response during the load transient verify the effectiveness of the proposed scheme.

1. Introduction

The two-stage inverter is composed of a front-end dc-dc converter and a downstream single-phase inverter, which is widely used for the power supply with a wide input voltage range [1,2,3,4]. The instantaneous output power of the single-phase inverter fluctuates at twice the output frequency (2f_o), resulting in the second harmonic current (SHC) in the inductance branch of the front-end dc-dc converter [5,6]. The SHC will increase the current stress and power losses of the power switches and the magnetic components, decrease the energy conversion efficiency, and shorten the lifespan of the dc source such as fuel cells and batteries [7,8,9]. Thus, it is necessary to reduce the SHC in the dc-dc converter.

The SHC reduction approaches can be classified into two categories. The first approach is to provide the additional hardware circuit for the two-stage inverter. In [10], an improved circuit consists of an isolated dc/dc converter and interconnection inverter, which achieves the dc active filter function and reduces the ripple current to approximately 20% of that of the conventional circuit. An active low-frequency ripple control device based on the virtual capacitor concept is proposed [11], and the low-frequency ripple current caused by the single-phase inverter can be compensated by introducing a current integrator. Moreover, an SHC compensator (SHCC) is adopted to buffer the ripple power in a single-phase power factor correction converter and a single-phase inverter [12,13], and the SHCC is connected to the dc bus and the port current is required to follow the SHC [12]. A virtual impedance is introduced to be in parallel with the port of the SHCC for compensating the SHC, and the virtual impedance is realized by feeding forward the SHCC port voltage [13]. The suppression of the SHC in the frontend dc-dc converter with dc transformer resonant converter is investigated [14], and the preregulator or postregulator is necessary to regulate the output voltage. In summary, an additional hardware circuit is essential for SHC reduction in the above approaches [10,11,12,13,14], and it is evident that the extra circuit increases the complexity, volume, and cost of the overall inverter.

The second approach is to reduce the SHC by the appropriate control scheme for the front-end dc-dc converter. In [15,16], the secondary component in the input current of the single-phase inverter is extracted and fed to the voltage regulator to compensate for the current fluctuation, which can suppress the SHC in the front-end dc-dc converter, whereas the accurate dc bus capacitance is necessary and the dynamic performance in the voltage control mode is relatively general. In [17], the second harmonic component in the inductor current is calculated with the small signal model, then a compensation controller is designed based on the calculation results, which can compensate the second harmonic in the two-stage inverter, however, the calculation is very complex and dependent on the accuracy of the model. In [18], a load current feedforward method for the dual active bridge dc-dc converter is proposed to increase the output impedance at 2f_o and reduce the SHC, but it is not appropriate for other dc-dc converter structures. In [19], by adding the inductor current feedback to the back of the current regulator through a bandpass filter (BPF), the presented BPF inserted inductor current feedback method can increase the output impedance of the dc-dc converter, thereby suppressing the SHC. However, the virtual impedance will decrease with the increase in the loop gain, which limits the reduction ability of the SHC. In [20], the introduction of the inner current loop on the basis of the voltage control mode can suppress the current pulsation in the dc-dc converter, whereas the low crossover frequency of the outer voltage loop will affect the dynamic performance of the inverter. In [21], a resonant controller is inserted between the voltage regulator and the current regulator in the forward path, which can reduce the second harmonic component, but the resonant controller limits the loop gain and the dynamic performance. In [22], the notch-filter-inserted load current feedforward scheme (NF-LCFFS) with the virtual parallel impedance is proposed, which can suppress the SHC by the inner inductor current loop and improve the dynamic response of the front-end dc-dc converter by the load current feed-forward path. Based on the NF-LCFFS, the notch-filter-inserted current reference plus load current feedforward scheme (NF-CR+LCFFS) is also proposed in [22], which can further increase the output impedance of the dc-dc converter at 2f_o and reduce the SHC. Meanwhile, the crossover frequency of the voltage outer loop in the NF-CR+LCFFS can be increased to improve the dynamic performance.

To further reduce the SHC as well as improve the dynamic performance in the two-stage inverter without adding any extra circuit, this paper proposes a new inductor current feedback path scheme (NICFPS) for the front-end dc-dc converter. By virtue of the virtual resistance and the BPF, this scheme introduces a new feedback path for the inductor current, and the feed point is in the front of the voltage regulator. In this way, the output impedance of the front-end dc-dc converter at 2f_o can be increased obviously, so the SHC can be reduced effectively. Meanwhile, the dynamic response of the front-end dc-dc converter can also be improved by increasing the crossover frequency of the outer voltage loop. Moreover, the simulation and experimental results verify the effectiveness of the proposed scheme.

This paper is organized as follows. The SHC mechanism of a two-stage inverter with buck dc-dc converter is studied in Section 2. Section 3 presents the virtual resistance-based NICFPS and its implementation approach. Section 4 designs the key parameters in the feedback function for the proposed NICFPS, and gives a performance comparison of the output impedance with different control schemes. Based on a 10 kW two-stage inverter, the proposed NICFPS is verified by simulation and experiment in Section 5 and Section 6. Finally, Section 7 concludes this paper.

2. SHC Mechanism of Two-Stage Inverter

Figure 1a gives the configuration of the two-stage inverter studied in this paper, where the front-end dc-dc converter is a buck converter and the downstream inverter is a single-phase inverter. Figure 1b shows the equivalent schematic diagram. In Figure 1, U_in and i_in are the input voltage and input current of the converter, respectively; C_bus and U_bus are the capacitor and voltage of the intermediate dc bus, respectively; i_o and U_o are the output current and output voltage of the inverter, respectively; i_C is the capacitor current; i_inv is the input current of the inverter; L is the inductor; i_L is the inductor current.

Figure 1. Two-stage inverter. (a) Configuration; (b) equivalent schematic diagram; (c) block diagram for Z_L(s).

The instantaneous output power of the single-phase inverter pulsates at twice the output frequency, and the input current of the inverter can be expressed as [22]

$$i_{\mathrm{inv}}=\frac{U_{\mathrm{m}}{i}_{\mathrm{m}}}{2U_{\mathrm{bus}}}\cos \phi -\frac{U_{\mathrm{m}}{i}_{\mathrm{m}}}{2U_{\mathrm{bus}}}\cos (2{\omega }_{\mathrm{o}}t-\phi )=i_{\mathrm{dc}}+i_{2\mathrm{nd}}$$

(1)

where U_m and i_m are the amplitudes of the output voltage and the output current, respectively; φ is the load impedance angle; ω_o is the angular frequency; ω_o = 2πf_o, and f_o is the frequency of the output voltage.

It can be seen from Equation (1) and Figure 1b that i_inv is composed of two parts, one is the dc component i_dc, and the other is the SHC component i_2nd, which is provided by the intermediate bus capacitor branch and inductor branch. Hence, the SHC proportion in the front-end buck converter is determined by the inductor branch impedance Z_L(s) of the buck converter and the impedance of C_bus at 2f_o. Moreover, C_bus is always designed large enough to achieve a very low dc-link voltage ripple, and the SHC in i_in is mainly caused by the inductor branch [22,23]. Thus, the SHC suppression in i_L can effectively reduce the input power fluctuation and the SHC on the input side.

3. Proposed Control Scheme with New Inductor Current Feedback Path

In this section, a new control method is presented for the SHC reduction and the dynamic performance improvement, which can increase the Z_L(s) at 2f_o and decrease the Z_L(s) at frequencies except for 2f_o. Based on Figure 1c, the virtual impedance is introduced into the inductance current branch, then by the transformation and simplification, the novel control method and implementation of the NICFPS are presented.

3.1. Introduction of Virtual Resistor and BPF

The control block diagram with the introduction of a virtual resistance r_s and a BPF is shown in Figure 2a, where U_ref is the reference value of bus voltage; G_v(s) is the transfer function of the voltage regulator; G_i(s) is the transfer function of the current regulator; G_notch(s) is the transfer function of the notch filter; H_v is the voltage feedback gain; H_i is the current feedback gain; R_L is the series equivalent resistance of the inductor; G_pwm is the PWM gain; G_pwm = U_in/V_m, and V_m is the amplitude of the carrier.

Figure 2. Introduction of virtual resistance and BPF. (a) Block diagram; (b) equivalent transformation.

The transfer function of the notch filter can be derived as

$$G_{\mathrm{notch}}(s)=\frac{A_{\mathrm{VF}}(s^2+{\omega }_{\mathrm{o}}{}^2)}{s^2+2(2-A_{\mathrm{VF}}){\omega }_{\mathrm{o}}+{\omega }_{\mathrm{o}}{}^2}$$

(2)

where A_VF is the gain of the passing frequency range.

The transfer function G_BPF(s) of a BPF is expressed as

$$G_{\mathrm{BPF}}(s)=\frac{{\omega }_{\mathrm{b}}s}{s^2+{\omega }_{\mathrm{b}}s+{(2{\omega }_{\mathrm{o}})}^2}$$

(3)

where ω_b is the angular frequency bandwidth.

As seen in Figure 1c and Figure 2a, the introduction of r_s and G_BPF(s) in Figure 2a can be helpful to increase the Z_L(s) of the front-end converter at 2f_o, thereby suppressing the SHC. Meanwhile, the crossover frequency of the outer voltage loop in Figure 2a can be increased by changing its parameters. Therefore, the introduction of r_s and G_BPF(s) in Figure 2a can both suppress the SHC and improve the dynamic performance of the front-end buck converter. Based on Figure 2a, the equivalent transformation is shown in Figure 2b. As seen in Figure 2b, the inductor current feedback function consists of two terms, one is r_sG_BPF(s), and the other is H_v + 1/(G_v(s)G_i(s)G_pwm). To realize the control scheme, the second term should be simplified.

3.2. Simplification of Feedback Function

To simplify the feedback function in Figure 2b, it is necessary to simplify 1/G_v(s) and 1/G_i(s). The proportion-integral (PI) controller is adopted, then the transfer function G_PI(s) and the corner frequency f_L can be expressed as

$$G_{\mathrm{PI}}(s)=K_{\mathrm{p}}+K_{\mathrm{i}}/s$$

(4)

$$f_{\mathrm{L}}=K_{\mathrm{i}}/2\pi K_{\mathrm{p}}$$

(5)

where K_p is the proportional gain; K_i is the integral gain.

By setting K_p = 1, the Bode diagram of 1/G_PI(s) with different f_L is shown in Figure 3. As seen with the decrease in f_L, the magnitude of 1/G_PI(s) is closer to the constant value, and the phase of 1/G_PI(s) at 2f_o is closer to zero. However, according to Equation (5), the lower integral gain with the lower f_L will degrade the steady-state performance of the buck converter. Based on the above analysis, f_L = 5 Hz is determined for the PI regulator. When f_L = 5 Hz, the phase delay is only 2.8° and the amplitude is almost constant for 1/G_PI(s) at 2f_o.

Figure 3. Bode diagram of 1/G_PI(s) with different f_L.

When f_L = 5 Hz, the Bode diagram of 1/G_PI(s) with the different K_p is shown in Figure 4. As seen with the increase in K_p, the amplitude of 1/G_PI(s) at 2f_o decreases gradually, and the phase of 1/G_PI(s) at 2f_o almost remains constant. Thus, it is clear that the simplification of 1/G_PI(s) is independent of K_p, 1/G_PI(s), and H_v + 1/(G_v(s)G_i(s)G_pwm) in the feedback function and can be equivalent to the constant value at 2f_o, derived as

$$K_{\mathrm{PI}}=\mathrm{Mag}\left[\frac{1}{G_{\mathrm{PI}}(j2\pi \cdot 2f_{\mathrm{o}})}\right]$$

(6)

$$K_{\mathrm{f}}=\mathrm{Mag}\left[H_{\mathrm{v}}+\frac{1}{G_{\mathrm{pwm}}{G}_{\mathrm{v}}(j2\pi \cdot 2f_{\mathrm{o}})G_{\mathrm{i}}(j2\pi \cdot 2f_{\mathrm{o}})}\right]$$

(7)

Figure 4. Bode diagram of 1/G_PI(s) with different K_p when f_L = 5 Hz.

3.3. Proposed NICFPS and Implementation

After the simplification of the feedback function, the control block diagram of the proposed NICFPS is shown in Figure 5a.

Figure 5. Proposed NICFPS. (a) Block diagram; (b) implementation.

As seen from Figure 5a, the sampled inductor current, after passing the equivalent gain K_f, the virtual resistance r_s and the BPF are fed to the dc bus reference voltage U_ref, which is the distinctive feature of the proposed NICFPS. The actual implementation of the NICFPS is shown in Figure 5b and it is obvious that the scheme is easy to implement by software. It should be noted that Figure 5 shows only the equivalent implementation method, the actual meaning of the proposed NICFPS from Figure 2 is to add the virtual resistance between U_bus and i_L to reduce the SHC.

4. Parameter Design and Performance Analysis

The main parameters in the feedback function, including the current and voltage regulator parameters, equivalent gain K_f, the virtual resistance r_s, and the bandwidth f_b of the BPF, will be designed in this section.

The parameters of the inverter prototype are shown in Table 1, which are used for the theoretical analysis, simulation, and experimental verification in this paper.

Table 1. Parameters of the prototype.

Parameter	Value
Input voltage (Uin)	550 V
Output voltage (Uo)	220 V
Intermediate bus voltage (Ubus)	450 V
Output frequency (fo)	50 Hz
Switching frequency (fs)	10 kHz
Filter inductor (L)	1.7 mH
Intermediate bus capacitor (Cbus)	1500 μF
Output power (Po)	10 kW
Equivalent series resistor (RL)	0.02 Ω
PWM gain (Gpwm)	550
Voltage feedback gain (Hv)	1/600
Current feedback gain (Hi)	1/150

4.1. BPF Parameter Design

It can be seen from Figure 5a that the inner current loop gain T_{i_NICFPS} can be expressed as

$$T_{\mathrm{i}\_\mathrm{NICFPS}}(s)=\frac{H_{\mathrm{i}}{G}_{\mathrm{pwm}}{G}_{\mathrm{i}}(s)}{sL+R_{\mathrm{L}}+\frac{1}{s{C}_{\mathrm{bus}}}}$$

(8)

The crossover frequency f_ci of the inner current loop is usually selected to be 1/5 to 1/10 of the switching frequency to guarantee excellent tracking ability [22]. Hence, when 1/10 is selected, we have f_ci = 1 kHz.

According to Equations (4) and (5), the transfer function of the current regulator at f_ci can be derived as

$$G_{\mathrm{i}}(j2\pi f_{\mathrm{ci}})=K_{\mathrm{pi}}+(-j{K}_{\mathrm{pi}}\frac{f_{\mathrm{Li}}}{f_{\mathrm{ci}}})$$

(9)

where K_pi and f_Li are the proportional gain and corner frequency of the current regulator, respectively.

When f_Li = 5 Hz, it is evident that f_ci is much larger than f_Li. Hence, according to Equation (9), we have G_i(j2πf_ci) ≈ K_pi.

The magnitude of the inner current loop has a unity gain at f_ci. According to Equation (8), (10) can be obtained.

$$\left|T_{\mathrm{i}\_\mathrm{NICFPS}}(j2\pi f_{\mathrm{ci}})\right|=\frac{2\pi f_{\mathrm{ci}}{C}_{\mathrm{bus}}{H}_{\mathrm{i}}{G}_{\mathrm{pwm}}{K}_{\mathrm{pi}}}{\sqrt{{(1-4{\pi }^2{f}_{\mathrm{ci}}{}^2{C}_{\mathrm{bus}}L)}^2+{(2\pi f_{\mathrm{ci}}{C}_{\mathrm{bus}}{R}_{\mathrm{L}})}^2}}=1$$

(10)

Then from Equation (10), K_pi can be derived as

$$K_{\mathrm{pi}}=\frac{\sqrt{{(1-4{\pi }^2{f}_{\mathrm{ci}}{}^2{C}_{\mathrm{bus}}L)}^2+{(2\pi f_{\mathrm{ci}}{C}_{\mathrm{bus}}{R}_{\mathrm{L}})}^2}}{2\pi f_{\mathrm{ci}}{C}_{\mathrm{bus}}{H}_{\mathrm{i}}{G}_{\mathrm{pwm}}}$$

(11)

From Equations (5) and (11), the current regulator is obtained as

$$G_{\mathrm{i}}(s)=2.9+\frac{90}{s}$$

(12)

For the outer voltage loop, the higher crossover frequency means better dynamic performance. Moreover, the effect of the BPF in the voltage loop is similar to that of the notch filter in the forward path in [22], so the crossover frequency f_cv of the voltage loop should be less than the center frequency of the BPF. To improve the dynamic response while reducing the influence of the BPF on the stability margin, f_cv = 50 Hz is determined.

Based on Figure 5a, the outer voltage loop gain T_{v_NICFPS} can be expressed as Equation (13). The magnitude of the outer voltage loop has a gain unity at f_cv, then Equation (14) is obtained.

$$T_{\mathrm{v}\_\mathrm{NICFPS}}(s)=\frac{H_{\mathrm{v}}{G}_{\mathrm{v}}\left(\mathrm{s}\right)G_{\mathrm{i}}\left(\mathrm{s}\right)G_{\mathrm{pwm}}}{s{C}_{\mathrm{bus}}[sL+R_{\mathrm{L}}+G_{\mathrm{pwm}}{H}_{\mathrm{i}}{G}_{\mathrm{i}}(s)+G_{\mathrm{pwm}}{K}_{\mathrm{f}}{r}_{\mathrm{s}}{G}_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{BPF}}(s)]+1}$$

(13)

$$\left|T_{\mathrm{v}\_\mathrm{NICFPS}}(j2\pi f_{\mathrm{cv}})\right|=1$$

(14)

According to Equation (14), the proportional gain K_pv of the voltage regulator can be derived as

$$K_{\mathrm{pv}}=\frac{\sqrt{{(1-4{\pi }^2{f}_{\mathrm{cv}}{}^2{C}_{\mathrm{bus}}L)}^2+{(2\pi f_{\mathrm{cv}}{C}_{\mathrm{bus}}{G}_{\mathrm{pwm}}{H}_{\mathrm{i}}{K}_{\mathrm{pi}})}^2}}{H_{\mathrm{v}}{K}_{\mathrm{pi}}{G}_{\mathrm{pwm}}}$$

(15)

From Equations (5) and (15), the voltage regulator is derived as

$$G_{\mathrm{v}}(s)=0.7+\frac{20}{s}$$

(16)

Based on Equations (7), (12) and (16), the equivalent gain K_f in the feedback function can be obtained.

4.2. Determination of Virtual Resistor Value

The SHC suppression ratio is used to determine the minimum value of the virtual resistor. By setting the reference voltage to zero, the control block diagram in Figure 5a can be equivalently transformed into that in Figure 6.

Figure 6. Block diagram for the gain from i_inv to i_L.

Based on Figure 6, the transfer function G_ii(s) from i_inv to i_L can be derived as Equation (17). The corner frequency f_Lv of the voltage regulator is much lower than 2f_o, hence when f_Lv = 5 Hz, we have G_v(j2π·2f_o) ≈ K_pv. For the reason that 2f_o is the center frequency of both the BPF and the notch filter, the magnitude of G_BPF(s) is around 1 at 2f_o, and the magnitude of G_notch(s) is nearly 0 at 2f_o.

Defining |G_ii(j2π·2f_o)| as the SHC suppression ratio and α as the SHC suppression requirement, then Equation (18) can be obtained from Equation (17). In general, α is required to be less than 5%, i.e., α ≤ 5% [19]. When α is set to 5%, by substituting Equations (11) and (15) into (18), it can be deduced that the requirement of virtual resistance is r_s ≥ 15.5 Ω.

$$G_{\mathrm{ii}}(s)=\frac{i_{\mathrm{L}}(s)}{i_{\mathrm{inv}}(s)}=\frac{s{C}_{\mathrm{bus}}{H}_{\mathrm{i}}{G}_{\mathrm{notch}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}+H_{\mathrm{v}}{G}_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}+1}{s{C}_{\mathrm{bus}}(sL+R_{\mathrm{L}}+G_{\mathrm{i}}(s)G_{\mathrm{pwm}}{H}_{\mathrm{i}}+r_{\mathrm{s}}{K}_{\mathrm{f}}{G}_{\mathrm{BPF}}(s)G_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}})+H_{\mathrm{v}}{G}_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}+1}$$

(17)

$$\left|G_{\mathrm{ii}}(j2\pi \cdot 2f_{\mathrm{o}})\right|=\frac{\sqrt{{(H_{\mathrm{v}}{G}_{\mathrm{pwm}}{K}_{\mathrm{pv}}{K}_{\mathrm{pi}}+1)}^2}}{\sqrt{{(1+H_{\mathrm{v}}{G}_{\mathrm{pwm}}{K}_{\mathrm{pv}}{K}_{\mathrm{pi}}-16{\pi }^2{f}_{\mathrm{o}}{}^2{C}_{\mathrm{bus}}L)}^2+{(4\pi f_{\mathrm{o}}{C}_{\mathrm{bus}}{H}_{\mathrm{i}}{G}_{\mathrm{pwm}}{K}_{\mathrm{pi}}+4\pi f_{\mathrm{o}}{r}_{\mathrm{s}}{K}_{\mathrm{f}}{C}_{\mathrm{bus}}{K}_{\mathrm{pi}}{G}_{\mathrm{pwm}}{K}_{\mathrm{pv}})}^2}}\le \alpha$$

(18)

To obtain the inductor branch impedance Z_{Lv_NICFPS}(s), U_ref in Figure 5a is set to 0, then the block diagram in Figure 5a can be transformed into that shown in Figure 7. Based on Figure 7, the inductor branch impedance can be obtained as Equations (19) and (20). When α ≤ 5% and r_s ≥ 15.5 Ω, the magnitude plots of Z_{Lv_NICFPS}(s) with different r_s are shown in Figure 8.

Figure 7. Block diagram for Z_{Lv_NICFPS}(s) of the proposed scheme.

Figure 8. Magnitude plots of Z_{Lv_NICFPS}(s) with different r_s.

As can be seen from Figure 8, Z_{Lv_NICFPS}(s) will increase with the increase in r_s in the wide frequency range near 2f_o, which shows that the SHC suppression capability will improve, but the dynamic performance will deteriorate. The reason is that the actual BPF is not ideal, r_s will affect the inductor branch impedance not only at 2f_o but also at frequencies except for 2f_o. In view of both the SHC and the dynamic performance, r_s = 20 Ω is determined.

$$Z_{\mathrm{Lv}\_\mathrm{NICFS}}(s)=\frac{sL+R_{\mathrm{L}}+G_{\mathrm{pwm}}{H}_{\mathrm{i}}{G}_{\mathrm{i}}(s)[1-G_{\mathrm{notch}}(s)]+K_{\mathrm{f}}{r}_{\mathrm{s}}{G}_{\mathrm{BPF}}(s)G_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}}{1+G_{\mathrm{v}}(s)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}{H}_{\mathrm{v}}+s{C}_{\mathrm{bus}}{G}_{\mathrm{notch}}\left(\mathrm{s}\right)G_{\mathrm{i}}(s)G_{\mathrm{pwm}}{H}_{\mathrm{i}}}$$

(19)

$$Z_{\mathrm{Lv}\_\mathrm{NICFS}}(j2{\omega }_{\mathrm{o}})=\frac{j2{\omega }_{\mathrm{o}}L+R_{\mathrm{L}}+G_{\mathrm{pwm}}{H}_{\mathrm{i}}{G}_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})+K_{\mathrm{f}}{r}_{\mathrm{s}}{G}_{\mathrm{v}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{pwm}}}{1+G_{\mathrm{v}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{pwm}}{H}_{\mathrm{v}}}$$

(20)

4.3. Design of Bandwidth for BPF

Figure 9 shows the magnitude plots of the Z_{Lv_NICFPS}(s) with different BPF bandwidth fb. It is obvious that, as f_b increases, Z_{Lv_NICFPS}(s) grows larger at low frequency, decreasing the dynamic response. Thus, f_b should not be too large in view of the dynamic performance. Meanwhile, when f_b is too small, such as the value lower than 10 Hz, the magnitude change of Z_{Lv_NICFPS}(s) at low frequency is not quite obvious. Moreover, f_b should be greater than the fluctuation range of 2f_o [15,18]. Thus, in /the inverter illustrated in Table 1, f_b in the feedback function is designed as 10 Hz.

Figure 9. Magnitude plots of Z_{Lv_NICFPS}(s) with different f_b.

4.4. Output Impedance Comparison

The magnitude of the output impedance can be used to evaluate the performance of SHC reduction and dynamic response during the load transient. The higher magnitude of the output impedance at 2f_o means the better ability for SHC reduction, and the lower magnitude at frequencies except for 2f_o means the lower bus voltage overshoot and undershoot during the load transient.

In the existing typical control schemes, the NF-LCFFS and NF-CR+LCFFS in [22] have a relatively high performance of SHC reduction and dynamic response. Hence, to evaluate the performance of the proposed NICFPS, this section compares the output impedance among the proposed NICFPS and the two abovementioned schemes, in which scheme I and scheme II indicate the NF-LCFFS and NF-CR+LCFFS, respectively.

The block diagram of the three schemes is shown in Figure 10. Compared with scheme II, the proposed NICFPS requires the additional parameter design for r_s, f_b, and K_f, however, the parameters can be easily determined only by the simple calculation and output impedance comparison as described in Section 4.

Figure 10. Control block diagram of the three schemes: Scheme I and Scheme II are both from Reference [22].

In the three schemes, the parameters of the current regulator and crossover frequency of the inner current loop are the same. In order to reduce the SHC effectively, the crossover frequency of the outer voltage loop is selected as 10 Hz in scheme I, and 50 Hz in both scheme II and the proposed NICFPS.

Based on Figure 10 in this paper and Equations (21) and (23) in the Reference [22], inductor branch impedance at 2f_o for schemes I and II can be derived as

$$Z_{\mathrm{Lv}\_\mathrm{SchemeI}}(j2{\omega }_{\mathrm{o}})=\frac{j2{\omega }_{\mathrm{o}}L+R_{\mathrm{L}}+G_{\mathrm{pwm}}{H}_{\mathrm{i}}{G}_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})}{1+G_{\mathrm{v}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})G_{\mathrm{pwm}}{H}_{\mathrm{v}}}$$

(21)

$$Z_{\mathrm{Lv}\_\mathrm{SchemeII}}(j2{\omega }_{\mathrm{o}})=j2{\omega }_{\mathrm{o}}L+R_{\mathrm{L}}+G_{\mathrm{pwm}}{H}_{\mathrm{i}}{G}_{\mathrm{i}}(j2{\omega }_{\mathrm{o}})$$

(22)

According to Equations (20)–(22), the magnitude plots of the inductor branch impedance of the buck converter with the three schemes are shown in Figure 11. It can be seen from Figure 11 that, at frequencies except for 2f_o, the proposed NICFPS and scheme II have lower output impedance, which means better dynamic performance. Moreover, the proposed NICFPS has the highest output impedance at 2f_o, which indicates the best SHC suppression ability among the three schemes.

Figure 11. Magnitude plots of output impedance.

5. Simulation Results

To verify the effectiveness of the proposed NICFPS, the simulation results of about a 10 kW two-stage inverter with the parameters in Table 1 are provided. The simulation model is built by MATLAB software, and based on that, the proposed NICFPS and the two typical schemes are tested.

Figure 12 shows the steady-state simulation results of the three schemes with the 10 kW output power. As seen, the SHC proportion in i_L is around 4.3% in the NICFPS, while 32.6% in scheme I and 10% in scheme II. It is obvious that the proposed NICFPS has the best ability to suppress the SHC, and the reason is that the scheme has the highest output impedance at 2f_o, which can be seen in Figure 11.

Figure 12. Steady-state simulation results. (a) Scheme I; (b) Scheme II; (c) proposed NICFPS.

Figure 13 shows the dynamic simulation results of the three schemes, and the load of the inverter changes between 33% and 100% full load. As seen, in the proposed NICFPS and scheme II, the undershoots of U_bus are both close to 50 V and the settling times are both about 50 ms when the load steps up, the overshoots of U_bus are both 33 V, and the settling times are both nearly 100 ms when the load steps down. However, in the scheme I, the settling time is about 200 ms, and the undershoot and overshoot are 58 V and 36 V, respectively. It can be seen from Figure 13 that scheme I has the evident overshoot and undershoot during the load transient, and the proposed NICFPS and scheme II have better dynamic performance. This is because scheme I has the highest output impedance almost at all frequencies, but the proposed NICFPS and scheme II can reduce the output impedance at the frequencies except for 2f_o, and the characteristic comparison of the output impedance among the three schemes can be seen from Figure 11.

Figure 13. Dynamic simulation results between 33% and 100% full load. (a) Scheme I; (b) Scheme II; (c) proposed NICFPS.

Based on Figure 12 and Figure 13, Table 2 gives the simulation results of the three control schemes in terms of the SHC proportion and voltage fluctuation during load transient. The results in Table 2 show that the proposed NICFPS has both the best ability to suppress SHC and good dynamic performance. Moreover, the simulation results are in accordance with the theoretical analysis in Section 4.

Table 2. Simulation results comparison.

Performance	Scheme I	Scheme II	NICFPS
SHC proportion	32.6%	10%	4.3%
Undershoot (V/ms)	58/185	48/53	47/45
Overshoot (V/ms)	36/217	33/98	33/93

6. Experimental Results

To further verify the aforementioned theoretical analysis and simulation results, a 10 kW prototype is developed and tested with the three control schemes, namely, scheme I (NF-LCFFS), scheme II (NF-CR+LCFFS), and the proposed NICFPS. The experimental platform is shown in Figure 14, which mainly consists of a two-stage inverter, a control board, an oscilloscope, and a debugging computer. The two-stage inverter is composed of a front-end buck converter and a downstream single-phase inverter. The microprocessor of the inverter is TMS320F28335 from TI company. The parameters of the prototype are listed in Table 1.

Figure 14. Experimental platform.

Figure 15 shows the steady-state experimental results of the three schemes with 10 kW ac output power. It can be seen from Figure 15 that the SHC proportion in the proposed NICFPS is about 4.7%, while in scheme I it is 33.2% and in scheme II it is 11.1%. Thus, it is clear that the proposed NICFPS has the best effect on the SHC reduction because the highest output impedance at 2f_o can be obtained for the scheme as shown in Figure 11.

Figure 15. Steady-state experimental results. (a) Scheme I; (b) Scheme II; (c) proposed NICFPS.

Figure 16 shows the dynamic experimental results of the three schemes, and the ac load of the inverter changes between 33% and 100% full load. In the proposed NICFPS and scheme II, the undershoots of U_bus are both close to 50 V and the settling times are both about 50 ms when the load steps up, the overshoots of U_bus are both 33 V, and the settling times are both nearly 100 ms when the load steps down. However, in scheme I, the settling time is even close to 230 ms, and the undershoot and overshoot are 61 V and 38 V, respectively. It is obvious that the NICFPS and scheme II have better dynamic performance. The reason is that the proposed NICFPS and scheme II can reduce the output impedance at the frequencies except for 2f_o, which can be seen in Figure 11.

Figure 16. Dynamic experimental results between 33% and 100% full load. (a) Scheme I; (b) Scheme II; (c) proposed NICFPS.

Table 3 summarizes the experimental results comparison of the three control schemes in terms of the SHC proportion and the bus voltage fluctuation when the output power step changes between a 33% and 100% rated load. As seen, the proposed NICFPS has the best ability to suppress the SHC since it has the highest magnitude of the output impedance at 2f_o. Meanwhile, due to the lower output impedance at the frequencies except for 2f_o, the proposed NICFPS and scheme II have better dynamic performance than scheme I.

Table 3. Experimental results comparison.

Performance	Scheme I	Scheme II	NICFPS
SHC proportion	33.2%	11.1%	4.7%
Undershoot (V/ms)	61/193	49/57	48/49
Overshoot (V/ms)	38/228	34/107	33/98

In brief, among the three control schemes, the proposed NICFPS has the best SHC reduction ability and dynamic performance. Furthermore, comparing the SHC proportion, overshoot, and undershoot in Table 3 with those in Table 2, it can be seen that the experimental results are well in agreement with the simulation results in Section 5 and the theoretical analysis in Section 4.

7. Conclusions

This paper focuses on the SHC reduction for the two-stage inverter with the front-end buck converter. To reduce the SHC, the virtual resistance and the BPF in a new feedback path are introduced to increase the output impedance at 2f_o, and the control method of the NICFPS is proposed after simplifying the feedback function. In consideration of both the SHC reduction and the dynamic response improvement, the parameter design approach for the feedback function is further presented for the proposed NICFPS. The implementation method of the NICFPS is illustrated, and the output impedance derivation and the performance analysis are provided, which indicate that compared to the existing control methods, the proposed NICFPS can remarkably decrease the SHC while still maintaining good dynamic performance. The simulation model and the experimental prototype for a 10 kW two-stage inverter are built and tested, and simulation and experimental results verify the effectiveness of the proposed control scheme. The SHC proportion can be reduced to about 4.7% in the proposed NICFPS, 33.2% in scheme I, and 11.1% in scheme II. The undershoot and settling time can be reduced close to 50 V and 50 ms in the proposed NICFPS, and 61 V and 230 ms in scheme I.