An Improved Charge-Based Method Extended to Estimating Appropriate Dead Time for Zero-Voltage-Switching Analysis in Dual-Active-Bridge Converter

Abstract

This paper presents a comprehensive analysis of zero-voltage-switching (ZVS) realization with an improved charge-based method by considering both voltage dependency parasitic capacitance and dead time in dual-active-bridge (DAB) converters, when the voltage ratio between the primary and secondary sides does not match the turn ratio of the transformer. For this purpose, a unified equivalent circuit is proposed to represent the switching motions at all possible switching instances under the condition of one-leg manipulation. The combinations of switching cases can be presented in a table to build the corresponding equivalent circuit for ZVS analysis. Combined with the improved charge-based method, the common solutions of the minimum required switching current and the appropriate dead-time range for each equivalent circuit to realize ZVS are deduced. The allowable range of the dead time for ZVS as a function of the switching current is analyzed to determine the appropriate dead time. Once the switching current and dead-time range are derived, the model-based lowest switching current control method can be used to achieve ZVS by using the appropriate amount of both factors. Experiments using a 4 kW DAB prototype were conducted to verify the theoretical analyses.

1. Introduction

Over recent years, the dual-active-bridge (DAB) converter has been widely studied as an interface converter for various applications that require galvanic isolation, a high-voltage step-up/-down ratio, and bidirectional power flow control [1,2,3], for example, in vehicle-to-grid (V2G)-capable electric vehicle (EV) chargers, solid-state transformers (SSTs), and supercapacitor-based energy storage systems. By applying the conventional modulation method, the single-phase-shift (SPS) method, the DAB converter can easily achieve zero-voltage switching (ZVS) when the voltage ratio is fixed at its designated value without additional circuitry [4]. ZVS realization can effectively reduce the switching losses and electro-magnetic interference (EMI) emissions, especially for the areas where high-switching frequency converters are widely applied [5]. Moreover, ZVS operation can also reduce the risk of malfunction and the breakdown of power devices [6]. As another method of soft switching, zero-current switching (ZCS) is also an important technique in the research of bidirectional converters [7]. However, certain switching losses are still generated during the turning-on process compared with ZVS in a DAB converter. Thus, the research on ZVS in DAB converters has received much attention.

In some applications, such as energy storage using batteries and supercapacitors, and power conversions for an active power decoupling [8], a varying input voltage can be applied. However, once the input voltage deviates from the desired value, ZVS operation can be lost in some parts of the operation range. To address the above problem, many studies have been conducted over the past decade. A switched auxiliary inductor to change the equivalent magnetizing inductance has been proposed for extending the ZVS range in [9]. One of the drawbacks of this method is that additional components are needed; therefore, the power density can be reduced. Another major approach is using the so-called burst mode [10,11,12]. However, the switching transients present at the exchanging of the active and inactive periods cannot realize ZVS. In similar approaches, some modulations using a variable switching frequency have been proposed in [13,14,15]. Increasing the switching frequency can extend the range of ZVS in low-power operations. However this extension cannot be infinitely increased and the other losses related to the frequency can be increased. In addition to the above methods, ZVS-range extensions based on some advanced modulation strategies, such as an extended-phase shift (EPS), a dual-phase shift (DPS) and a triple-phase shift (TPS), by introducing a higher degree of freedom, have been introduced in [16,17,18,19,20].

Most research [12,13,14,16,17,18,19,20] discusses the switching condition to judge the ZVS under a current-based method, in which the current direction at the switching instant is simply used to judge whether the switching is ZVS or not. A charge-based method is much more precise method than the current-based method [21,22]. It judges ZVS considering if the charge stored in the parasitic capacitance of switches has totally been released before the switches turn on. With this method, the actual switching current needed to complete the ZVS can be obtained. Based on this approach, some works have proposed controlling the critical switching current for ZVS with optimized operations from certain aspects [21,23]. Moreover, an improved charge-based method, which considers the non-linearity of the parasitic capacitance of semiconductor devices, has been introduced. In [24], the ZVS judgement, in particular, the operating conditions of the EPS, is analyzed with the improved charge-based method. This can provide a much more accurate estimation of the required switching current to ensure the ZVS.

However, the switching current is not the sole required condition to achieve ZVS. An appropriate dead time is also needed. The charge-based method with considering the non-linear parasitic capacitance can estimate the process during the dead time accurately; however, it has not been applied to discuss the appropriate dead time in terms of ZVS realization. A strategy to determine the dead time, including the margin for possible error and a method to realize ZVS in actual converters, is a beneficial topic that will be discussed later on in this paper.

This paper applies the improved charge-based method, which considers the voltage dependency of the parasitic capacitance of devices, to discuss the appropriate dead-time period. For this purpose, a unified equivalent circuit used to consider all the possible switching conditions and any phase-shift modulations is proposed for the first time. Based on the equivalent circuit, the equation of the minimum required switching current to ensure ZVS is deduced. Then, a comprehensive analysis on characteristics of dead time is performed and the acceptable dead-time range as a function of the switching current is discussed so that strategies to determine the dead time can be discussed.

A 4 kW laboratory prototype of the DAB converter was used to verify the above theoretical research. The model-based lowest switching current control proposed in [23] for EPS was taken as an example to verify the appropriate dead-time period with enough of a margin of the switching current for ZVS.

2. Unified Equivalent Circuit for Switching Instant in DAB Converters

2.1. Model of Dual-Active-Bridge Converter

The configuration of the DAB converter is shown in Figure 1. The DAB converter consists of two H-bridges and a medium-frequency transformer (MFT) with a turn ratio of $N:1$. $V_1$ and $V_2$ are the DC terminal voltages of the input and output. L is the primary-side referred equivalent inductance of the transformer. The voltage ratio is defined as $k=V_1/\left(N{V}_2\right)$. The power devices are operating under the switching frequency of $f_{\mathrm{sw}}$.

Phase-shift modulations are the most widely used modulation techniques in DAB converters. Schematic waveforms of three typical methods, SPS, EPS and TPS, are shown in Figure 2. $S_1$∼$S_8$ are the gate signals for the corresponding switches in Figure 1. In all the modulations, switches are controlled by 50% duty ratio signals and the phase-angle differences between them are controlled. Using different phase-shift relationships of gate signals, two- or three-level square voltages are generated in the port voltages of two full bridges, $v_{\mathrm{ab}}$ and $v_{\mathrm{cd}}$. All the possible patterns to achieve cyclic and symmetric port voltages can be classified into three modulation schemes.

The schematic waveforms with SPS, which have a two-level port voltage on both sides, are shown in Figure 2a. The phase-shift difference between the two-level port voltage is expressed by its per-unit value as $D_{\delta }$ and it is the sole control freedom in SPS for controlling power. In EPS, a three-level voltage is involved on one side, as shown in Figure 2b. Thus, another phase-shift ratio expressed as $D_{\mathrm{f}}$ is introduced to this side. TPS is the most general modulation, which has a three-level voltage on both sides. The inherent phase-shift ratios in the primary and secondary sides are expressed as $D_{\mathrm{fp}}$ and $D_{\mathrm{fs}}$, respectively. Thus, SPS and EPS are unique cases of TPS.

2.2. Unified Equivalent Circuit

To analyze ZVS realization, all the switching instants that cause changes in the port voltages should be analyzed. In any switching instances, only one or two legs are manipulated, while the others are kept as they are. The conditions where two legs are manipulated at the same time only happen in SPS and EPS.

A unified equivalent circuit, as shown in Figure 3, can be used to analyze all the possible switchings in the above modulations. The considered leg is composed by upper and lower devices, $S_{\mathrm{U}}$ and $S_{\mathrm{L}}$, respectively. $V_{\mathrm{DC}}$ is the DC terminal voltage of the operating side. $V_{\mathrm{eq}}$ is the equivalent voltage source that represents the port voltage of the other side bridge converted to the operating side, ${V_{\mathrm{port}}}^{\prime }$. It should be mentioned that ${V_{\mathrm{port}}}^{\prime }$ is equal to $N{v}_{\mathrm{cd}}$, which can be $+N{V}_2$, $-N{V}_2$ and zero, for considering the primary-side bridge, and $v_{\mathrm{ab}}/N$, which can be $+V_1/N$, $-V_1/N$ and zero, for considering the secondary-side bridge. Then $V_{\mathrm{eq}}$ is determined in accordance with the status of the other leg in the same bridge, and can be $+{V_{\mathrm{port}}}^{\prime }$ or $-{V_{\mathrm{port}}}^{\prime }$. $L_{\mathrm{eq}}$ is the equivalent series inductance converted to the operating side.

The leg which connects to the positive pole of the port voltage is defined as the left leg, and the leg which connects to the negative pole of the port voltage is defined as the right leg.

All the possible combinations of the switching leg, switching motion, and other conditions are listed in

Table 1. List of all possible combinations of switching cases and the corresponding results of $V_{\mathrm{eq}}$ in phase-shift modulations.

#	Switching	Switching	Device in	${{\mathit{V}}_{\mathbf{port}}}^{\prime }$	${\mathit{V}}_{\mathbf{eq}}$
	Leg	Motion	Adjacent Leg
1	left		upper on	+	$-{V_{\mathrm{port}}}^{\prime }$
2				−	$+{V_{\mathrm{port}}}^{\prime }$
3		$S_{\mathrm{U}}$ turns on,		0	0
4		$S_{\mathrm{L}}$ turns off	lower on	+	refer to #8
5				−	refer to #7
6				0	refer to #9
7			upper on	+	$-{V_{\mathrm{port}}}^{\prime }$
8				−	$+{V_{\mathrm{port}}}^{\prime }$
9		$S_{\mathrm{U}}$ turns off,		0	0
10		$S_{\mathrm{L}}$ turns on	lower on	+	refer to #2
11				−	refer to #1
12				0	refer to #3
13	right		upper on	+	$+{V_{\mathrm{port}}}^{\prime }$
14				−	$-{V_{\mathrm{port}}}^{\prime }$
15		$S_{\mathrm{U}}$ turns on,		0	0
16		$S_{\mathrm{L}}$ turns off	lower on	+	refer to #20
17				−	refer to #19
18				0	refer to #21
19			upper on	+	$+{V_{\mathrm{port}}}^{\prime }$
20				−	$-{V_{\mathrm{port}}}^{\prime }$
21		$S_{\mathrm{U}}$ turns off,		0	0
22		$S_{\mathrm{L}}$ turns on	lower on	+	refer to #14
23				−	refer to #13
24				0	refer to #15

, resulting in $V_{\mathrm{eq}}$ in the unified equivalent circuit. The # in the left column represents the number of conditions. All the cases are divided into left-leg switchings and right-leg switchings; the switching motion, status of the adjacent leg and ${V_{\mathrm{port}}}^{\prime }$ are three decisive factors. By using these three factors, $V_{\mathrm{eq}}$ in the unified equivalent circuit can be picked from the table. The connection of the equivalent circuit shown in Figure 3 corresponds to the conditions in which the upper switch in the adjacent leg of the considered bridge is kept on; therefore, $V_{\mathrm{eq}}$ in these conditions can be directly obtained by the decisive factors and is shown in Table 1.

On the other hand, the cases in which the lower device in the adjacent leg is kept on cannot directly be explained by the circuit shown in Figure 3; however, the switching process of all these can be explained by any one of the cases with the upper switch on in the adjacent leg owing to the symmetry of the circuit. The counterparts of these cases are described in Table 1. The counterpart case has the complete opposite conditions of the three decisive factors in the same switching leg of the considered case. It should be mentioned that the corresponding direction of the inductor current is also the opposite in this case. It can be said that the opposite switching motion with the opposite current direction achieves the same switching process with the considered case, but the roles of upper and lower devices are changed. Consequently, all the possible switching instances that can happen in DAB converters can be explained by the unified equivalent circuit shown in Figure 3, picking $V_{\mathrm{eq}}$ from Table 1 for the decisive factors.

For instance, at the $t_1$ instant of TPS in Figure 2c, the lower device $S_4$ turns on and the upper device $S_3$ turns off in the right leg. In the adjacent leg, the lower device $S_2$ is kept on. Meanwhile, the port voltage on the opposite side, ${V_{\mathrm{port}}}^{\prime }$, is negative. Thus, the switching at $t_1$ corresponds to case #23. As shown in the table, the counterpart case of #23 is #13, in which the upper device turns on in the right leg, the upper device in the adjacent leg is kept on and ${V_{\mathrm{port}}}^{\prime }$ is positive. Since the upper device in the adjacent leg is kept off in #23, the $t_1$ instant cannot be explained by the given circuit directly. However, the switching process of #23 can be completely explained by its counterpart case, #13. Thus, the switching transient that happens at $t_1$ can be explained by the unified equivalent circuit with conditions described for case #13, that is, $V_{\mathrm{eq}}=+{V_{\mathrm{port}}}^{\prime }=N{V}_2$.

It should be mentioned that the above discussion only involves the condition where one leg has switching motion. In SPS and EPS modulations, the conditions where two legs are manipulated simultaneously also existed; for instance, the switching at $t_1$ in SPS shown in Figure 2a and the switching at $t_2$ in EPS shown in Figure 2b. However, these conditions in EPS are usually not the critical switchings for ZVS. When these conditions become the critical switchings in SPS, other advanced modulations are usually used to take the place of SPS. Therefore, the conditions with one leg being manipulated are focused on in most of studies for ZVS in DAB converters and this paper does not pay much attention to the analysis of the conditions with two legs being manipulated.

3. Improved Charge-Based Method and Dead-Time Estimation

3.1. Concept of Minimal Switching Current

The most fundamental condition for realizing ZVS by the current-based method is the current direction at turn-on switching being negative (source to drain). Thus, the corresponding direction of the inductor current at the switching instant can be a sole judgement factor for ZVS. However, in practical converters, the parasitic capacitance and snubber capacitors connected to the devices in parallel need to be discharged by the end of the dead time to achieve ZVS. Therefore, the time for discharging and the dead time should be considered to judge the ZVS. This paper introduces a method considering both aspects. The improved charge-based method is extended to estimate the appropriate dead time.

With the knowledge introduced in the last section, all the switching instances under the condition of one leg being manipulated in DAB converters can be explained by the unified equivalent circuit in Figure 3. Furthermore, all of these switching instants can be classified into two cases in equivalent circuits where the upper device, $S_{\mathrm{U}}$, is turning on or the lower device, $S_{\mathrm{L}}$, is turning on. The circuits of these two cases are shown in Figure 4. The correct current direction to achieve ZVS based on the current-based method is assumed at the beginning of the dead time, and the current paths for the charging and discharging of the parasitic capacitance are drawn as dashed lines in the circuit diagrams with the direction.

The voltages across $S_{\mathrm{U}}$ and $S_{\mathrm{L}}$ are defined as $v_{\mathrm{dsU}}$ and $v_{\mathrm{dsL}}$, respectively. In the action shown in Figure 4a, for instance, $C_{\mathrm{pU}}$ is charged at the dc-side voltage; therefore, $v_{\mathrm{dsU}}=V_{\mathrm{DC}}$, and $v_{\mathrm{dsL}}=0$ at the beginning of the process. Then, $v_{\mathrm{dsL}}$ is increased by charging $C_{\mathrm{pL}}$ and $v_{\mathrm{dsU}}$ is decreased by discharging $C_{\mathrm{pU}}$ when the direction of the inductor current is the right direction. After a certain period, the charging and discharging are completed. To achieve a zero-voltage turning-on of $S_{\mathrm{U}}$, it should be turned on after $v_{\mathrm{dsU}}$ becomes zero. After $v_{\mathrm{dsU}}$ becomes zero, the remaining current flowing through the inductor conducts through the free-wheeling diode of $S_{\mathrm{U}}$ for a while. To achieve ZVS, $S_{\mathrm{U}}$ should be turned on during this period, where $v_{\mathrm{dsU}}$ is kept at zero. A similar derivation can be obtained for the case where $S_{\mathrm{L}}$ is turned on with the current direction shown in Figure 4b. To ensure the remaining current flows through the body diode after the charging and discharging, a certain amount of the initial current in the inductor is indispensable.

This paper involves a concept of minimal switching current, $I_{\mathrm{m}}$, that is the minimum required current flowing through the inductor at the beginning of the dead time to complete the charging and discharging. With this current at the beginning of the dead time, the inductor current becomes exactly zero when the charging and discharging process is completed. With this condition, the end of the dead time can only be set at the instant when the inductor current reaches zero. Both longer and shorter dead times than this result in losing ZVS.

3.2. Derivation of Minimal Switching Current

Here, the case shown in Figure 4a with $S_{\mathrm{U}}$ turning on is taken as a representative case in the following analysis. Considering the energy conservation in the equivalent circuit, the initial energy stored in the parasitic capacitance of the devices and the inductor should be equal to the sum of the final energy stored in them and the energy transferred to dc voltage sources. By assuming that the same type of devices are used for both the upper and lower arms, the electrostatic energy stored in $C_{\mathrm{pU}}$ at the beginning of the instant is totally equal to that in $C_{\mathrm{pL}}$ at the end; therefore, these parts can be canceled. If the initial inductor current is equal to the minimal switching current $I_{\mathrm{m}}$, the magnetic energy stored in the inductor becomes zero at the end of the transient; therefore, the initial magnetic energy in the inductor is equal to the energy transferred to the voltage sources as

$$\frac{1}{2}{L}_{\mathrm{eq}}{I_{\mathrm{m}}}^2=E_{\mathrm{dc}},$$

(1)

where $E_{\mathrm{dc}}$ is the energy transferred to two dc voltage sources during the charging and discharging process.

The equivalent circuit shown in Figure 4a represents the case of upper device, $S_{\mathrm{U}}$, turning on. $E_{\mathrm{dc}}$ in this condition, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}$, can be derived as

$$E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}={\int }_{t_a}^{t_b}\left(-V_{\mathrm{DC}}{i}_{\mathrm{CL}}\left(t\right)+V_{\mathrm{eq}}{i}_{\mathrm{L}}\left(t\right)\right)dt,$$

(2)

where $i_{\mathrm{CL}}$ and $i_{\mathrm{L}}$ are the currents flowing through the dc voltage sources $V_{\mathrm{DC}}$ and $V_{\mathrm{eq}}$, respectively. $t_{\mathrm{a}}$ and $t_{\mathrm{b}}$ are the time of the beginning and the end of the charging and discharging, respectively. In the equivalent circuits, the direction of $V_{\mathrm{eq}}$ represents the polarity when the equivalent port voltage on the other side bridge takes positive. $i_{\mathrm{L}}$ can be derived as

$$i_{\mathrm{L}}\left(t\right)=i_{\mathrm{CU}}\left(t\right)+i_{\mathrm{CL}}\left(t\right),$$

(3)

where $i_{\mathrm{CU}}$ is the discharging current of $C_{\mathrm{pU}}$ and $i_{\mathrm{CL}}$ is also the charging current of $C_{\mathrm{pL}}$. $i_{\mathrm{CL}}$ and $i_{\mathrm{CU}}$ can be expressed as

$$\left\{\begin{array}{cc}\hfill i_{\mathrm{CL}}& =C_{\mathrm{pL}}(v_{\mathrm{dsL}})\frac{d}{dt}{v}_{\mathrm{dsL}}=C_{\mathrm{p}}(v_{\mathrm{dsL}})\frac{d}{dt}{v}_{\mathrm{dsL}},\hfill \\ \hfill i_{\mathrm{CU}}& =-C_{\mathrm{pU}}(v_{\mathrm{dsU}})\frac{d}{dt}{v}_{\mathrm{dsU}}=C_{\mathrm{p}}(V_{\mathrm{DC}}-v_{\mathrm{dsL}})\frac{d}{dt}{v}_{\mathrm{dsL}},\hfill \end{array}\right.$$

(4)

where $C_{\mathrm{p}}$ is a universal expression for parasitic capacitance; therefore, $S_{\mathrm{U}}$ and $S_{\mathrm{L}}$ can be represented by the same function of $C_{\mathrm{p}}$. $C_{\mathrm{p}}$ is usually a function of its drain–source voltage. As a result, the inductor current can be expressed as

$$i_{\mathrm{L}}=\left[C_{\mathrm{p}}\left(v_{\mathrm{dsL}}\right)+C_{\mathrm{p}}(V_{\mathrm{DC}}-v_{\mathrm{dsL}})\right]\frac{d}{dt}{v}_{\mathrm{dsL}}.$$

(5)

The total transferred charge by $i_{\mathrm{CL}}$ and $i_{\mathrm{L}}$ are defined as $\Delta Q_{\mathrm{CL}}$ and $\Delta Q_{\mathrm{L}}$, respectively, and can be calculated as

$$\left\{\begin{array}{cc}\hfill \Delta Q_{\mathrm{CL}}& ={\int }_{t_{\mathrm{a}}}^{t_{\mathrm{b}}}{i}_{\mathrm{CL}}\left(\mathit{t}\right)dt={\int }_0^{V_{\mathrm{DC}}}{C}_{\mathrm{p}}\left(\mathit{v}\right)dv,\hfill \\ \hfill \Delta Q_{\mathrm{L}}& ={\int }_{t_{\mathrm{a}}}^{t_{\mathrm{b}}}{i}_{\mathrm{L}}\left(\mathit{t}\right)dt={\int }_0^{V_{\mathrm{DC}}}\left[C_{\mathrm{p}}\left(\mathit{v}\right)+C_{\mathrm{p}}({\mathit{V}}_{\mathrm{DC}}-\mathit{v})\right]dv.\hfill \end{array}\right.$$

(6)

In general, the transferred charge through a device with the voltage charging from 0 to V can be expressed as

$$Q(V)={\int }_0^V{C}_{\mathrm{p}}\left(\mathit{v}\right)dv,$$

(7)

and its value can usually be obtained from device data-sheets. By using (7), $\Delta Q_{\mathrm{CL}}$ and $\Delta Q_{\mathrm{L}}$ in (6) can be expressed as

$$\left\{\begin{array}{cc}\hfill \Delta Q_{\mathrm{CL}}& ={\int }_0^{V_{\mathrm{DC}}}{C}_{\mathrm{p}}\left(\mathit{v}\right)dv=Q(V_{\mathrm{DC}}),\hfill \\ \hfill \Delta Q_{\mathrm{L}}& ={\int }_0^{V_{\mathrm{DC}}}2C_{\mathrm{p}}\left(\mathit{v}\right)dv=2Q(V_{\mathrm{DC}}),\hfill \end{array}\right.$$

(8)

By using (6) and (8), (2) can be rewritten as

$$E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}={\int }_0^{V_{\mathrm{DC}}}\left[-V_{\mathrm{DC}}{C}_{\mathrm{p}}\left(\mathit{v}\right)+2V_{\mathrm{eq}}{C}_{\mathrm{p}}\left(\mathit{v}\right)\right]dv=(-V_{\mathrm{DC}}+2V_{\mathrm{eq}})Q(V_{\mathrm{DC}}).$$

(9)

$I_{\mathrm{m}}$ for the case of the upper device turning on, ${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}$, can be derived as

$${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}=\sqrt{\frac{2E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}}{L_{\mathrm{eq}}}}=\sqrt{\frac{2(2V_{\mathrm{eq}}-V_{\mathrm{DC}})Q\left(V_{\mathrm{DC}}\right)}{L_{\mathrm{eq}}}}.$$

(10)

When the practical voltage ratio of $0.5<k<2$ and $V_{\mathrm{eq}}=+{V_{\mathrm{port}}}^{\prime }$, which gives $2V_{\mathrm{eq}}-V_{\mathrm{DC}}>0$, is assumed, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}>0$ is achieved. For example, case #13 in Table 1 can be a representative of this condition. On the contrary, when $V_{\mathrm{eq}}=-{V_{\mathrm{port}}}^{\prime }$, as is the case of #14, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}<0$ is achieved. It is obvious that, when $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}<0$, a valid ${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{U}}\_\mathrm{on})}$ is not available.

The same derivation can be performed in the equivalent circuit shown in Figure 4b with $S_{\mathrm{L}}$ turning on. The energy transferred to the voltage sources of the equivalent circuit for the case of the lower device turning on, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}$, and the minimal switching current in this condition, ${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}$, can be derived as

$$E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}={\int }_0^{V_{\mathrm{DC}}}\left[V_{\mathrm{DC}}{C}_{\mathrm{p}}\left(\mathit{v}\right)-2V_{\mathrm{eq}}{C}_{\mathrm{p}}\left(\mathit{v}\right)\right]dv=(V_{\mathrm{DC}}-2V_{\mathrm{eq}})Q(V_{\mathrm{DC}}),$$

(11)

and

$${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}=\sqrt{\frac{2E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}}{L_{\mathrm{eq}}}}=\sqrt{\frac{2(V_{\mathrm{DC}}-2V_{\mathrm{eq}})Q\left(V_{\mathrm{DC}}\right)}{L_{\mathrm{eq}}}}.$$

(12)

When the practical voltage ratio of $0.5<k<2$ and $V_{\mathrm{eq}}=+{V_{\mathrm{port}}}^{\prime }$, as is the case of #1, for instance, which gives $V_{\mathrm{DC}}-2V_{\mathrm{eq}}<0$, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}<0$ is achieved. On the contrary, when $V_{\mathrm{eq}}=-{V_{\mathrm{port}}}^{\prime }$, as is the case of #20, $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}>0$ is achieved. Additionally, when $E_{\mathrm{dc}({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}<0$, a valid ${I_{\mathrm{m}}}_{({\mathit{S}}_{\mathrm{L}}\_\mathrm{on})}$ is not available.

In conclusion, all of the possible switching instances with one-leg manipulation can be classified into two categories: $E_{\mathrm{dc}}>0$ and $E_{\mathrm{dc}}<0$. The schematic and example waveforms of the drain–source voltages and the inductor current with a long enough dead time for these two categories are shown in Figure 5. $E_{\mathrm{dc}}>0$ means that the dc voltage sources receive energy from the inductor; therefore, the current at the end of the charging and discharging process becomes closer to zero than that at the beginning, as shown in Figure 5a. This clearly indicates that a certain positive value of $I_{\mathrm{m}}$ is needed to complete the charging and discharging with this current, where the positive value for $I_{\mathrm{m}}$ means the correct direction for ZVS based on the current-based method. On the other hand, $E_{\mathrm{dc}}<0$ means that the dc voltage sources give out energy to the inductor; therefore, the current at the end of the charging and discharging process becomes farther from zero than that of the beginning as shown in Figure 5b. Hence, even zero initial current can realize ZVS and any correction for ZVS in practical condition is not needed. That is the reason why $I_{\mathrm{m}}$ does not have an available solution in the case of $E_{\mathrm{dc}}<0$.

3.3. Lowest Switching Current Control

Once $I_{\mathrm{m}}$ at a specific switching instant is deduced, a strategy called lowest switching current control, which is proposed in [23], can be used to control the current at this instant to be equal to a given reference, which is defined as ${I_{\mathrm{m}}}^{*}$. This is a modification of the conventional modulations that manipulates the current at some switching instances slightly based on the model of the circuit with known parameters. This method is only available for the modulations which have two or more degrees of control freedom, such as EPS and TPS, since the switching current must be modified without changing the transferred power. At the very least, ${I_{\mathrm{m}}}^{*}>I_{\mathrm{m}}$ is needed. In addition, it should be mentioned that an appropriate margin should be included into ${I_{\mathrm{m}}}^{*}$ to ensure ZVS for both the possible control error of the lowest switching current and the variations in circuit parameters and operating conditions.

3.4. Range of Dead-Time Duration for ZVS

All the above analyses focus on the initial current value at the beginning of the dead time, $t_{\mathrm{a}}$. It is also important to discuss the end instant of the dead time. Here, we also took the two categories of $E_{\mathrm{dc}}>0$ and $E_{\mathrm{dc}}<0$ as different cases to analyze. It can be seen from the schematic waveforms shown in Figure 5 that the current conducts the free-wheeling diode of $S_{\mathrm{U}}$ (or $S_{\mathrm{L}}$) after the charging and discharging process is completed at $t_{\mathrm{b}}$. The switch voltages are clamped until $i_{\mathrm{L}}$ reaches zero at $t_{\mathrm{c}}$. Consequently, the dead time should be ended between $t_{\mathrm{b}}$ and $t_{\mathrm{c}}$, and the dead-time duration, $t_{\mathrm{d}}$, should be longer than $t_{\mathrm{b}}-t_{\mathrm{a}}$ and shorter than $t_{\mathrm{c}}-t_{\mathrm{a}}$.

The allowable range of the dead time for ZVS depends on the initial current. This paper assumes that the initial current is successfully controlled to be equal to ${I_{\mathrm{m}}}^{*}$. The range of the dead time can be a function of ${I_{\mathrm{m}}}^{*}$. It is difficult to solve the charge and discharge duration algebraically; however, it is enough to analyze it by a numerical approach for the purpose of suggesting the appropriate dead time, since it only depends on the almost fixed circuit parameters, including dc source voltages and the characteristics of the parasitic capacitance.

Figure 6 shows the schematic view of the range of the dead-time duration, $t_{\mathrm{d}}$, for ZVS as function of ${I_{\mathrm{m}}}^{*}$. There is a lower limit, which corresponds to $t_{\mathrm{b}}-t_{\mathrm{a}}$, and an upper limit, which corresponds to $t_{\mathrm{c}}-t_{\mathrm{a}}$. As discussed in Section 3.2, there is a certain positive value of minimal switching current, $I_{\mathrm{m}}$, under the condition of $E_{\mathrm{dc}}>0$. With this minimal switching current condition, the charging and discharging process is ended when the current reaches zero; therefore, the lower and upper limits become equal, as shown in Figure 6a. Consequently, there is no ZVS area below this initial current under $E_{\mathrm{dc}}>0$. On the other hand, there is no limitation related to the initial switching current under $E_{\mathrm{dc}}<0$, as shown in Figure 6b; therefore, the ZVS range still exists around zero initial current and even in the negative initial current range in principle. With the negative initial current, an extra time period before $t_{\mathrm{a}}$, in which the charging and discharging of the parasitic capacitance are not started, is included in the dead time. Therefore, both the lower and upper limits of the dead time linearly increased for as long as the increase in $|{I_{\mathrm{m}}}^{*}|$, as shown in Figure 6.

The results shown in Figure 6 suggest that a wider range of dead-time durations to achieve ZVS can be available by setting a high value for ${I_{\mathrm{m}}}^{*}$. Therefore, a large margin of ${I_{\mathrm{m}}}^{*}$ is good for ZVS realization in both aspects—enough of an initial switching current and appropriate dead-time value.

Furthermore, it can be found that the allowable range of $t_{\mathrm{d}}$ for ZVS under the condition of $E_{\mathrm{dc}}>0$ is narrower than that under $E_{\mathrm{dc}}<0$ in general. This is due to the fact that $|i_{\mathrm{L}}|$ decreases under $E_{\mathrm{dc}}>0$, while it increases under $E_{\mathrm{dc}}<0$, as can be seen from Figure 5. The narrower range of $t_{\mathrm{d}}$ makes it more difficult for the switching under $E_{\mathrm{dc}}>0$ to achieve ZVS than that under $E_{\mathrm{dc}}<0$.

4. Experimental Verification of ZVS Realization

4.1. Experimental Setup

To verify that the evaluation of ZVS by improved charge-based method and dead-time estimation is effective, a laboratory prototype of the DAB converter with the power rating of 4 kW was fabricated as shown in Figure 7.

Table 2. Specifications of 4 kW Prototype of DAB Converter.

Rated power	P	4 kW
Switching frequency	$f_{\mathrm{sw}}$	20 kHz
Input voltage	$V_1$	270 V ($k=0.67$)
		400 V ($k=1.5$)
Output voltage	$V_2$	400 V ($k=0.67$)
		270 V ($k=1.5$)
Leakage inductance	L	61 $\mathsf{\mu }$H
Transformer winding ratio	$1:n$	$1:1$
Type of devices		C3M0025065D

shows the specifications of the fabricated DAB converter.

The DAB converter can be operated, for instance, in EPS modulation. It should be mentioned that, in other modulations, operations with one-leg manipulations will achieve the same results. The switching instant at $t_4$ of EPS, as shown in Figure 2b, is the critical switching. The critical switchings in the condition of $k<0$ and $k>0$ exactly correspond to cases #13 and #8 in Table 1. Two different settings of the voltage ratio, $k=0.67$ and $k=1.5$ with the power flow from the primary to secondary side, which represent the condition $E_{\mathrm{dc}}>0$ and $E_{\mathrm{dc}}<0$, respectively, are taken as examples.

4.2. Estimation of Minimal Switching Current and Dead-Time Range for ZVS

To verify the feasibility of the proposed method for ZVS realization in the practical condition, the lowest switching current control was tested in the fabricated converter. Prior to the experiments, the minimal switching current, $I_{\mathrm{m}}$, and the dead-time range for ZVS with the parameters of the fabricated converter were estimated in both settings. As discussed in Section 3.2, the constraint of the minimum switching current exists in the condition of $E_{\mathrm{dc}}>0$, with $V_{\mathrm{DC}}=400$ V, and Q($V_{\mathrm{DC}}$) can be calculated as 137 nC by using (7) and the C–V characteristics of the device. Thus, the theoretical minimal switching current, $I_{\mathrm{m}}$, for $k=0.67$ is calculated as 0.8 A by using (10). Due to the dc voltage giving out energy to the inductor in the condition of $E_{\mathrm{dc}}<0$ with $V_{\mathrm{DC}}=400$ V, $I_{\mathrm{m}}=0$ A is assumed in this paper without any correction for ZVS in the practical condition.

The lower and upper limits of the dead-time duration, $t_{\mathrm{d}}$, as a function of the initial switching current were also estimated. The estimation was performed numerically since the algebraic derivation of the duration is complicated. The numerical analysis was in the time domain and based on the given initial circuit parameters at the beginning of the dead time. It also considered the voltage-dependent parasitic capacitance, which is represented by the C–V characteristics of the device.

The estimation results of the dead-time range for both $k=0.67$ and $k=1.5$ are shown in Figure 8 as solid lines. Figure 8a also confirmed that the upper and lower limits meet at $I_{\mathrm{m}}$ = 0.8 A.

4.3. Verification of ZVS Realization with Lowest Switching Current Control

4.3.1. Operations without Lowest Switching Current Control

To verify that the ZVS cannot be achieved without considering the parasitic capacitance and dead-time period, some operations with the initial switching current controlled to be zero were tested. These operating points are indicated in Figure 8 as A, B, and C. To observe the critical switching transients, the reference power was set at 2000 W for all the operations of A, B, and C.

The experimentally measured zoomed waveforms during the dead time of the critical switching transients are shown in Figure 9. These include the drain–source voltage of the device to be turned on, $v_{\mathrm{dsU}}$ in Figure 9a, $v_{\mathrm{dsL}}$ in Figure 9b,c, the transformer current, $i_{\mathrm{L}}$, and the gate signals for $S_{\mathrm{U}}$ and $S_{\mathrm{L}}$ instead of the gate–source voltages. It can be seen that the converter did not achieve zero voltage turn-on at those switching transients. In operation A, in which the initial switching current is equal to zero under $E_{\mathrm{dc}}>0$, the discharging of $v_{\mathrm{dsU}}$ was not completed by the time that $i_{\mathrm{L}}$ becomes zero; therefore, there was no chance of achieving ZVS, even by controlling $t_{\mathrm{d}}$. In operation B, in which $t_{\mathrm{d}}$ is lower than the lower limit under $E_{\mathrm{dc}}<0$, the discharging was slowly continuing with increasing $i_{\mathrm{L}}$; however, there was not enough dead time to complete the discharging. In operation C, in which $t_{\mathrm{d}}$ was higher than the upper limit, the dead time was too long so that the recharging of $v_{\mathrm{dsL}}$ was observed.

4.3.2. Verification of Dead-Time Range for ZVS

To verify the theoretical calculation of the limits, the boundary operations of the ZVS were searched experimentally. Specifically, the lower and upper limits of $t_{\mathrm{d}}$ were identified by observing the waveforms when changing the initial switching current. During the experiments, the reference powers were set at 2000 W for both $k=0.67$ and $k=1.5$. The experimentally observed lower and upper limits of $t_{\mathrm{d}}$ for $k=0.67$ and $k=1.5$ are shown in Figure 8 as marks. The trend of experimental results agreed with the calculated boundaries. Both the calculated and experimental results verify that the dead-time range in $E_{\mathrm{dc}}>0$ is narrower than that under $E_{\mathrm{dc}}<0$. It is much easier to achieve ZVS with a wide dead-time range under the condition of $E_{\mathrm{dc}}>0$.

The operating point with the experimental minimal switching current in $E_{\mathrm{dc}}>0$ was found at the point of $I_{\mathrm{m}}=1.2$ A and $t_{\mathrm{d}}=500$ ns, and is marked as D in Figure 8a. The zoomed waveforms during the dead time of one critical switching transient with this operation are shown in Figure 10. It can be observed from the waveforms that the discharging of $v_{\mathrm{dsU}}$ was completed just at the moment when $i_{\mathrm{L}}$ reached 0 A.

4.3.3. Operations with Lowest Switching Current Control and Designed Dead Time

To verify that the ZVS can always be achieved in the operations with a designed initial switching current and the dead time discussed in Section 4.2, two operating points under the lowest switching current control were tested. ${I_{\mathrm{m}}}^{*}$ were set as 2.5 A for both $k=0.67$ and $k=1.5$ considering margins for possible errors. On the other hand, a constant dead time, $t_{\mathrm{d}}=600$ ns, was set for this setup to ensure that the switching condition is far enough from both limits for any initial switching current. Corresponding settings of ${I_{\mathrm{m}}}^{*}$ and $t_{\mathrm{d}}$ are marked as E and F in Figure 8.

The zoomed waveforms of the critical switching transients of the operations with the power reference of 2000 W for both $k=0.67$ and $k=1.5$ are shown in Figure 11. It can be clearly seen that the drain–source voltage of the device to be turned on discharged completely and the polarity of $i_{\mathrm{L}}$ did not change during the dead-time in both operations. Thus, it is confirmed that ZVS was successfully realized with enough of a margin for this setting.

5. Conclusions

This paper proposes a unified equivalent circuit to consider all the possible switching instants under the condition of a one-leg manipulation in DAB converters. By using the unified equivalent circuit, an improved charge-based method with dead-time estimation is studied to identify the ZVS realization considering the effect of both the voltage-dependent parasitic capacitance and dead-time period. All equivalent circuits can be divided into two cases, the upper or lower device turning on, and the corresponding equations of the specific initial current, which is defined as the minimal switching current, are deduced. With the different parameters of the circuit, all of the switching instants can be further classified into two categories according to the sign of the energy transferred to dc voltage sources. Based on the classification, the function of the acceptable dead-time range with a switching current is analyzed and different difficulties for realizing ZVS operations are found in these two categories. A laboratory 4 kW DAB prototype was fabricated to verify that the estimation of ZVS realization by an improved charge-based method is effective. The lowest switching current control when considering enough of a margin of the switching current and dead time can successfully achieve ZVS at critical switching instants. It is much easier to realize ZVS operation with a wider dead-time range by using the category of $E_{\mathrm{dc}}<0$. Thus, during the designing and operating of DAB converters, besides the margin of the switching current and dead time being considered, operations that satisfied $E_{\mathrm{dc}}<0$ are welcomed for easier ZVS realization.