Analytical Estimation of Power Losses in a Dual Active Bridge Converter Controlled with a Single-Phase Shift Switching Scheme

Abstract

Micro-grid solutions around the world rely on the operation of DC/DC power conversion systems. The most commonly used solution for these topologies is the use of a dual active bridge (DAB) converter. Increasing the efficiency and reliability of this system contributes to the improvement in the stability of the entire microgrid. This paper discussed an analytical method of energy efficiency and power loss estimation in a single phase dual active bridge (DAB) converter controlled with a single-phase shift (SPS) modulation scheme for microgrid system stability. The presented approach uses conduction and commutation losses of semiconductors and high frequency transformer. All parameters required for the calculation may be obtained from the manufacturers’ datasheets or can be based on a simple measurement. The approach was validated by the comparison of the estimated energy efficiency characteristics with the measured ones for a prototype of a 5 kW single phase DAB converter equipped with silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFET).

1. Introduction

Dual active bridge (DAB) topology is among the most popular DC/DC converters used in electronic power systems. This topology is widely used in DC/DC microgrids as well as mixed networks and owes its popularity to many advanced features such as bidirectional power flow, galvanic isolation, control simplicity, wide range of voltage regulation, and soft switching of semiconductor devices. DAB topology has been applied to solid-state transformers, electromobility, energy storage systems, and DC voltage distribution networks [1,2]. Nowadays, the development of DAB converters is mainly focused on the increase in energy efficiency by using modern power semiconductors (SiC, GaN), where the adaptation of new control strategies enables a reduction in the current stress and the limitation of current RMS values, and a diminishing of DAB transformer power losses [1,2,3,4,5,6]. Crucially, the application of modern power semiconductor devices enables an increase in the switching frequency up to 1 MHz [7], which results in a higher power density, a reduction in passive components dimensions, and a reduction in the overall converter dimensions.

The problem of energy efficiency evaluation is one of the main aspects of the beginning stage of the design process of a future converter. Importantly, a proper evaluation of power losses allows for a selection of cooling methods and radiator features, which reduce the overall converter dimensions and the total cost. At the early stages of the design process, energy efficiency may be estimated using a simulation tool or via an analytical analysis. Many simulators (e.g., PLECS) offer comprehensive tools for the evaluation of power losses and a thermal analysis using electro-thermal models [8]. This method is easy to use and delivers results with a satisfactory accuracy for the design purpose. However, it requires access to precise models of semiconductors, which not all suppliers offer, because such models are usually shared by manufacturers only for selected types of semiconductors, or the developed models are dedicated to one specific simulator. Crucially, many models of semiconductors presented in the literature cannot be parameterized using the manufacturer’s datasheet, hence additional laboratory measurements are required to obtain the model parameters, which is usually time-consuming and increases the total cost [9,10].

Notably, the measurement of some quantities in the DAB converter (e.g., the power loss of a transformer) may be problematic, hence using analytical methods may be a suitable approach to obtaining a power loss distribution.

Another approach uses an analytical analysis based on a set-up of mathematical equations describing the function of the considered converter. It is worth mentioning that the presence of high-frequency currents in a DAB converter AC circuit, or the determination of the switching process mechanism of semiconductors (under soft or hard conditions) in dependence on the converter AC side currents values results in limited usefulness of the analytical methods, which have been derived for classic H-bridge topologies. These approaches are usually described for sinusoidal modulation with a low fundamental current frequency at the inverter AC side [11,12,13]. Moreover, in some systems, the transistor turn-on losses are neglected [14], or it is assumed that both the turn-on and turn-off processes perform only under hard switching conditions [12]. In available application notes, switching losses under hard conditions are usually calculated using simplified formulas with constant values of time parameters describing the switching processes [4]. Moreover, to simplify the considerations, the impact of transistor gate resistance is often omitted [12,14,15].

In the literature, analytical methods of power loss estimation dedicated to DAB converters have also been proposed.

For example, in [16], an analysis of a power transfer in a single-phase DAB converter was provided. The presented analyses were performed for different cases of input-to-output voltage relations including the influence of the dead time and conduction losses of semiconductor devices. However, the presented analysis was incomplete as it omitted the discussion of the impact of semiconductor switching losses and transformer losses. An interesting approach was presented in [17], where a theoretical analysis of power losses was given, which was used for the optimal design methodology of a single-phase DAB converter. A valuable part of this work is a presentation of an estimation method of capacitors and transformer losses. The obtained results were compared with the results of the simulation and experimental measurements to prove the correctness of the adopted methodology, however, an analysis of the semiconductor switching losses was not included—the authors assumed that all switches were switched under soft conditions. Another solution was presented in [18], where an analysis of the conducted differential mode current harmonic magnitudes and the power factor in a DAB converter was discussed. Importantly, that solution was based on a Fourier series theory, hence its adaptation is more complex and time consuming. This approach may be used for the overall prediction of the DAB operational performance and to optimize and identify the current and voltage ranges. Commutation losses were not considered here either; hence based on the methodology presented in [18], the DAB converter efficiency may only be evaluated in a generic way.

The approach presented in [19] was dedicated to the estimation of semiconductor losses including the impact of dead-time and turn-off process for SiC MOSFET and Si IGBT transistors operating in DAB converters. All of the required parameters may be easily extracted using the manufacturer’s datasheet. The used mathematical expressions are not complicated, and method adaptation is not time-consuming. It should be noted that the presented considerations did not take into account the transformer losses, which is a significant disadvantage of the method.

A more advanced approach was described in [20], where the estimation method of semiconductors and transformer losses was proposed. The obtained results were used to improve the overall energy efficiency by modifying and optimizing the DAB converter control strategy. The limitations of the primary approach are the omission of the diodes’ reverse recovery process and neglect of the impact of transistor gate resistance on the switching process dynamics.

A comprehensive estimation method of the DAB converter efficiency was proposed in [21]. The transformer losses were predicted using the Steinmetz equation and the semiconductors’ conduction and switching losses were also calculated. Additional analyses were performed for hard and soft switching conditions in dependency on the current values in the AC circuit of the DAB converter. The high accuracy of the obtained results and the usefulness of the proposed approach were confirmed by a comparison with the experimental measurement results. However, two different polynomial functions—one for hard switching and one for soft switching—must be used to calculate the semiconductor switching losses. Parameters of these functions were fitted by using least means squares approximation. As a result, the method is complicated and time-consuming.

Based on the presented analysis, it appears that a different approach is necessary. In this paper, a calculation method of power loss and energy efficiency of a one-phase DAB converter composed with SiC-MOSFETs and controlled with single phase shift was proposed. The proposed set of equations, whose coefficients may be easily obtained from the manufacturer’s datasheets, describes the commutation and conduction losses of diodes and transistors and the transformer losses were also considered. The correctness of theoretical considerations was verified by comparing the analytical results with the experimental ones, performed on a 5 kW DAB converter prototype.

2. Dual Active Bridge DC/DC Converter

The basic topology of the dual active bridge (DAB) DC/DC converter with a one-phase high frequency transformer is presented in Figure 1a. It consists of two H-bridges coupled by an AC-link formed by a transformer with a turn’s ratio n = N₂/N₁ and an additional inductor L_d. The DAB converter may be driven using various control methods. Due to its simplicity of implementation, small inertia, and satisfactory dynamic performance, the single phase shift (SPS) switching scheme, where all transistors are switched with a 50% duty cycle ratio and the phase-shift ϕ is used to control the power flow (Figure 1b), was the most common scheme. Nevertheless, using SPS control causes a reduction in the operating range in which semiconductors are switched to soft conditions, especially when the input-to-output voltage ratio is significantly different from 1. Another disadvantage of the application of the SPS modulation scheme is an increase in the rms value of the transformer current at the converter’s low output power. As a result, a significant reactive power flow is then observed, which increases the conduction loss and the current stress of transistors and diodes [22,23]. To improve the converter efficiency by reducing the circulating power flow and limiting the current rms value, other control methods, which provide an extra degree of freedom, have been proposed such as extended phase shift (EPS), dual phase shift (DPS), or triple phase shift (TPS) modulation [24,25].

Despite the undeniable advantages of EPS, DPS, and TPS, in comparison with SPS, a practical application of these types of modulation is more complex. These methods significantly complicate the implementations of the modulator, and their efficiency characteristics in relation to the output power, with the change in the voltage ratio, decreases significantly. Hence, in this paper, the authors considered a DAB controlled with a SPS control scheme, however, the proposed approach may be adopted to other modulation types.

3. Currents Estimation in a DAB Converter

An equivalent circuit of the single-phase DAB converter (Figure 1a) is presented in Figure 2. A resultant inductance L represents a sum of inductances in the AC-circuit:

$$L=L_d+L_{\delta 1}+L_{\delta 2}^{\prime },$$

(1)

where:

-

L_d—inductance of the additional inductor;

-

L_δ1, L_δ2′—leakage inductance of each transformer winding converted to the bridge H₁ side: L_δ2′ = L_δ2/n²;

-

L_δ2—leakage inductance of transformer winding at the H₂ bridge side;

n = N₂/N₁—transformer turns ratio.

In the presented equivalent scheme, values of the H₂ bridge voltages and currents are also referred to the H₁ bridge side.

In this study, the DAB converter features were considered when the SPS modulation strategy was applied. Each bridge generated a quasi-square wave voltage u₁ and u₂/n with a 50% duty cycle (Figure 3).

The value and power flow direction between bridges H₁ and H₂ are controlled by the phase shift ϕ. To simplify the calculations, the impact of the transistors’ dead time may be neglected. Similarly, it can be assumed that the values of voltages U_DC1 and U_DC2/n are high enough, which enables the voltage drop to be omitted at the transistors and diodes. In brief, positive values of the phase shift are used when U_DC1 > U_DC2/n, however, for a negative value of ϕ, the results may be obtained using a similar approach. In Figure 4, exemplary theoretical waveforms are presented, when U_DC1 < U_DC2/n and ϕ > 0.

Based on Figure 3a and an equivalent scheme of the DAB converter (Figure 2), voltage u_L, affecting the inductances in the AC-link, is described by:

-

for the time interval t_A:

$$u_{L\left(A\right)}=u_1-\frac{u_2}{n}=U_{DC1}+\frac{U_{DC2}}{n},$$

(2)

-

for the time interval t_B:

$$u_{L\left(B\right)}=u_1-\frac{u_2}{n}=U_{DC1}-\frac{U_{DC2}}{n}.$$

(3)

Hence, the current i_L in specified time moments is described by:

$$i_L\left(t_1\right)=I_1,$$

(4)

$$i_L\left(t_2\right)=I_2=I_1+\frac{u_{L\left(A\right)}}{L}{t}_A$$

(5)

and

$$i_L\left(t_4\right)=i_L\left(\frac{T_S}{2}\right)=I_3=I_2+\frac{u_{L\left(B\right)}}{L}{t}_B=-I_1.$$

(6)

Thus, the average values of the input and output currents I_DC1 and I_DC2 are given by:

$$I_{DC1\left(av\right)}=\frac{2}{T_S}{{\displaystyle \int }}_0^{T_S/2}{i}_{DC1}\left(t\right)dt=\frac{1}{T_S}\left[I_2\left(t_A+t_B\right)+I_3\left(t_B-t_A\right)\right],$$

(7)

and

$$I_{DC2\left(av\right)}=\frac{2}{T_S}{{\displaystyle \int }}_0^{T_S/2}{i}_{DC2}\left(t\right)dt=\frac{1}{n{T}_S}\left[I_2\left(t_B-t_A\right)+I_3\left(t_A+t_B\right)\right].$$

(8)

Because t_A = T_S/2 − t_B and substitutions (2) and (3) to (8), (9) leads to:

$$I_{DC1\left(av\right)}=\frac{1}{n{T}_S}\left[-\frac{2U_{DC2}}{L}{t}_B{}^2+\frac{T_S·U_{DC2}}{L}{t}_B\right],$$

(9)

and

$$I_{DC2\left(av\right)}=\frac{1}{n{T}_S}\left[-\frac{2U_{DC1}}{L}{t}_B{}^2+\frac{T_S·U_{DC1}}{L}{t}_B\right].$$

(10)

For known values of I_DC1(av) or I_DC2(av), n and U_DC1 or U_DC2, the length of the time interval t_B may be easily extracted by solving Equations (9) or (10). Next, the length of interval t_A may be obtained for a specified switching time T_S, which allows for a calculation of the values of current i_L at characteristic moments of the DAB converter operating cycle.

4. Estimation of Transistor and Diode Power Losses

The total power loss P_T of a single transistor operating in a H-bridge is the sum of commutation losses and conduction loss P_C(T):

$$P_T=P_{ON\left(T\right)}+P_{C\left(T\right)}+P_{OFF\left(T\right)},$$

(11)

where P_ON(T) and P_OFF(T) are the turn-on and turn-off switching losses, also called the commutation losses. The total power loss of a single diode P_D may be defined in an analogous way.

Conduction losses result from voltage drops on conducting transistors and diodes. If MOSFET transistors are applied in a converter construction, using a linear approximation of the transistor output characteristic i_D(u_DS) (Figure 5) allows one to estimate a voltage drop u_DS depending on a drain current i_D:

$$u_{DS}=\frac{U_{DS\left(N\right)}}{I_{D\left(N\right)}}{i}_D,$$

(12)

where U_DS(N) and I_D(N) are the rated values of the transistor drain-to-source voltage u_DS and drain current i_D (given in the manufacturer’s datasheet).

Similarly, using a linear approximation of the datasheet diode characteristic i_DZ(u_D), the voltage drop u_D caused by a flow of current i_DZ may be calculated as:

$$u_D=r_D\cdot i_{DZ}+U_{FO},$$

(13)

where U_FO is a diode threshold voltage and r_D is the diode dynamic resistance r_D = Δu_D/Δi_DZ (Figure 5).

Hence, the conduction power loss of the MOSFET transistor and diode calculated for one switching period T_S are given as follows:

-

for MOSFET:

$$P_{C\left(T\right)}=\frac{U_{DS\left(N\right)}}{I_{D\left(N\right) }{T}_{S }}{{\displaystyle \int }}_{t_0}^{t_O+T_S}{\left[i_D\left(t\right)\right]}^{2}dt=\frac{U_{DS\left(N\right)}}{I_{D\left(N\right)}}\cdot I_{D\left(rms\right)}{}^2$$

(14)

-

and for the diode:

$$P_{C\left(D\right)}=U_{FO}\cdot I_{DZ\left(av\right)}+r_D\cdot I_{DZ\left(rms\right)}{}^2,$$

(15)

where I_D(rms) and I_DZ(rms) are rms values of transistor and diode currents and I_DZ(av) is an average value of a diode current i_DZ calculated for one switching period T_S.

Commutation losses result from finite values of the rise and fall times of the transistor voltage and current waveforms during switching processes. Considering the theoretical voltages and current waveforms obtained in a basic switching cell (Figure 6) during the transistor turn-on process under hard conditions, the transistor current i_D reaches the value of the load current I_O before the reduction in the drain-to-source voltage u_DS [26] (Figure 7).

Hence, in the turn-on process of a transistor, two characteristic sub periods may be described. Impacted by the diode D_Z reverse recovery, during the first stage of the turn-on process, the drain current rises to the value, which is a sum of the absolute values of load current I_O and reverse recovery current I_RM of diode D_Z (Figure 7b). Considering the waveforms presented in Figure 6, the transistor current i_D derivative with time is expressed by:

$$a_{iD}=\frac{d{i}_D}{dt}=\frac{I_O+\left|I_{RM}\right|}{t_{RI}\prime }=\frac{I_O}{t_{RI}}.$$

(16)

To estimate the current i_D rise time t_RI, a MOSFET gate circuit should be analyzed (Figure 8). During the transistor switching process, which is caused by drive voltage U_DR changes, transistor parasitic capacitances C_GD and C_GS are recharged by the gate current i_G [27]:

$$i_G=C_{GD}\frac{d{u}_{GD}}{dt}+C_{GS}\frac{d{u}_{GS}}{dt}.$$

(17)

The gate current i_G may also be described by the equation:

$$i_G=\frac{U_{DR}-u_{GS}}{R_G},$$

(18)

where R_G is an external gate resistance. In the manufacturer’s datasheet, the values of capacitances C_GD and C_GS are given as an input capacitance C_iss and a reverse transfer capacitance C_rss with the following relationships:

$$C_{iss}=C_{GD}+C_{GS}$$

(19)

and

$$C_{rss}=C_{GD}.$$

(20)

Next, substituting (18)–(20) to Equation (17):

$$\frac{U_{DR}-u_{GS}}{R_G}=C_{rss}\frac{d(u_{GS}-u_{DS})}{dt}+(C_{iss}-C_{rss})\frac{d{u}_{GS}}{dt},$$

(21)

which leads to:

$$\frac{U_{DR}-u_{GS}}{R_G}=C_{iss}\frac{d{u}_{GS}}{dt}-C_{rss} \frac{d{u}_{DS}}{dt}.$$

(22)

During the current i_D rise phase of the turn-on process, to simplify the calculations, it can be assumed that the voltage u_DS remains constant and its derivative with time equals zero (Figure 7). Hence, Equation (22) may be modified as follows:

$$\frac{U_{DR}-u_{GS}}{R_G}=C_{iss}\frac{d{u}_{GS}}{dt}.$$

(23)

Next, transforming Equation (23):

$$dt=\frac{R_G\cdot C_{iss}}{U_{DR}-u_{GS}}d{u}_{GS}$$

(24)

the rise time t_RI is given by:

$$t_{RI}={{\displaystyle \int }}_{U_{GS\left(TH\right)}}^{U_{GS\left(P\right)}}\frac{R_G\cdot C_{iss}}{U_{DR}-u_{GS}}d{u}_{GS}=R_G{C}_{iss}ln\frac{\left|U_{DR}-U_{GS\left(TH\right)}\right|}{\left|U_{DR}-U_{GS\left(P\right)}\right|}.$$

(25)

where U_GS(TH) is a MOSFET gate threshold voltage and U_GS(P) is a minimal value of the gate-to-source voltage, enabling the conduction of the load current I_O. These values may be obtained from a datasheet transfer characteristic i_D(u_GS). After the calculation of parameter t_RI, the value of derivative di_D/dt may be easily estimated using (16).

To estimate the diode turn-off power loss under hard-switching conditions, a reverse-recovery process must be used. Hence, the values of reverse current I_RM and diode reverse recovery time t_RR should be evaluated (Figure 7b). To solve this problem, a number of analytical methods using datasheet information have been proposed. For example, in [28], a regression method was proposed to obtain the reverse-recovery parameters during switching intervals, and in [29], a set of equations including, additionally, the impact of parasitic inductances and diode capacitance, was proposed. These methods offer satisfactory accuracy with a maximum error of parameter estimation lower than 10%, however, their application seems to be complex and time consuming. Considering the waveforms presented in Figure 7b, the values of parameters t_RR, I_RM, and Q_RR depend on the load current I_O, diode current derivative with time a_iDz, and temperature [30]. In this paper, to be concise, the effect of temperature was omitted. Based on the results of the measurements and the manufacturer’s data, the following empirical relations enabling the estimation of t_RR and I_RM for various values of load current I_O and a_iDZ = di_DZ/dt were derived:

$$t_{RR}=t_{RR\left(N\right)}\left(-0.15\left|\frac{a_{iDz}}{A_{iDz\left(N\right)}}\right|+0.2\frac{I_O}{I_{O\left(N\right)}}+0.9\right)$$

(26)

and:

$$I_{RM}=0.2I_{RM\left(N\right)}\left(\frac{I_O}{I_{O\left(N\right)}}+1.25\right)\left(\left|\frac{a_{iDz}}{A_{iDz\left(N\right)}}\right|+1\right),$$

(27)

where:

-

a_iDZ = di_DZ/dt = −a_iD (from Equation (16) and Figure 7b);

-

t_RR(N) is a nominal value of the diode D_Z reverse recovery time measured for the nominal load current I_O(N) and nominal derivative with time of the diode current A_iDZ(N). These nominal values are usually given in the manufacturer’s datasheet.

Thus, the total length of interval t_RI′ (Figure 7b) is given by:

$$t_{RI}^{\prime }=t_{RI}+\frac{\left|I_{RM}\right|}{a_{iD}}.$$

(28)

When the transistor drain current reaches the maximum value, the next phase of the turn-on process begins. Voltage u_DS starts to fall and, by the end of interval t_FV, the recombination process of the diode charge is finished—voltage u_DS is reduced to zero and the diode current is zero (Figure 7b) [12]. Factually, at that moment, the diode current was limited to about 10% of I_RM and the voltage u_DS was reduced to the value resulting from the voltage drop on the conducting transistor. Hence, the transistor voltage fall time t_FV is described by:

$$t_{FV}=t_{RR}-\frac{\left|I_{RM}\right|}{a_{iD}}.$$

(29)

Considering the waveforms presented in Figure 7b and based on the estimated values of t_RI′ and t_FV, the turn-on power loss of the MOSFET P_ON(T) under hard switching conditions is expressed by:

$$P_{ON\left(T\right)}=\frac{1}{T_S}{{\displaystyle \int }}_0^{t_{FV}+t_{RI}\prime }{u}_{DS}\left(t\right)\cdot i_D\left(t\right)dt.$$

(30)

which leads to:

$$P_{ON\left(T\right)}=\frac{U_{DC}}{T_S}\left[\frac{t_{RI}\prime }{2}\left(I_O+\left|I_{RM}\right|\right)+t_{FV}\left(\frac{I_O}{2}+\frac{\left|I_{RM}\right|}{3}\right)\right].$$

(31)

Similarly, the diode reverse recovery power loss is given by:

$$P_{OFF\left(D\right)}=\frac{1}{T_S}{{\displaystyle \int }}_0^{t_{FV}}{u}_{DZ}\left(t\right)\cdot i_{DZ}\left(t\right)dt=\frac{U_{DC}\cdot \left|I_{RM}\right|\cdot t_{FV}}{6T_S}.$$

(32)

During the MOSFET turn-off process under hard conditions, the transistor u_DS voltage reaches the value of the supply voltage U_DC before a reduction in the drain current i_D (Figure 9) [26,31]. Analyzing the MOSFET turn-off process (Figure 9), two characteristic phases may be recognized:

-

during time interval t_RV, voltage u_DC rises to U_DC;

-

during time interval t_FI, drain current i_D decreases do zero.

During time interval t_RV, assuming the gate-to-source voltage u_GS is constant, the transistor is turned off within the flat Miller Plateau Region. Because u_GS = U_GS(P) and du_GS/dt = 0, Equation (22) may be simplified:

$$\frac{U_{DR}-U_{GS\left(P\right)}}{R_G}=-C_{rss} \frac{d{u}_{DS}}{dt} ,$$

(33)

which leads to:

$$t_{RV}=\frac{R_G\cdot C_{rss}}{U_{GS\left(P\right)}-U_{DR}}{{\displaystyle \int }}_0^{U_{DC}}d{u}_{DS}=\frac{R_G\cdot C_{rss}\cdot U_{DC}}{U_{GS\left(P\right)}-U_{DR}} .$$

(34)

The relation describing a current i_D fall time may also be derived in an analogous way:

$$t_{FI}={{\displaystyle \int }}_{U_{GS\left(P\right)}}^{U_{GS\left(TH\right)}}\frac{R_G\cdot C_{iss}}{U_{DR}-u_{GS}}d{u}_{GS}=R_G{C}_{iss}ln\frac{\left|U_{DR}-U_{GS\left(P\right)}\right|}{\left|U_{DR}-U_{GS\left(TH\right)}\right|} .$$

(35)

Thus, MOSFET turn-off power losses are given by:

$$P_{\mathrm{OFF}\left(\mathrm{T}\right)}=\frac{1}{T_S}{{\displaystyle \int }}_0^{t_{RV}+t_{FI}}\left(u_{\mathrm{DS}}(t)\cdot i_{\mathrm{D}}(t)\right)dt=\frac{U_{\mathrm{DC}}\cdot I_O}{2T_S}\left(t_{RV}+t_{FI}\right).$$

(36)

For example, from Figure 3, it can be distinguished that transistor pair T₁ and T₄ in bridge H₁ is switched on when diodes D₁ and D₄ conduct, which forms soft switching conditions. Similarly, the turn-on process of transistors T₂ and T₃ also occurs under ZCS (zero current switching) conditions. Hence, it can be assumed that the turn-on power loss for these transistor pairs P_ON(T) = 0. At moments t₄ and t₇, transistor pairs T₁, T₄ and T₂, T₃ are switched off. In this study, the least favorable operating conditions of semiconductors were assumed, hence, to calculate the power loss P_OFF(T) from Equation (36), it was assumed that transistor pairs T₁, T₄ and T₂, T₃ were turned off under hard-switching conditions with a current i_T1,T4(t₄) = i_T2,T3(t₇) = −I₁ = I₃ and supply voltage U_DC = U_DC1. From Figure 3, it can also be distinguished, that if I₂ < 0, then transistors T₅, T₈ are switched on and diodes D₆, D₇ are turned off under hard-switching conditions. To calculate transistor T₅ turn-on power losses P_ON(T5) and diode D₆ turn-off power losses P_OFF(D6), Equations (31) and (32) should then be used for U_DC = U_DC2 and I_O = I₂/n. The turn-off process of transistors T₅, T₈ occurs under ZCS conditions, hence, the commutation loss P_OFF(T5) equals zero. If I₂ > 0, the transistor T₅, T₈ turn-on process ensues when diodes D₁, D₄ conduct, which allows for the development of soft-switching conditions. Nevertheless, the H₂ bridge transistors’ turn-off process occurs under hard switching conditions. To calculate the commutation power loss P_OFF(T5), Equation (36) may be applied for U_DC = U_DC2 and I_O = I₂/n. Notably, that power loss may be calculated only for one transistor and diode for each of bridges H₁ and H₂. Hence, the power loss of transistor T₁ is given by:

$$P_{T1}=P_{C\left(T1\right)}+P_{OFF\left(T1\right)} ,$$

(37)

where the transistor T₁ conduction power loss P_C(T1) may be calculated from (14):

$$P_{C\left(T1\right)}=\frac{U_{DS\left(N\right)}}{I_{D\left(N\right)}}\cdot I_{T1\left(rms\right)}{}^2 ,$$

(38)

and I_T1(rms)² is obtained by:

If I₂ < 0 (from Figure 3a):

$$I_{T1\left(rms\right)}{}^2=\frac{1}{T_S}{{\displaystyle \int }}_{t_3 }^{t_4}{i}_L^2\left(t\right)dt=\frac{1}{3T_S}\left(\frac{T_S}{2}-t_3\right)I_3^2 ,$$

(39)

and if I₂ > 0 (from Figure 3b):

$$I_{T1\left(rms\right)}{}^2=\frac{1}{T_S}{{\displaystyle \int }}_{t_2 }^{t_4}{i}_L^2\left(t\right)dt=\frac{1}{3T_S}\left[\left(t_3-t_2\right)I_2^2+\left(\frac{T_S}{2}-t_3\right)\frac{I_3^3-I_2^3}{I_3-I_2}\right].$$

(40)

The commutation power loss P_OFF(T1) is described in Equation (36). Because diode D₁ is turned off under soft-switching conditions, only a conduction loss (see Equation (15)) may be taken into account:

$$P_{D1}=P_{C\left(D1\right)}=U_{FO}\cdot I_{D1\left(av\right)}+r_D\cdot I_{D1\left(rms\right)}{}^2,$$

(41)

where I_D1(av) and I_D1(rms)² are given as follows:

If I₂ < 0 (from Figure 3a):

$$I_{D\left(av\right)}=\frac{1}{T_S}{{\displaystyle \int }}_{0 }^{t_3}\left[-i_L\left(t\right)\right]dt=\frac{1}{2T_S}\left[I_3{t}_A-I_2\left(t_A+t_3-t_2\right)\right],$$

(42)

$$I_{D\left(rms\right)}{}^2=\frac{1}{T_S}{{\displaystyle \int }}_{0 }^{t_3}{\left[-i_L\left(t\right)\right]}^{2}dt=\frac{1}{3T_S}\left[\frac{I_1^3-I_2^3}{I_1-I_2}{t}_A+I_2^2\left(t_3-t_2\right)\right].$$

(43)

and if I₂ > 0 (from Figure 3b):

$$I_{D\left(av\right)}=\frac{1}{T_S}{{\displaystyle \int }}_{0 }^{t_2}\left[-i_L\left(t\right)\right]dt=\frac{1}{2T_S}\left[I_3\left(t_2-t_1\right)\right],$$

(44)

$$I_{D\left(rms\right)}{}^2=\frac{1}{T_S}{{\displaystyle \int }}_{0 }^{t_2}{\left[-i_L\left(t\right)\right]}^{2}dt=\frac{1}{3T_S}\left[I_3^2\left(t_2-t_1\right)\right].$$

(45)

For the known values I₁, I₂, and I₃, the length of the time intervals (t₂ – t₁), (t₃ – t₂), and (T_S/2 – t₃) for specific values of voltage U_DC1 and U_DC2/n may be obtained from modified Equations (4)–(6).

The total power losses of the H₁ bridge transistors is equal to:

$$P_{TH1}=4\cdot P_{T1},$$

(46)

and the total power losses for the bridge H₁ diodes are given by:

$$P_{DH1}=4\cdot P_{D1}.$$

(47)

Hence, the total power losses of bridge H₁ is equal to:

$$P_{H1}=P_{TH1}+P_{DH1}.$$

(48)

The total power losses of all transistors (P_TH2) and diodes (P_DH2) in a H₂ bridge may be obtained in an analogous way.

5. Transformer Losses

For the analytical evaluation, it was assumed that the transformer total power loss P_TR is a sum of the power loss in the core P_FE, and the power losses generated in the primary and secondary windings are P_CU(prim) and P_CU(sec).

$$P_{TR}=P_{FE}+P_{CU\left(prim\right)}+P_{CU\left(sec\right)}.$$

(49)

To calculate the core power loss P_FE, a modified Steinmetz’s formula may be used, which for rectangular voltages is given as follows [32,33]:

$$P_{FE}=\frac{8}{{\pi }^2}k{f}^{\alpha }{B}_M^{\beta }\left(c_0-c_1{T}_C+c_2{T}_C^2\right)V_C,$$

(50)

-

f—inducplified waveforms of voltages;

-

B_M—induction peak value [T];

-

T_C—core temperature [°C];

-

V_C—core volume [cm³].

The coefficients of Equation (50) may be directly obtained from datasheets developed by the core manufacturers.

Considering the scheme presented in Figure 2, an equivalent circuit of the transformer connected in series with an additional choke placed at the primary side is shown in Figure 10. Thus, a magnetizing voltage u_Lm affecting the magnetizing inductance L_m is described by:

$$u_{Lm}=\frac{L_{\delta 2}\prime }{L_d+L_{\delta 1}+L_{\delta 2}\prime }{u}_1+\frac{L_d+L_{\delta 1}}{L_d+L_{\delta 1}+L_{\delta 2}\prime }\frac{u_2}{n},$$

(51)

From Figure 2, neglecting a voltage drop on the diodes and transistors and assuming a rectangular shape of the voltage waveforms, the voltages u₁ and u₂/n were equal to, respectively, ±U_DC1 and ±U_DC2/n. From (51), it may be distinguished that the worst working conditions of core occurred when L_d = 0 and L_δ2 = L_δ2′. Hence, the magnetizing voltage u_Lm is then given by:

$$u_{Lm}=\frac{1}{2}\left(u_1+\frac{u_2}{n}\right),$$

(52)

and induction B_M reaches the maximum possible values. Based on waveforms presented in Figure 11, B_M may be described in the following way:

-

if U_DC1 = U_DC2/n (Figure 11a):

$$B_M=\frac{\Delta B_1}{2}=\frac{U_{DC1}}{2N_1{S}_c}{t}_B,$$

(53)

-

if U_DC1 > U_DC2/n (Figure 11b):

$$B_M=\frac{\Delta B_1+\Delta B_2}{2}=\frac{1}{4N_1{S}_c}\left[U_{DC1}\frac{T_S}{2}+\frac{U_{DC2}}{n}{t}_B\right],$$

(54)

-

if U_DC1 < U_DC2/n (Figure 11c):

$$B_M=\frac{\Delta B_1+\Delta B_2}{2}=\frac{1}{4N_1{S}_c}\left[U_{DC1}{t}_B+\frac{U_{DC2}}{n}\frac{T_S}{2}\right],$$

(55)

where S_C is a cross-sectional area of the core.

To simplify the estimation of the transformer windings’ power loss P_CU, calculations may be performed for the windings’ resistance measured for the switching frequency f_S = 1/T_S and the rms value of the windings’ currents according to the formula [32]:

$$P_{\mathrm{CU}\left(\mathrm{prim}\right)}+P_{\mathrm{CU}\left(\sec \right)}= R_{\mathrm{CU}\left(\mathrm{prim}\right)}\cdot I_{1\left(\mathrm{rms}\right)}^2+R_{\mathrm{CU}\left(\sec \right)}\cdot I_{2\left(\mathrm{rms}\right)}^2,$$

(56)

where R_CU(prim), R_CU(sec) are the resistances of the transformer windings (respectively at the H₁ bridge side and H₂ bridge side) measured for the switching frequency f_S; I_1(rms) is the rms value of the transformer current at the bridge H₁ side; I_2(rms) is the rms value of the transformer current at the bridge H₂ side given by:

$$I_{2\left(rms\right)}=\frac{I_{1\left(rms\right)}}{n}=\frac{1}{n}\sqrt{\frac{2}{3T_S}\left[\frac{I_3^3+I_2^3}{I_3+I_2}{t}_A+\frac{I_3^3-I_2^3}{I_3-I_2}{t}_B\right]}.$$

(57)

6. Validation

The parameters that are required for DAB converter efficiency calculation using the proposed approach were collated and are explained in

Table 1. The parameters required for the DAB efficiency estimation.

Parameter	Explanation
POUT	Output power [W]
UDC1	Input voltage [V]
UDC2	Output voltage [V]
n = N1/N2	Transformer turns ratio
TS	Switching period [s]
Ld	Inductance of the additional inductor [-]
Lδ1	Leakage inductance of transformer winding at the H1 bridge side [-]
Lδ2	Leakage inductance of transformer winding at the H2 bridge side [-]
UDS(N)	Rated value of MOSFET drain–to–source voltage [V]
ID(N)	Rated value of MOSFET drain current [A]
UFO	Diode threshold voltage [V]
rD	Diode dynamic resistance [Ω]
Ciss	MOSFET input capacitance [F]
Crss	MOSFET reverse transfer capacitance [F]
RG	MOSFET external gate resistance [Ω]
UDR	MOSFET gate driver voltage [V]
UGS(TH)	MOSFET gate threshold voltage [V]
UGS(P)	Minimal value of the MOSFET gate-to-source voltage enabling the conduction of load current IO [V]
tRR(N)	Nominal value of the diode DZ reverse recovery time measured for the nominal load current IO(N) [s]
AiDZ(N)	Nominal derivative with time of the diode current during reverse recovery current measurement [A/s]
IRM(N)	Diode nominal reverse current measured for AiDZ(N) and IO(N)
f	Induction frequency [Hz]
BM	Induction peak value [T]
TC	Transformer core temperature [°C]
VC	VC—core volume [cm3]

. The described approach was validated by a comparison of the estimated DAB efficiency characteristics with the experimental ones measured for the converter, whose parameters are shown in

Table 2. The DAB converter specifications.

Parameter	Specification
Rated output power	5 kW
UDC1	670 V
UDC2	385 V
T1–T8, D1–D8	F4-23MR12W1M1_B11 (Infineon)
Switching frequency	50 kHz
N1/N2	33/18
Transformer	3C95 ferrite core (SMA Magnetics) OD = 87/ID = 5 6/H = 50 mm
Ld	25 µH

. To measure the input P_IN and output P_OUT power (Figure 12) of the tested DAB converter, a Yokogawa WT5000 precision power analyzer was used. Importantly, the experimental measurements were performed for the DAB converter in a basic configuration without any additional sub-circuits (e.g., start-up resistors were disconnected). Voltages U_DC1 and U_DC2 were kept at a constant level U_DC1 = 670 V and U_DC2 = 385 V and the output P_OUT power was controlled by changes in the load resistance R_L. In the applied laboratory conditions, the maximum output power was limited to 5 kW due to the limitation of the measurement range of the used power analyzer. Waveforms of the current i₁ and voltage u₁ in the AC circuit were measured using a Tektronix DPO3034 oscilloscope equipped with the high-voltage differential probe P5210A and the current probe TCP404XL.

At the first step, the accuracy of the input current average value estimation I_DC1(av) was evaluated. For the known values of the output power P_OUT and voltage U_DC2, based on Equations (7)–(10), the average value of the input current was calculated and compared with the experimental results. The maximum noted difference between the estimated and measured values did not exceed 10% and the accuracy increased with the growth in the output power and input current value (Figure 13). Crucially, the proposed analytical approach was simplified, so the impact of some factors (e.g., time dead influence) was not factored in. As a result, the accuracy of the estimation at a lower level of load may be worse.

A similar conclusion may be drawn for the comparison of the DAB estimated and measured energy efficiency characteristics (Figure 14). The estimated η (P_OUT) characteristic followed the shape of the measured one with the highest accuracy noted for the output power exceeding 50% of the maximum out-power. The maximum noted efficiency for the tested DAB converter in a specific range of output power up to 5 kW reached 98%, which was confirmed by both the experimental and analytical results.

The application of the proposed analytical method enabled an estimation of the power loss distribution for the main converter components. Based on the estimated characteristics presented in Figure 15, it can be stated that the power losses were mainly generated in bridges H₁ and H₂. Notably, the considered DAB converter operated in conditions that correlated with the theoretical current and voltage waveforms presented in Figure 4a. As a result, transistors T₁–T₄ were turned on under hard-switching conditions with current I₁ > 0 and I₁ = −I₃. Thus, the commutation power losses in bridge H₁ resulted from the transistor’s turn-on process and the reverse recovery process of diodes D₁–D₄. Because value I₁ decreases with the growth of the DAB output power (Figure 16), the commutation losses in bridge H₁ also decrease, so, as a consequence, the bridge H₁ total power loss P_H1 is reduced.

From Figure 4a, T₅–T₈ were turned off under hard-switching conditions with the current determined by the value of I₂/n = −I₄/n. Similarly, since the I₂ value increased with the growth of the out-power P_OUT (Figure 16), the transistor’s commutation losses increased, so in bridge H₂, the total power loss P_H2 grew. From Figure 15, the transformer loss P_TR obtained using Equation (49) was significantly lower than the losses noted for bridges H₁ and H₂.

Losses generated in each of the bridges H₁ and H₂ were mainly determined by switching losses, however, the share of conduction losses increased with the growth in the DAB converter output power, which resulted from Equations (14) and (15) (Figure 17).

Based on the results of the analytical calculation, transformer losses P_TR are determined by the loss in the core P_FE (Figure 18). In the tested DAB converter, for the specified range of output power up to 5 kW, the value t_B changed within a small range (coefficient t_B/(0.5T_S) does not fall below 0.95), hence, according to Equations (50)–(55), a slight reduction in the core loss P_FE was observed. The windings’ total power loss P_CU depends on the rms value of the primary and secondary windings currents, so it should grow with the increase in the DAB converter output power, which was confirmed by the results of the analytical calculations.

The presented calculations were also performed for the case when energy was transmitted from bridge H₂ to H₁. In this case, the obtained analytical characteristic η(P_OUT) was also confirmed by the results of the experimental measurements, which validated the adopted approach (Figure 19). Moreover, the results of a detailed analysis of power loss distribution were also convergent with the description above.

Obtained results were compared with ones calculated using the approach proposed in [19]. Adapting this solution is not time-consuming, and all of the required parameters may be obtained based on the manufacturer’s datasheet. However, in [19], no methods of transformer loss estimation were proposed, so in both approaches, the same setup of equations based on Steinmetz’s formula was used to evaluate the transformer losses. Using both of the compared methods, the obtained efficiency characteristics, calculated for the case when energy was transferred from bridge H₁ to H₂, are presented in Figure 20a. Higher accuracy of the proposed solution was noted, especially for the light load of the converter. At higher loads, the predominance of the proposed method was also distinguishable. However, the difference between the measured and estimated results using the approach in [19] decreased with the growth in the output power P_OUT. One of the main assumptions of the method in [19] is that all transistors are switched-on under soft conditions. It should be noted that considering the assumed direction of energy flow, the transistors in bridge H₁ are turned on under hard-switching conditions. As a result of the transistors’ turn-on power losses omission, the total losses of bridge H₁ were underestimated, as presented in Figure 20b. Both compared methods enabled the estimation of the transistors’ turn-off losses. However, to simplify the calculations, in the method [19], constant values of the current fall time were assumed. For the converter light load, the obtained power losses of bridge H₂ were comparable. However, the difference between the calculated results slightly increased with the growth in the output power P_OUT.

7. Conclusions

In this paper, an analytical method of power loss estimation in a single-phase DAB converter controlled with a SPS modulation scheme is presented. The obtained results of the calculations were confirmed by the results of the measurements, which proved the correctness of the adopted approach. The method of optimizing the efficiency of the DAB converter proposed and confirmed in the simulation tests can be used in the process of designing converters at the HW level. The proposed method will allow us to complete the calculation of the correct operating point of the system, which will reduce the risk of failure by reducing the operating temperature of the transistors and passive components. Future studies will be focused on the validation of the presented method in a three-phase DAB converter and for DAB converters driven with other switching schemes.