T-NPC Soft-Commutated Inverter Based on Reverse Blocking IGBTs with the Novel Concept of a DESAT Control Circuit in the Gate Driver

Abstract

This article presents the concept of switching and conduction loss reduction in a T-NPC inverter based on IGBT transistors. The method of limiting switching losses involves the connection of an LC circuit designed to cause transistors in vertical branches to shut down under zero voltage conditions. In order to reduce conduction losses, it was proposed to use two reverse blocking transistors connected anti-parallel in the horizontal branch of the inverter. To ensure safe operation of the transistors, a gate driver proposal for controlling the IGBT reverse blocking transistor is presented. The solution is characterized by a changed part of the driver, responsible for short-circuit protection. It eliminates excessive, destructive currents that can potentially flow through the driver circuit under the influence of the power supply voltage of the power circuit connected backwards to the controlled transistor. Examples of applications and benefits of the proposed solution are presented and verified with laboratory tests.

1. Introduction

NPC (Neutral Point Clamped) converter systems have been developed over the years for implementation in high-power converter systems [1,2]. One of the favorable NPC topologies is the concept of a T-NPC system, which is characterized by a small number of semiconductor devices [3]. These topologies are also the subject of intensive research and, in several publications [4,5,6,7,8], certain research problems related to the implementation of T-type NPC inverters in photovoltaic systems [4,5], in high-power traction systems, and in rectifier systems [7,8] were presented.

Power electronics is an area of engineering that seeks new methods which convert electrical energy in order to maximize efficiency. Solutions often lead to a reduction in switching losses in power transistors. In terms of reducing conducted losses, an improvement was achieved with the use of appropriately selected components. Reducing conduction losses along with the elimination of the number of transistors in the system may be achieved by using reverse blocking IGBTs (RB-IGBTs) in certain topologies [9]. They can be used where a controlled unidirectional current flow is required, and no anti-parallel diode (body diode) is needed. The concept of RB-IGBT modules is still being developed. In [10], the novel concept of an IGBT with bidirectional blocking capability with improvement in E_off and V_on reduction was demonstrated, and in [11] the novel concept of N-channel RB-IGBT with low energy losses and a simplified fabrication process was proposed.

Among the known systems, RB-IGBT devices can be used in current-source inverters, matrix converters, modular multilevel converters (MMC), and in the horizontal branch of the T-NPC voltage inverter. Such solutions eliminate the diode which conducts current in a vertical branch together with a transistor, and thus the conducted losses in the inverter are reduced. Publications [12,13,14,15] presented concepts and results of research on MMC with RB-IGBT transistors. One of the research problems still being analyzed in this type of system is DC Fault Ride-Through. The use of reverse blocking branches simplifies the control and application of industrial MMC. In [16], current-source rectifiers with RG-IGBT implementation were demonstrated. The publication [17] presented a three-phase T-type inverter based on RB-IGBT where high efficiency (98% at 15 kW output power and 600 V input voltage) was achieved, and in [18] a five-level inverter with a bidirectional blocking branch in its structure was analyzed.

The application of RB-IGBT can allow a decrease in power losses in T-type inverters, while the efficiency can be further improved using the soft switching technique. The analysis of IGBT soft turn-off, power losses, and switching processes was presented in [19]. In the case of systems with IGBTs, the amount of energy dissipated during its turn-off can be significant; that is why many concepts for reducing turn-off losses appear. Publications [20,21,22] presented the results of research on a T-NPC type inverter in soft turn-off obtained by using a passive auxiliary switching circuit. The efficiency results presented in [21] positively verified this concept of modification of the three-level T-NPC inverter. In [22], the improvement of the operation of this converter via additional control functions was presented. This system was optimized by using a different, active resonant cell, as presented in [23]. In this system [23], no load current flows through the resonant choke, which reduces its volume. The concept of limiting switching losses by using active commutation circuits can also be found for two-level inverter systems, an example of which is the inverter presented in [24].

Reverse blocking transistors (RB-IGBT) can be controlled using classic drivers. For this type of transistor, however, driver solutions are developed to improve the performance of the transistor. In [25], a gate driver solution was presented to optimize the switching dynamics of the RB-IGBT, which may be worse than those of a classic IGBT. In the case of IGBT transistors, the driver usually has an additional function to protect the transistor against short circuit (DESAT control). The use of classic drivers with a protective function for reverse blocking transistors connected in parallel is impossible, due to the flow of current caused by the supply voltage of the power circuit through the diodes of the driver control circuit. Various methods are used to limit this effect [26,27,28,29]. In [26,27], U_CE voltage detection for the collector’s overcurrent protection used a sensing circuit with a large resistor. This new method was implemented in the new driver project demonstrated in [26,27]. In [28], the concept of modifying the driver protection circuit for RB-IGBT by using resistors and an additional diode implemented with the standard driver was presented. In [29], a concept for a protection system was demonstrated where the CPLD-based circuit managed different categories of IGBT faults.

Publication [30] presented a short-circuit current protection solution in a gate-driver circuit that can also work with a standard IGBT driver. In the solution presented in [30], the DESAT control circuit was activated when the power transistor was switched on. Preliminary analyses of the concept show that it can be very effective, but its application requires verification based on research, which is presented in this article. The results of the research contained in this article include the analysis of T-type three-level inverter systems, with the RB-IGBT transistor implemented.

Overcurrent protection and soft switching operation allow a decrease in the temperature stress of an IGBT switch, which may improve the reliability of a converter. Distribution of failure is the subject of research in multilevel NPC inverters. In [18], there is detailed research of reliability and failure issues in relation to a five-level inverter, where a T-NPC part was used. The issue of the reliability of IGBT transistor-based modules is also the subject of separate studies, as demonstrated in publications [31,32,33,34,35]. In [35], there is an analysis of the factors influencing the failure rate of the IGBT modules. Overcurrent and thermal parameters are important factors that are associated with the DESAT protection implemented in a gate driver.

Contributions to the article include proposing a driver that works with IGBTs and, in particular, RB-IGBTs and making an analysis of a resonant circuit to support the turn-off of transistors in a T-NPC inverter. The driver ensures the effectiveness of the short-circuit protection (DESAT protection) and does not allow, compared with the classical driver application, the flow of destructive current through the DESAT sub-circuit. As a result, it is possible to use RB-IGBT with full protection, for instance, in the horizontal branch of the T-NPC inverter with the RB-IGBT connected in anti-parallel. Such a solution makes it possible to reduce the conducted losses of the system. The driver proposal has been granted several patents. In terms of minimizing switching losses, the use of an additional resonant circuit is presented. The analysis of this circuit was carried out and the criteria for the selection of its parameters were determined.

The article also contains numerous experimental results, giving the possibility to verify the operation of the driver system in the three-level T-NPC type inverter. The setup used in the research allowed us to compare the operation of the inverter system in three configurations, namely the classic system, the inverter with anti-parallel reverse-blocking transistors, and the resonant inverter, which is also included in the article.

The organization of the article is as follows. Section 2 describes a concept for the T-NPC inverter in a topology with auxiliary circuits for soft turn-off as well as the analytical consideration of this circuit. In the same section, a concept for the proposed gate-driver for RB-IGBTs is addressed. The operation of the inverters is verified by experiments, which is presented in Section 3 along with the experimental results.

2. T-NPC Inverter Cases of Implementation for Power Loss Reduction and DESAT Control Circuit in Gate Driver

2.1. T-NPC Inverter in Soft Switching Configuration for the Reduction of Switching Losses

The T-type topology can be supported with a soft switching cell according to the concepts shown in Figure 1 (S3L converter) and published in [15,16,17,18]. In the S3L converter, turn-off losses can be significantly reduced, which is favorable for IGBT-based converters. An auxiliary commutation cell (ACC) of the S3L converter was built of capacitors and diodes in the circuitry, which delayed voltage rise on the transistor during its turn-off process. An additional inductor as used for charging the ACC capacitors.

The process of current commutation in the ACC occurs in several stages which contain charging or discharging of the auxiliary capacitors. Figure 2 presents the results of simulations carried out in the Matlab Simulink, which show the idea of the S3L converter operation.

During the turn-on process (stages F, G in Figure 2) of the transistor in the vertical branch (e.g., T₁), the auxiliary capacitor C₂ is charged from the upper dc-link capacitor connected in series with the resonant inductor (C_in1, T₁, C₂, D_h3, L_res). In the case when the commutation of the load current from the upper transistor of the vertical branch to the horizontal branch occurs, the auxiliary capacitor C₂ discharges (stages B, C, and D in Figure 2). After the vertical switch T₁ is turned off, the current flows via the lower capacitor C₂, causing its discharging. The rate of voltage decrease across the C₂ capacitor determines the rate of voltage rise across the transistor during its turn-off process. At the same time, the current on the auxiliary choke rises and the process of commutation finishes when the current flows via the horizontal branch and the auxiliary choke. The turn-off losses on the vertical switches can be significantly decreased.

A detailed concept and operation of the S3L converter was presented in [15]. In [16,17,18], further issues associated with the S3L converter such as the dead-time, EMC, efficiency, and other solutions were analyzed. An analytical consideration of the ACC is included in the next section.

Analytical Consideration and Selection of the S3L Parameters

When transistor T₁ is switched on (Figure 1), capacitor C₂ is charged in the oscillatory circuit composed of the following devices: C_in1, T₁, C₂, D_h3, and L_res. For zero initial current of the L_res choke, non-zero initial voltage across the capacitor, and zero resistance (no damping) of the charging circuit, the choke current L_res and the voltage across capacitor C₂ are as follows:

$$i_{L\mathrm{r}\mathrm{e}\mathrm{s}}\left(t\right)=\frac{\left({\frac{1}{2}U}_{\mathrm{i}\mathrm{n}}-U_0\right)}{{\rho }_{ch}}{\mathit{sin\omega }}_{\mathrm{ch}}t$$

(1)

$$u_{C2}\left(t\right)={\frac{1}{2}U}_{\mathrm{i}\mathrm{n}}+\left(U_0-{\frac{1}{2}U}_{\mathrm{i}\mathrm{n}}\right){\mathit{cos\omega }}_{\mathrm{ch}}t$$

(2)

where i_Lres [A] is the choke L_res current, u_C2 [V] is the voltage across capacitor C₂, U_in [V] is the system supply voltage, U₀ [V] is the initial voltage across capacitor C₂, ω_ch = (L_resC₂)^−0.5 [rad/s], and ρ_ch = (L_res/C₂)^0.5 [Ω] is the pulsation and wave resistance of the capacitor C₂ charging circuit.

The charging time of capacitor C₂ is equal to half of the overcharge period of the resonant circuit. In order to maximally charge capacitor C₂ in any case, this time interval should be shorter than the shortest conduction time of transistor T₁:

$$t_{\mathrm{c}\mathrm{h}}=\frac{1}{2}{T}_{\mathrm{c}\mathrm{h}}=\pi \sqrt{L_{res}{C}_2}<t_{\mathrm{T}1 \mathrm{O}\mathrm{N}}$$

(3)

where: t_ch [s] is the charging time of capacitor C₂, T_ch [s] is the overcharge period of the resonant circuit, and t_{T1 ON} [s] is the conduction time of transistor T₁.

Assuming zero initial conditions, after the charging time there is maximum voltage across capacitor C₂:

$$U_{\mathrm{C}2\mathrm{m}\mathrm{a}\mathrm{x}}=U_{\mathrm{i}\mathrm{n}}$$

(4)

Capacitor C₂ is discharged in the circuit composed of the devices: C_in2, D_h4, C₂, L_f, and the load. The initial value of the discharge current is I_{load max}. Due to the high value of the output filter inductance L_f and the possible inductance of the load, the oscillating discharge period (ω_dis = (L_fC₂)^−0.5) is significantly greater than the time required to fully discharge capacitor C₂. For this reason, it should be assumed that capacitor C₂ discharges linearly with the load current:

$$\frac{{\mathrm{d}u}_{\mathrm{C}2}}{\mathrm{d}t}=\frac{I_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d} \mathrm{m}\mathrm{a}\mathrm{x}}}{C_2}$$

(5)

where I_{load max} [A] is the maximum value of the load current.

The discharge time of capacitor C₂ should not be longer than the non-conduction time t_OFF of transistor T₁ and not shorter than its turn-off time t_off.

$$t_{\mathrm{T}1 \mathrm{o}\mathrm{f}\mathrm{f}}\le t_{\mathrm{d}\mathrm{i}\mathrm{s}}=\pi \sqrt{L_{\mathrm{f}}{C}_2}\le t_{\mathrm{T}1 \mathrm{O}\mathrm{F}\mathrm{F}}$$

(6)

where t_dis [s] is the discharging time of capacitor C₂, t_{T1 OFF} [s] is the non-conduction time of transistor T₁, t_{T1 off} [s] is the turn-off time of transistor T₁, and L_f [H] is the inductance of the filter choke.

During the t_off turn-off of transistor T₁ at the maximum load current I_{load max}, the voltage across capacitor C₂ should decrease by no more than the assumed ΔU. Then, the minimum capacitance value of the capacitor is defined as:

$$C_{2\mathrm{m}\mathrm{i}\mathrm{n}}=\frac{I_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d} \mathrm{m}\mathrm{a}\mathrm{x}}{t}_{\mathrm{T}1 \mathrm{o}\mathrm{f}\mathrm{f}}}{{∆U}_{\mathrm{C}2}}$$

(7)

If capacitor C₂ is charged to the maximum voltage U_C2max and during the non-conduction of transistor T₁ the load current is minimum I_{load min}, then to ensure its discharge to zero, the capacitance value should not be greater than the following limit:

$$C_{2\mathrm{m}\mathrm{a}\mathrm{x}}=\frac{I_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d} \mathrm{m}\mathrm{i}\mathrm{n}}{t}_{\mathrm{T}1 \mathrm{O}\mathrm{F}\mathrm{F}}}{U_{\mathrm{i}\mathrm{n}}}$$

(8)

In fact, the minimum value of the inverter’s load current is zero at the beginning and the end of each half-period. This allowed us to assume that switching losses were negligible. Therefore, it is necessary to determine the minimum value of the load current for which (8) will apply. For smaller current values, capacitor C₂ will not be fully discharged.

The charging current of capacitor C₂ is added to the load current flowing through transistor T₁. Assuming the maximum value of the collector current I_{T1 max} of transistor T₁, for the maximum load current I_{load max} the minimum value of the inductance of the resonant choke is:

$$L_{\mathrm{r}\mathrm{e}\mathrm{s} \mathrm{m}\mathrm{i}\mathrm{n}}=C_2\frac{{\frac{1}{4}U}_{\mathrm{i}\mathrm{n}}^2}{{\left(I_{T1 \mathrm{m}\mathrm{a}\mathrm{x}}-I_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d} \mathrm{m}\mathrm{a}\mathrm{x}}-∆I_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}\right)}^2}$$

(9)

where ΔI_load [A] is the ripple of the current load.

The maximum value of the choke inductance L_res is derived from the oscillation charging time of capacitor C₂ and the minimum conduction time of transistor T₁:

$$L_{\mathrm{r}\mathrm{e}\mathrm{s} \mathrm{m}\mathrm{a}\mathrm{x}}=\frac{t_{\mathrm{T}1 \mathrm{O}\mathrm{N} \mathrm{m}\mathrm{i}\mathrm{n}}^2}{C_2{\pi }^2}$$

(10)

The amplitude of the current that charges capacitor C₂ is:

$$I_{\mathrm{C}2 \mathrm{m}\mathrm{a}\mathrm{x}}=\frac{U_{\mathrm{i}\mathrm{n}}}{{2\rho }_{ch}}=\frac{U_{\mathrm{i}\mathrm{n}}}{2}\sqrt{\frac{C_2}{L_{res}}}$$

(11)

while the current of the resonant choke is the sum of the load current during the conduction time of the inverter’s horizontal branch transistors and the charging current of capacitors C₁ and C₂.

Analogous charging, discharging, and capacitance selection conditions for the capacitor C₁ occur in the negative half-period of the output voltage.

The currents of diodes D_h3 (D_h2), D_h4 (D_h1) are the same as the charging and discharging currents of capacitor C₂ (C₁), respectively. The maximum voltage across diodes D_h3 and D_h2 is on the level of U_in/2, while the voltage stress across diodes D_h4 and D_h1 is U_in.

2.2. Reduction of the Conducted Losses in a T-NPC Inverter

In the most commonly used solutions, two anti-series connected transistors in the horizontal branch of the T-NPC inverter are used. This ensures controlled current flow in both directions. In this case, the current in the horizontal branch flows through two semiconductor elements—a transistor and a diode in each direction

In a T-NPC inverter, it is possible to reduce the number of semiconductor devices used in the horizontal branch with the use of two reverse-blocking IGBT transistors connected in anti-parallel. Figure 3 shows such a circuit with input capacitors and an output filter. The flow of current in both directions is still controlled, and two diodes are eliminated from the system. Thus, it is possible to reduce system losses by conducted losses of diodes.

In the proposed solution, as well as in other similar ones with reverse-blocking transistors (without body diode), where there is a higher voltage potential on the transistor emitter than on its collector, it is not possible to use a classic gate driver with short-circuit protection (DESAT). In order to maintain full protection, a suitable solution is proposed in in the next section.

Driver with DESAT Control for Anti-Parallel Connected Reverse Blocking Transistors

Figure 4 shows a functional diagram of the classic and the author’s proposed gate driver of an IGBT transistor [30] with applied power transistor short-circuit protection (DESAT control). The circuit in its basic form consists of a gate resistor R_g; short circuit protection elements C_d, R_d, D_d; and diodes D₁, D₂. The diodes D₁, D₂ are necessary to protect the internal DESAT circuit of the driver module. In some models they are found inside the driver IC.

In case of a higher voltage potential on the emitter of a power transistor in the classic driver, there will be a current flow from the ground potential of the driver through the protection diode D₁, resistor R_d, and diode D_d of the DESAT circuit (Figure 4a). This current will be practically limited only by the resistance of the resistor R_d. It is usually 100–1000 Ohms and depends on the IC used. For a voltage occurring at the power transistor of several hundred volts (for example, in an NPC inverter), the current flowing through the DESAT circuit could have a value of up to several amps which is destructive for the circuit.

The operation of the proposed driver circuit, according to the concept presented in [30], for switching on and off the IGBT power transistor is the same as any classical one. The difference lies in the operation of short-circuit protection. To eliminate the possibility of a large current flowing through the circuit, the protection circuit is switched on only for the duration of the power transistor’s operation. This is performed by the S switch (Figure 4b). It can be controlled by a gate signal through the corresponding sub-circuit. The switch was used between the driver IC and the high-voltage diode D_d so it could be, for example, a low-voltage transistor. The whole modification is therefore not expensive or problematic. An example of the implementation of the proposed driver is shown in Figure 5.

3. Experimental Results

3.1. The Laboratory Setup

In order to verify the proposed concepts, laboratory tests were carried out. Three T-NPC inverter circuits were created which contained:

-

the classic inverter with a horizontal branch consisting of anti-series connected IGBT transistors with reverse body diodes;

-

the inverter with a resonant circuit added, according to Figure 1;

-

the inverter with anti-parallel reverse-blocking transistors in the horizontal branch (Figure 3).

Figure 6 exhibits the laboratory setup of the inverter with anti-parallel reverse-blocking transistors in the horizontal branch. The circuit contains transistors placed on a heatsink, complete drivers with a secondary-side power supply, and supporting input capacitors. For the horizontal transistors, the driver proposed was applied (according to Figure 5). The transistors were controlled by an external control system based on Intel Cyclone V. The classic inverter and S3L were very similar and are made in the same way. The PCB has different power tracks in the horizontal branch and the classic drivers were used. The S3L (according to Figure 1) was based on a classic T-NPC inverter with the added L_resC₁(C₂) resonant circuit and D_h1–D_h4 diodes. All three systems can convert the same power.

In all these cases, circuit parameters such as input capacitor capacitances, output LC filters, and control methods were the same. The circuits were tested under the same steady-state conditions.

Table 1. Basic parameters of the system.

Component	Parameters
T1, T4	IKW40N120
T2, T3 (classic T-NPC and Figure 1)	IKW40N120
T2, T3 (Figure 3)	IXRH50N120
Passives (Figure 1)	C1 = C2 = 22 nF, Lres = 20 uH
Diodes (Figure 1)	Dh1, Dh4: C4D20120, Dh2, Dh3: IDP15E60
Input capacitance	Cin1 = Cin2 = 4.23 mF
Output filter	Lf = 150 uH, Cf = 2 × 4, 7 uF

shows the basic parameters of the system.

The waveforms were measured with an MSO68B oscilloscope. Current probes TCP0150, differential-voltage probes THDP0200, and low-voltage probes TPP1000 were used. The efficiency of all T-NPC inverter circuits was measured using a Yokogawa WT3000 analyzer.

3.2. Result of Measurements

Figure 7 shows a set of voltage and current waveforms of the T-NPC inverter with a horizontal branch consisting of two reverse blocking transistors connected in anti-parallel (from Figure 3). A steady-state case was recorded for a supply voltage U_in = 400 V, a load power approximately P_out ≈ 1.5 kW, and a switching frequency f_sw = 15.7 kHz. The waveforms of the inverter output voltage and current as well as the current of transistors T₁ and T₃ are presented. The obtained results show that such a system operates like a classic T-NPC inverter in the most common topology with two transistors containing body diodes connected anti-series in the horizontal branch. The waveforms shown in Figure 7 are for an active power. For another type of load, the waveforms of inverters with transistors in the horizontal branch connected anti-series or anti-parallel will also be the same.

Figure 8 shows the efficiency results of the three systems presented earlier. The difference in efficiency of the classic T-NPC system compared with the proposed topologies ranges from 0.1% to 0.45%. The largest improvement of approximately 0.5% was visible for the S3L system in the low power range. The number and type of transistors used in the experiments were the same, while the turn-off losses of T₁ and T₄ have been reduced. For a light load, these losses are relatively large. As the load power increased, their share decreased and remained at 0.15–0.2%. When comparing the efficiency of the system in Figure 3 with a classic T-NPC inverter, the tendency is different than before. The number of semiconductors and conducted losses on them has now been reduced; therefore, the efficiency difference remains at a similar level over the entire load range. The results in this case will always depend to a small extent on the type of transistor used.

Figure 9 shows the measurement results of the driver circuit proposed in Section 2 (Figure 5).

While the driver IC controlled the IGBT transistor in the power circuit (u_OUT = 15 V), the auxiliary transistor T₁ was switched on with the same signal (Figure 5). This caused the activation of transistor T₂ in the DESAT circuit. The power transistor was then switched on and the driver performed voltage drop control on its collector-emitter structure. During this time interval, the current could flow through the IGBT transistor. When the IGBT transistor was not conducting, the signal u_OUT = 0 V and transistors T₁ and T₂ were turned off. The DESAT circuit was disconnected. This solution does not allow current to flow from the emitter potential of the IGBT transistor (e.g., from the power source of the power circuit) through the driver circuit.

4. Discussion

The article presents two concepts to reduce losses in a T-NPC inverter. In each case they gave positive results confirmed by laboratory tests. In case of switching loss reduction, it is necessary to add an LC circuit. This solution is cost-effective in high power systems due to the minimization of relatively high switching losses always occurring during system operation and increasing efficiency. In low-power systems, it may not be cost-effective due to low losses and the possibility of using other types of transistors. In addition, the use of an LC circuit requires a relatively small financial outlay and is a source of little additional loss. However, as shown in the laboratory test, even for a low-power system with IGBT transistors, the use of LC cells increases the efficiency of the system. In the case of limiting the conducted losses, the financial outlay are negligible due to the preservation of the same number of power elements. Similarly, modifying the driver according to the presented solution only requires the investment of two transistors and four low-power resistors. In comparison to existing solutions, the proposed concept is relatively simple and does not require a lot of financial investment. It also does not require the use of high-power current-limiting resistors, which may cause additional power losses and current passing in the protection circuit. The solution proposed in this paper allows RB-IGBT transistors to be used in complete safety. The increase in efficiency in this case will depend on the parameters eliminated and used semiconductors in the horizontal branch. The use of the proposed driver increases the safety of the system.

The proposed gate driver and methods of losses reduction presented In the article can also be applied in many other power electronic systems. Such gate drivers can be used in all applications with RB-IGBTs as well as with all IGBTs. RB-IGBTs with the proposed gate-driver can be applied in a horizontal branch of the T-NPC inverter, current inverters, or matrix converters. The presented resonant cell is dedicated to this topology; however, with appropriate modifications it can affect the minimization of switching losses of transistors in other circuits, such as in buck or boost converters. These issues and also the optimization of the resonance cell are further research directions.