Implementation of Phasor Measurement Unit Based on Phase-Locked Loop Techniques: A Comprehensive Review
Abstract
:1. Introduction
2. Synchrophasor Concepts
- Frequency step change test: A cosine signal with a frequency deviation of ±2 Hz for P class and ±5 Hz for M class of the nominal frequency.
- Magnitude deviation test: A cosine signal with an amplitude of 80% to 120% and 10% to 120% of the rated amplitude for P class and M class, respectively.
- Phase angle variation test: A cosine signal running at a frequency of for both PMU classes.
- Harmonic distortion test: A signal containing 1% and 10% of each harmonic up to 50th for P class and M class, respectively.
- Out-of-band interference test: The frequency of the signal varies between nominal frequency and ±10% of half the frequency of the reporting rate. This test is applicable only for P-class PMU.
- Amplitude modulation test: A cosine signal with a modulation amplitude of 10% of the rated amplitude value and modulation frequency of 2 Hz and 5 Hz for P class and M class, respectively.
- Phase angle modulation test: A cosine signal with a modulation angle of 0.1 radians and modulation frequency of 2 Hz and 5 Hz for P class and M class, respectively.
- Linear frequency ramp test: A cosine signal running at the nominal frequency by adding a frequency ramp of ±2 Hz/s and ±5 Hz/s for P class and M class, respectively.
- Magnitude step change test: A cosine signal with a 5% and 10% of the nominal magnitude step change for P class and M class, respectively.
- Phase angle step change test: A cosine signal with a 10° step change for both PMU classes.
3. Basic Concepts of the Three-Phase PLL
4. PLL-Based Algorithm for the Estimation of the Synchrophasor
4.1. PID SRF-PLL-Based Algorithm for Positive-Sequence Synchrophasor Estimation
4.1.1. Experimental Results under Steady-State Conditions
4.1.2. Experimental Results under Dynamic Conditions
- Amplitude modulation test: The TVE is almost proportional to the value of the modulation frequency. Consequently, the TVE is considerably smaller for P class compared to M class since the required modulation frequency for P class is smaller than the corresponding M-class modulation frequency. Nevertheless, the proposed algorithm meets the requirement for both P and M classes.
- Phase angle modulation test: In this test, the proposed algorithm performs satisfactorily in terms of error values required by the standard making it compatible with both P and M classes.
- Linear frequency ramp test: The linear frequency ramp test results depict that the proposed algorithm fulfils all requirements for both PMU classes P and M.
- Amplitude step change test: The test results show that the TVE, FE and RFE narrowed very fast within the acceptable limits of the IEEE standard. Consequently, the proposed algorithm fulfils the requirements.
- Phase step change test: During the transient period, a small overshoot in the estimated signal amplitude occurred, causing phase and frequency errors that did not exceed the acceptable range for P and M classes.
4.2. Three-Phase Enhanced PLL (EPLL)-Based Algorithm for Synchrophasor Estimation
4.2.1. Simulation Results
- Amplitude step change test: The initial three-phase balanced grid voltages undergo a step change of 10% of the fundamental amplitude. In steady-state conditions, the TVE value is below 1%. During the transient, the FE reaches 25 mHz, ROCOF reaches 4 Hz/s and the phase angle error reaches 1.25°.
- Phase angle step change test: The initial three-phase balanced grid voltages undergo a phase angle step change of 10°. In steady-state conditions, the TVE value is below 1%. During the transient, the FE reaches 100 MHz and ROCOF reaches 6 Hz/s. The phase angle is accurately detected.
- Frequency step change test: The initial three-phase balanced grid voltages undergo a frequency step change of 0.1 Hz. In steady-state and dynamic conditions, the TVE value is below 1%. During the transient, the ROCOF reaches 5 Hz/s and the phase angle error reaches 0.25°. The frequency step change is accurately detected.
- Linear frequency ramp test: The frequency of the grid voltages increases with a ramp function of 1 Hz/s. Under this dynamic behavior, the TVE is about 0.1%, the phase angle presents an error of 0.1°, and the frequency is tracked with a steady-state error of 20 MHz. It is worth mentioning that the ROCOF is accurately detected.
- Unbalanced Signal test: Negative- and zero-sequence components with a magnitude of 10% are induced in the three-phase balanced voltages. The PLL rejects the undesired components providing TVE less than 2% during transients and less than 1% in steady state.
- Harmonic distortion test: A signal containing 1% of each harmonic up to the 15th is induced in the three-phase balanced voltages. The TVE value is below 0.8%, the phase angle error is less than 0.5°, and no steady-state error has been observed in terms of frequency and ROCOF.
- Amplitude and Phase Modulation test: The modulation amplitude with a frequency of 2 Hz and a magnitude of 10% is applied to the PLL. The phase angle provides a peak error of about 0.25°, the FE is about 60 MHz, the peak value of RFE reaches 0.5 Hz/s and the TVE is almost 1%.
4.2.2. Experimental Results
- Initially, the grid voltages are in normal condition when at time t = 0.5 s the following harmonics are injected into the grid: 5th, 7th, 11th and 13th, with the corresponding amplitude of 8%, 5%, 3% and 1% of the fundamental component. Under steady-state abnormal conditions, the TVE value is below 1%, FE is ±0.002 Hz and ROCOF is 40 Hz/s. The ROCOF value reaches 60 Hz/s during the transient period.
- Initially, the grid voltages are in normal condition when at the time t = 0.5 s a source voltage is connected to the network that bears an imbalance factor of 10% of the negative sequence. Under steady-state abnormal conditions, the TVE value is below 1%, FE is negligible and ROCOF is 0 Hz/s. The ROCOF value reaches 80 Hz/s during the transient period.
- In this test case, harmonics (from the first case) and low-frequency oscillations (of 1 Hz) are injected into the grid voltages. Under steady-state abnormal conditions, the TVE value is below 1%, while the ROCOF value reaches 40 Hz/s.
- In this final test case, all the above abnormal conditions are considered (harmonics, sequence unbalance and low-frequency oscillations). Under steady-state abnormal conditions, the TVE value is below 1%, while the ROCOF value reaches 30 Hz/s.
4.3. Double Frequency and Amplitude Compensation (DFAC)-PLL-Based Algorithm for Single-Phase Synchrophasor Estimation
4.3.1. Simulation Results under Steady-State Conditions
- Amplitude step change test: The amplitude of the input signal applied to the PLL varies from 10% to 120% in steps of 10% of the nominal amplitude. The limits for FE, RFE and TVE defined in IEEE standard [4,7] are 0.005 Hz, 0.1 Hz/s and 1%, respectively. The corresponding estimated values provided by the PLL meet the requirements.
- Frequency step change test: The frequency of the input signal applied to the PLL varies from 45 to 55 Hz. The limits for FE, RFE and TVE are the same as the amplitude step test. The corresponding estimated values, provided by the PLL, meet the requirements.
- Harmonics distortion test: Different sinusoidal signals containing harmonics (from 2nd to 50th) one at a time with an amplitude of 10% are applied to the PLL. The limits for FE and TVE defined in IEEE standard [4,7] are 0.025 Hz and 1%, respectively. The PLL provides TVE and FE within limits for harmonic orders greater than 10th and 39th, respectively.
4.3.2. Simulation Results under Dynamic Conditions
- Amplitude and phase angle modulation test: A sinusoidal modulation in the amplitude (with modulation frequency varying from 0.1 to 5 Hz) with a magnitude of 10% is applied to the PLL. According to the IEEE standard [4,7], the limits for FE, RFE and TVE are 0.3 Hz, 14 Hz/s and 3%, respectively. The proposed PLL succeeds in complying with the Standard for the FE and TVE but violates the RFE limit.
4.4. Harmonic Inter-Harmonic and DC Offset (HIHDO)-PLL-Based Algorithm for Three-Phase System Synchrophasor Estimation
4.4.1. Simulation Results of the HIHDO PLL-Based PMU Algorithm
4.4.2. Experimental Results of the HIHDO PLL-Based PMU Algorithm
- Phase angle step change test: The three-phase input signals undergo a phase angle jump of +30°. The PMU managed to track the phase angle step change while it obtained the value of +30° in 70 ms. During transients, slight overshoots occurred in the waveforms of the estimated signal amplitude and frequency with a settling time of 80 ms. Under this condition, the frequency reached 2.1 Hz and the amplitude 0.1 per unit at the time the phase angle step change occurred.
- Harmonic distortion test: In the grid voltages, the following harmonics were injected: 5th and 7th with the corresponding amplitude of 6% and 5% of the fundamental component. Furthermore, a phase angle step of −20° was introduced. The PMU succeeded in rejecting the high-frequency components while accurately estimating the signal amplitude, angle and frequency. During the transients, the voltage amplitude and frequency overshot were 1.6 Hz and 0.05 per unit, respectively. The settling times for the frequency, magnitude and phase estimations were 80 ms, 66 ms and 65 ms, respectively.
- Inter-harmonics and DC-offset rejection test: The PMU succeeded in rejecting the inter-harmonic and DC-offset components while accurately estimating the voltage amplitude, phase angle and frequency.
- Harmonics and voltage sag injection, and frequency step test: A combined set of test signals were applied to the proposed PLL-based PMU, comprising of 5% 7th, 3.5% 11th, 3% 15th and 2% 17th harmonics, voltage sag of 37% and frequency step change of −2 Hz. The harmonics were effectively compensated, resulting in an accurate estimation of voltage amplitude, phase angle and frequency. The proposed algorithm managed to detect the voltage sag within 10 ms while the settling time for the estimated frequency and phase angle were 80 ms and 140 ms, respectively. Furthermore, the PMU tracked the step change of the frequency within 100 ms.
5. Discussion
- The PID SRF-PLL-based PMU algorithm provides satisfactory experimental results in the estimation of positive-sequence amplitude, phase angle, frequency and ROCOF. In addition, the implementation of the algorithm presents a low computational burden, making it capable of being developed on a general-purpose microcontroller with DSP features. The experimental results showed that the proposed PLL-based PMU algorithm for the synchrophasor estimation complies with all the IEEE standard requirements [4,7] for both PMU classes P and M, while in conjunction with the low computational cost, makes it attractive for implementation of low-cost PMUs in order to be used in distribution networks [35], although it provides a low reporting rate.
- The EPLL-based PMU algorithm provides good experimental and simulation results in estimating positive-sequence amplitude, phase angle, frequency and ROCOF for a P-class PMU. It is worth noting that the estimated frequency and ROCOF are derived from the processing of the information obtained from all three signal components, making these estimated measurements more reliable and stable. In terms of amplitude and phase angle modulation tests, the proposed method meets TVE requirements but failed in estimating accurately the frequency as well as the ramp frequency test [21]. The proposed PMU algorithm addresses the abnormal grid conditions such as imbalances and harmonics, while also providing a fast dynamic response and acceptable steady-state accuracy which make it a potential candidate algorithm for a P-class phasor measurement unit [39]. It can be observed from [39] that the computational complexity of the proposed algorithm is low; therefore, it can be implemented on a low-cost microprocessor.
- The DFAC-PLL is a single-phase PLL that can estimate the phase amplitude, angle and frequency of the input signal [42]. Although the compliance testing of the PLL in accordance with the IEEE standard [4,7] is performed without the pre- and post-filtering stages, it shows that it can meet the requirements of the steady-state condition tests, while exceeding the acceptable limits in the harmonic distortion and out-of-band interference tests. In terms of dynamic condition tests, the proposed PLL meets the requirements for the synchrophasor estimation when subjected to the amplitude modulation test but exceeded the limitations in the phase angle modulation test. In case the DFAC-PLL is to be used for synchrophasor estimation algorithm, the filtering and compensation stages are required.
- The HIHDO-PLL-based PMU successfully faces the normal and abnormal grid conditions, while presenting excellent simulation results in the estimation of the positive-sequence component of phase magnitude and angle of the power grid. Moreover, it provides fast dynamic response and slight overshoots without sacrificing the required accuracy under harmonically polluted and faulty network conditions which is also the case for the estimation of the synchrophasor in a more realistic power grid. The proposed PLL presents a lower computational burden compared with existing PLL algorithms in the recent literature for addressing both the imbalances and harmonic distortion due to abnormal grid conditions, but its execution requires 106 mathematical operations, which is an important burden if its implementation is performed by a general-purpose microcontroller with DSP features. With the exception of the computational burden, the mathematical analysis and simulation results on network faults showed that the HIHDO-PLL has the potential to be used for synchrophasor estimation algorithms [43].
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
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PLL-Based PMU Approach | ||||
---|---|---|---|---|
PID SRF-PLL | EPLL | DFAC-PLL | HIHDO-PLL | |
Harmonic rejection | Good | Good | Poor | Very good |
Dynamic response | Faster | Fast | Slow | Fast |
Computational burden | Low | Medium | Medium | High |
Compliant with IEEE Std. | Yes, for P and M classes | Yes, for P class. Minor deviations | No | Should be investigated |
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Giotopoulos, V.; Korres, G. Implementation of Phasor Measurement Unit Based on Phase-Locked Loop Techniques: A Comprehensive Review. Energies 2023, 16, 5465. https://doi.org/10.3390/en16145465
Giotopoulos V, Korres G. Implementation of Phasor Measurement Unit Based on Phase-Locked Loop Techniques: A Comprehensive Review. Energies. 2023; 16(14):5465. https://doi.org/10.3390/en16145465
Chicago/Turabian StyleGiotopoulos, Vasilis, and Georgios Korres. 2023. "Implementation of Phasor Measurement Unit Based on Phase-Locked Loop Techniques: A Comprehensive Review" Energies 16, no. 14: 5465. https://doi.org/10.3390/en16145465