1. Introduction
The power system in the modern era has evolved into large and complex interconnected systems which is composed of nonlinear and dynamic elements. The development of smart grids has led to wide-scale integration of numerous elements at different operation levels of the grid. This has created complexities in the system and operational challenges that can be resolved using real-time digital computation, and advanced sensors and communication technologies [
1,
2,
3]. With the increased sophistication in the methods and equipment for testing, power system simulation tools can play a major role in the testing and analysis of the system.
Power system simulation methods are mainly classified in two types: offline simulation and real-time simulation. Offline simulation methods have limited ability to provide an accurate simulation for the behavior of real-life equipment and practical systems [
4]. The real-time simulation technology can perform numerous complex operations on the power system as they consist of high-speed processors and can provide higher efficiency and performance. Recently, Hardware-in-the-Loop (HIL) simulation has gained popularity, as it can wedge the gap between the behavior of the simulated and real system. In HIL testing, the power system under study is represented by a simulation model on a real time simulation platform, and the equipment under test is outside of the model but is linked to the simulation model through special Digital to Analog and Analog to Digital cards and necessary sensors and amplifiers [
4,
5]. One of the biggest advantages of HIL is that it can reduce the risk of field errors in actual scenarios [
6]. HIL testing allows for simulating a real scenario of the power system, such as a fault situation, and provides accurate data on handling such situations in the real world [
7]. HIL simulation platform performs time domain simulation to generate transient waveforms that are encountered in many protection applications [
8,
9,
10].
With the increased energy demand, it has become crucial to procure the demand in an economically and environmentally sustainable way. Due to this, the stability and safety limit of modern power grids are being pushed. To handle the surge and the pressure, utilities are adding sophisticated new schemes and devices to their networks [
11]. Whenever a new equipment and controller is added to the system, it needs to be tested and tuned before adding it to the network. In this situation, HIL simulation can be used for analyzing the new equipment in the simulated model before commissioning in the field [
4,
5,
12].
Over the years, real-time simulation has become popular among manufacturers and utilities to assist them in the study of behavior and operation of the power system, performing the closed-loop testing of new equipment, and developing new protection and control functions [
11].
Out of all the functions performed by a real-time simulation system, this paper is concerned with performing closed-loop testing of directional overcurrent relays using RTDS. Closed-loop testing of equipment in a model power system can mimic the characteristics of the system in a realistic scenario. Hence, readily decipherable information can be obtained on the performance of the equipment. In closed-loop testing of the relay, the RTDS outputs voltage and currents signals that are fed to the relay, and the relay provides an output, i.e., a tripping signal to the RTDS to open the circuit breaker in the RTDS model to disconnect the faulted section, and the simulation continues with the updated model [
13]. The closed loop setting is ideal for testing the coordination between multiple relays.
A directional overcurrent relay is one of the primary safety equipment used in a networked, non-radial electrical distribution system to ensure the reliable and efficient operation of the power system. This relay monitors the current flowing through the protected element and generates a trip signal to the circuit breaker in the case of an occurrence of a fault, i.e., when the current exceeds the value of pickup current in the relay [
14].
Numerous studies have been conducted in the field of HIL testing. These studies have been performed for various power system equipment using different real-time simulation software. F. R. Adegbohun et al. conducted a HIL testing for a grid-connected PV system consisting of SEL-421 relay, to test the hardware compatibility and model reliability [
7]. A performance analysis of relays was done by M. Afshar et al. for detection of high impedance faults using a RTDS. A 15-bus system was modeled in RSCAD with an arc model for the high impedance fault [
15]. The authors of [
16] proposed an improved numerical algorithm based on PSCAD/EMTDC simulation to eliminate the overreach issue in distance relay caused due to transients of the coupling capacitor voltage transformer. The authors proposed a prototype for distance relay that was tested using RTDS. The proposed relay had a faster operation speed and higher reliability. Y. S. Cho et al. designed a RSCAD model containing multi-function relay and mimic board to improve the understanding of the technology associated with the protection and operation of the power system [
17]. K. H. So et al. performed a closed-loop testing for differential and distance relay using EMTP [
18]. O. Dias et al. [
19] and T. Ledwaba et al. [
20] focused on the HIL testing of transmission network. In [
19], a 500 kV Brazilian transmission network was protected using SEL-421 distance relays. The simulation was performed for two fault cases: permanent and transient faults. The results were also cross-checked with the available field data. The HIL testing using ABB RED 670, a differential relay for a 400 kV, 50 Hz transmission network was performed in [
20]. They also studied the system dynamics with additional equipment, such as series capacitor. A non-linear programming based adaptive protection scheme for coordination of directional overcurrent relays in a 7-bus system was proposed in [
21]. The results were validated using RTDS. Reference [
22] proposed a coordination algorithm for advanced distance, and an over current relay was proposed that was validated using RTDS and Avera hardware relays. In [
23], a flywheel energy storage system (FESS), a primary energy storage component of an energy magazine, was tested using a Power Hardware-in-the Loop (PHIL) simulation. A 3.5MJ, 320kW FESS was virtually interfaced with a simulated model of a shipboard. M. Stifter et al. presented a PMU-RTS-HIL testbed for validation and testing of multiple PMUs. Various HIL platforms exist, such as Opal-RT, Typhoon, and RTDS. Opal-RT was used for the aforesaid task [
24]. Reference [
25] illustrated recent best practices in the field of development of real-time simulator, from the perspective of RTDS.
This paper uses RTDS to perform HIL tests, and it is expected that the method is readily extendable to other real time simulation platforms. The paper provides a thorough illustration of calculating scaling factors of GTAO card of RTDS, cable connection between digital I/O cards of RTDS and low-level interface of relay, connection with power amplifiers, and consideration of amplification factor of amplifiers in calculating GTAO scaling factors. It is crucial that these tasks are performed correctly to have a successful experiment.
The rest of the paper is organized as follows:
Section 2 describes the RSCAD model developed in RTDS for a five-bus system selected for this experiment.
Section 3 describes the procedure to configure the SEL-351 relays before they are used for HIL testing.
Section 4 explains the different relay schemes used in the HIL testing.
Section 5 discusses the key components and procedures in interfacing of the relays with the RTDS.
Section 6 presents the findings achieved for the work carried out in
Section 2,
Section 3,
Section 4 and
Section 5.
Section 7 concludes the methodology used for this research.
3. SEL-351 Relay Configuration
To configure the SEL-351 relay, SEL’s AcSELerator Quickset software was used. In this study, two SEL-351 relays were chosen. The configuration was done as follows. First, the communication between the computer and the relay was established. Then the as-found relay settings were read to the computer. In the ‘General settings’, the CT and PT ratio were set to 120 and 60 (12,470 / 60 = 207 V secondary L-L), respectively, for both the relays. The parameters in ‘Line Settings and Fault locator’ section, as shown in
Figure 4, needed to be calculated as follows:
The pickup current of 50P1P level 1 in the ‘Phase Instantaneous Overcurrent Elements’ and the value of ‘67P1D level 1’ in the ‘Phase Definite-Time Overcurrent Elements’ can also be set as shown in
Figure 5. Settings have been provided for R1, shown in
Figure 5. R2 can be set in a similar way. The 50P1P level for R2 will be less than R1 (0.77 in this case) as R2 is supposed to act first. 67P1D level for R2 will be set to zero as R2 is operating under instantaneous overcurrent scheme.
Another setting is the Trip logic equation, which will be 67P1T, 50P1, 51PT—to be explained in later sections. The Trip logic equation for R1 and R2 was set to 51PT under the IDMT overcurrent scheme in
Figure 6. For R2, 50P1 was used under the instantaneous overcurrent scheme, and 67P1T was used for R1 under the definite-time overcurrent scheme.
After entering the desired relay settings, the settings were written to the relay.
5. Interfacing Relays with RTDS
Figure 8 illustrates the setup for Hardware-in-the-Loop testing of SEL-351 relay using RTDS for the five-bus system.
Figure 9 shows the functional block diagram for the HIL setup.
As it can be observed from
Figure 9, two circuit breakers, CB1 and CB2, were used in the power system under study. CB1 was used for relay R1, and CB2 was used for R2. To connect both relays, R1 and R2, with RTDS, we required the Giga-Transceiver Analogue Output (GTAO) card and Gigabit-Transceiver Front Panel Interface (GTFPI) card provided in the RTDS. The GTAO provided analog signals, which could then be fed to a relay through an amplifier or through the low- level interface of the relay. In this study, we performed experiments using both the low-level interface method and CMS 356 (i.e., the amplifier). For successful implementation, one must consider the relay’s low-level interface scales, the current and potential transformer turns ratio, and the GTAO voltage and current scales. The GTAO provided the modeled system output to the relay, and when a fault was simulated, the relay sent a trip signal to the GTFPI card that in turn signaled the circuit breaker, which modified the simulation model, thus forming a closed-loop system. R1 here was to serve as a backup relay for faults within the protection zone of R2. When the fault occurs, R2 was supposed to act first to clear the fault. However, in case of failure of R2, R1 must act after a specified coordination delay, e.g., 4 cycles.
In
Figure 9, the Amplifier refers to external devices, such as the Omicron CMS 356, which can convert RTDS low current and voltage signals (0–5 V rms) to higher current and voltage signals (0–5 A, 0–120 V rms) that are at the same level of actual CT and VT signals that can be fed to the tested relays’ current and voltage input terminals on the backside without using the relay’s low-level signal interface.
Section 5.1 and
Section 5.2 provide a detailed description about the configuration of GTAO and GTFPI card, respectively, to perform their assigned operations shown in
Figure 9.
5.1. GTAO Card
The GTAO card can be modelled in the RSCAD software using the GTAO element as shown in
Figure 10. A GTAO card has 16 input ports. For our experiment, we needed 14 ports. In
Figure 10, port 1 to 7 were the current and voltage inputs for relay R2, and port 8 to 14 were the current and voltage inputs for relay R1. The GTAO card took these inputs and provided analogue outputs to the relay input port. In
Figure 9 and
Figure 10, Ia, Ib, and Ic were the input phase currents for R2, and Ia_R1, Ib_R1, and Ic_R1 were the input phase currents for R1. In and In_R1 were the neutral currents for R2 and R1, respectively. At bus 1, ‘phase1Asamp’ (Va), ‘phase2Asamp’ (Vb) and ‘phase3Asamp’ (Vc) were the phase voltages.
The connections shown in
Figure 10 were determined as per the highlighted connections given on the relay low-level test interface as shown in
Figure 11. The rightmost parameter ‘IA’ given on the relay panel was considered as the connection on the input port 1 on the GTAO element shown in
Figure 10 for relay R2 and so on. As observed from highlighted area in
Figure 11, the first four parameters were for currents, and the rest were for voltages. Not following the given connection pattern will result in errors in values on the relay front panel.
The above-mentioned parameters were sampled using a sampling frequency of 7.68 kHz before being provided as an input to the GTAO card. This can be done using the sampler element provided in the RSCAD library as shown in
Figure 12.
5.1.1. GTAO Scaling When Using Relay’s Low-Level Interface
The input parameters shown in
Figure 10 needed to be scaled to a value within ±5 V before being sent as input to the GTAO card. These values were internally scaled in the GTAO element. This section discusses the process of obtaining the scaling factor for input current and voltage parameters for GTAO. When providing the output of the GTAO card to the relay, it is also important to consider the scaling factors of the relay. The scaling factors available for SEL-351 relay can be seen in
Table 2. Initially, the required GTAO output voltages were calculated using the relay scaling factors, Current Transformer Ratio (CTR), and Potential Transformer Ratio (PTR). Then, these voltages were used to calculate the current and voltage scaling factors for the GTAO card.
Figure 13 shows the connection on the relay end between the GTAO card of the RTDS and relay. J1 was the terminal connector for input module of the relay, and J10 was the terminal for the processing module of the relay. J10 received the input secondary current and voltage parameters from the GTAO. After receiving the input secondary values, the processing module converted these values to primary values as per the relay scaling factor, CTR and PTR. These primary values could be verified on the relay front panel.
Figure 14 shows the connection made on the GTAO card to provide output current and voltage values to the relay. The bottom most port of the card was the first output port of the card. The connections shown here were made as per the connection diagram shown in
Figure 10 and
Figure 11. Port 1 to 7 were the output values provided to relay R2, and port 8 to 14 were the output values provided to relay R1.
For the relays used in this study, a scaling factor of 50 for current and 102 for voltage in the relay was adopted.
5.1.2. GTAO Scaling When Using CMS 356
The GTAO scaling was calculated differently when using CMS 356 in contrast with when using relay’s low-level interface.
In this study, the voltage amplification factor was 60 V/V, and the current amplification factor was 6.4 A/V for the CMS 356.
The GTAO scaling was calculated as follows. We have the following relationship between the GTAO output and the actual voltage and current:
The actual voltage is also expressed as:
The actual current is expressed as:
Here, PTR is Potential Transformer Ratio, and CTR is Current Transformer Ratio.
The GTAO scaling factor for voltage can be obtained by substituting Equation (3) in Equation (5).
Equation (7) can be used to calculate the GTAO scaling factor for voltage.
For a PTR equal to 60 and
of 60, the
Vsf will be as follows:
The GTAO scaling factor for current can be obtained by substituting Equation (4) in Equation (6).
Equation (8) can be used to calculate the GTAO scaling factor for the current.
For a CTR equal to 120 and
of 6.4, the
will be as follows:
5.2. Obtaining Readings on the Relay Front Panel
After getting the required output from the GTAO card, to show the reading on the relay front panel, i.e., the primary side value, multiply the GTAO output by the current or potential transformer ratio and the scaling factor of the relay. In case of using relay’s low-level interface, the formulae are shown below:
Table 3 shows the voltage output and scaling factors obtained for GTAO for our experiment. The current and voltage values shown in
Table 3 were the pre-fault values obtained on the relay front panel using the GTAO scales shown in the table. The calculations were verified by the actual readings on the relay.
When using CMS 356, the Relay reading would be calculated as the product of GTAO output and the CMS 356 amplification factor and the PT and CT ratio.
5.3. GTFPI Card
The GTFPI card was used to transmit the trip signal from the relay to the circuit breaker in the RSCAD model, as shown in
Figure 16. The relay trip signal is transmitted from the relay to the RTDS digital interface panel, as shown in
Figure 17 and
Figure 18.
In
Figure 16, ‘OUT 101’ and ‘OUT102’ are the trip signals from R1 and R2, respectively. ‘Inp_GTFPI’ is the input signal being provided from the GTFPI element. The input signal is a single word that can be converted into multiple logic outputs using a word/bit converter. The outputs of this converter are digital trip signals, i.e., logical outputs. These trip signals are then provided as an input to the digital interface panel provided on the front panel of RTDS, as shown in
Figure 18. If there is only one trip signal, the converter is not required as only one port of the digital interface panel is needed. In the case of multiple trip signals, this converter is required as only one GTFPI element can be used in a RSCAD model, and this experiment required more than one port of the digital interface panel. Here, each port was considered as one bit. Two input ports will capture the two trip signals. Hence, two bits were obtained using the converter.
Figure 17 shows the connections done on the relay back panel for providing input signals to the digital interface panel of RTDS. It can be observed from the figure that ‘OUT101’ terminal of the relay has two connections (i.e., one for trip signal and another for ground). However, in general, the first terminal of the relay was the input signal, and the second terminal was ground, unlike the relay shown in
Figure 17.
The connections coming from ‘OUT 101’ shown in
Figure 17 were provided to the digital interface panel, as shown in
Figure 18. As mentioned previously, two ports of the panel were used, i.e., one for relay R1 and one for relay R2. The input trip signal coming from relay was connected to the digital input channel on the panel, and the ground signal coming from relay was connected to the ground input on the panel.
5.4. Applying Faults to the System
Figure 19 shows the fault logic developed in RSCAD for the system. ‘SW1’, ‘SW2’, and ‘SW3’ were the switch elements in RSCAD, which denoted phases of the system. Each switch needed to be turned on to introduce the fault on the corresponding phase. For example, to apply a three-phase fault, all three switches must be turned on. Each fault type in RSCAD was assigned a binary value, which had a corresponding decimal value, as shown in
Table 4. The three switches shown in
Figure 19 were assigned a decimal value of 1, 2, and 4, respectively. The switch positions shown in
Figure 19 indicate that a three-phase fault were introduced in the system. Alternatively, a three-phase fault can also be introduced by using a single switch having a decimal value of 7.
The fault can be applied to the system using the push button titled ‘ApplyFLT’ as shown in
Figure 19. The duration of the fault can be determined using a slider titled ‘FDUR’. The output of this logic system was a control signal ‘FLT’, which was provided as an input control signal to the fault block in the RSCAD model.
5.5. Circuit Breaker Logic
Figure 20 shows the circuit breaker logic, where ‘XCBR1open’ and ‘XCBR1close’ were the push buttons used to open and close the circuit breaker contacts, respectively. The initial status of the breaker was ‘closed’, which was assigned a logical input of 1. ‘OUT101’ was the trip signal coming from relay R1. The first OR-gate was assigned for opening the circuit breaker and, hence, had two inputs, which were ‘XCBR1open’ and ‘OUT101’. The output of the first OR-gate served as the input
to the S-R flip flop. The second OR-gate was assigned for closing circuit breaker contacts. Since this experiment was not concerned with the reclosing of the circuit breaker after the occurrence of a fault, the control signal ‘PROTIED_Reclose_R1’ was assigned a zero value. The output of the second OR-gate served as the second input
to the flip flop. The output (Q) of the flip flop passed through a timer block, which determined the duration of the operation of the circuit braker. The final output of the circuit breaker logic for relay R1, i.e., ‘BRK_R1’, was provided as an input to the circuit breaker element assigned for R1 in the model. Similar logic was used for relay R2 with its corresponding trip signal and breaker signal.
7. Conclusions
Hardware-in-the-Loop (HIL) testing plays an increasingly critical role in system design and deployment. There is a lack of literature for providing guidance on how HIL tests can be setup including the connection of various HIL platform components, external power amplifiers, and the equipment under test and how critical parameters, such as scaling factors are calculated.
This paper presents the Hardware-in-the-Loop (HIL) testing done for a five-bus system. This paper thoroughly illustrates the procedure and steps for performing HIL test using RTDS platform, Omicron amplifiers, and SEL 351 protective relays as examples. Different tripping schemes including the Instantaneous overcurrent, Definite time, and Inverse Definite Minimum Time (IDMT) scheme have been implemented. The test results obtained by the testing platform RTDS and those recorded by the relays are compared, and the comparison confirms that the experiments are correct, and the testing platform and setup are suitable for testing protective relays. It is expected that the test setup is generally suitable for testing other equipment, such as power inverters, controllers, and machines, and such transients-based testing provides a realistic environment to better de-sign and test the equipment under test.
The procedure and framework presented in this paper will be useful for designing HIL experiments for research, education, and training purposes. In particular, the paper will provide guidance not only for students at universities, but also for professional engineers that intend to adopt and implement HIL tests.