A Triple Boost Seven-Level Common Ground Transformerless Inverter Topology for Grid-Connected Photovoltaic Applications

Abstract

This article proposes a single-stage, seven-level (7L), switched-capacitor-based grid-connected inverter architecture with a common ground feature. This topology has the ability to boost the output voltage up to three times the input voltage. The proposed topology can diminish the leakage current in grid-connected photovoltaic (GC-PV) applications, and its capacitor voltages are self-balanced without any additional control strategies. The different operating modes are described in detail with their related mathematical expressions. The design of passive components and a detailed power loss analysis are presented. The merits of the proposed structure are demonstrated using a detailed comparative assessment. The grid-connected operation of the proposed inverter structure is simulated in the MATLAB/Simulink environment, and the results are presented. The laboratory prototype of 935 W is built and analyzed to validate the performance of the proposed structure.

1. Introduction

The multilevel inverters are well matured and developed technology for various applications [1,2,3,4]. In recent years, transformerless (TL) inverters have replaced transformers in GC-PV systems due to their decreased cost, smaller size, and improved efficiency [5]. The removal of transformers, however, results in leakage current flow, which causes several issues, such as increased current harmonic distortion, personal safety, power quality, and electromagnetic interferences [6]. Additionally, in PV energy applications, the input voltage needs to be boosted, which gets rid of the front-end boost converter and makes the whole system more efficient. Thus, extensive research efforts have been carried out in recent years to develop TL inverter topologies with the inherent voltage-boosting ability and to eliminate the leakage current in photovoltaic applications [7]. Many TL inverter topologies have been proposed, such as the mid-point clamping method and decoupling (DC and AC) methods. However, they cannot eliminate the leakage current and can also not boost the input voltage [8,9]. A neutral point clamp-based quasi-Z-Source T-Type inverter using eight switches, four inductors, four capacitors, and four diodes was presented in [10]. This topology requires EMI filters to minimize high-frequency variation in CMV, increasing the cost of the inverter. Additionally, it requires a high number of power components to generate a five-level AC output voltage waveform with unity voltage gain. In [11], switched-boost inverter (SBI) topologies are proposed. It uses only half of the passive components compared to impedance-source inverters. However, the high voltage stress on the capacitor and lower boost factor than the impedance source topologies are the demerits of the SBI topologies. In [12], the quasi-switched-boost inverter (qSBI)-type topology was presented. When comparing the qSBI with qZSI, the capacitance of qZSI is fourfold that of qSBI, and the DC-link boost factor of qSBI is higher than that of qZSI. However, the high common-mode voltage generation in qSBI topologies makes them unsuitable for transformerless PV applications [13]. The common ground (CG)-type TL inverter topologies effectively eliminate the leakage current in GC-PV systems [14,15]. Here, the neutrality of the grid and negative terminal of the input PV source are connected to a common ground, as shown in Figure 1. In addition to leakage current elimination, the other aim, i.e., voltage boosting ability in transformerless inverter topology, is achieved by incorporating switched capacitors (SCs) into its structure. In [16], a family of flying capacitor-based CG-TL (type-I, type-II, and Type-III) inverter topologies are presented. Here, the maximum number of output voltage levels is three, and the maximum output voltage is equal to the input voltage. The topology [17] proposes a charge pump concept in the transformerless inverter. Since the negative output voltage level solely depends on this charge pump circuit, that may result in a requirement of the DC to offset compensation. CG-TL inverter topology based on a flying capacitor is presented in [18] to eliminate leakage current. It generates a five-level (5L) output voltage with unity voltage gain using six switches, one diode, and two capacitors. Here, to balance their capacitor voltages, their design needs to employ additional control approaches.

The author of [18] proposed another 5L CG-TL inverter topology [19] that uses seven switches and three capacitors. However, the voltage gain is still one, requiring additional sensors for their capacitor voltage balancing, which increases the cost. The topology proposed in [20] can eliminate leakage current but does not increase output voltage; additionally, like topologies [18,19], this requires voltage sensors to balance their capacitor voltage, which increases the cost. The topology suggested in [21] uses two capacitors, one of which is a switched capacitor and the other is a flying capacitor. Here, a small inductor is inserted in the capacitor charging loop; thereby, reducing the inrush current. Even though the topologies presented in [16,17,18,19,20,21] effectively eliminate leakage current due to their CG-type structure, they fail to boost the output voltage. In recent years, various topologies [22,23,24,25,26,27] with boosting ability have been proposed to address this shortcoming. Although the topology [22] can increase the voltage up to twice the input voltage, it suffers from high-current stresses on the semiconductor devices and necessitates high-rated capacitors. In [23], a dual boost CG-type inverter topology with soft charging is presented. This reduces the charging current ripples across the capacitors. The topologies [24,25,26,27] are similar and generate double voltage boosting at the inverter output terminals. The above topologies require either one of the capacitor voltages to be rated twice that of the input voltage. In topologies [24,25], the maximum blocking voltage (MBV) across four switches is double the source voltage, while three switches have an MBV of twice the input voltage [26,27]. Recently, CG-TL topologies with integrated boost cells have been proposed [28,29,30]. In these topologies, dynamic voltage boosting is achieved by varying the duty cycle of the integrated boost cell switch. The topology [28] uses seven switches, two diodes, and three capacitors to achieve a 5L output voltage. Since the duty cycle of the integrated boost cell switch is kept at 50%, the boosting factor of this topology is 4. Here, each of the three switched capacitors has to be rated at twice the input voltage, and the maximum blocking voltage of the semiconductor switch is four times the source voltage. Similar to topology [28], the topology presented in [29] also generates 5L output voltage at the cost of an increased number of semiconductor devices. In this case, the main cons are the maximum blocking voltage and the rating of switched capacitors. Another 5L CG-TL structure with an integrated boost cell is proposed in [30]. Here, keeping the duty cycle of the integrated boost cell switch at 50% yields a voltage gain of 2, which is equivalent to 4 in topologies [28,29]. Additionally, five of the eight power semiconductor switches have a voltage stress equal to the boosted output voltage, and the voltage stress on the capacitors is uneven. The CG-TL inverter topologies presented in [31,32] generate a 9L waveform with a voltage gain of 2. Here, also, the voltage stress on the utilized capacitors is uneven. Another 9L CG-type topology is proposed in [33]. This topology is capable of a voltage boosting of 4. The drawbacks of this topology are higher switch voltage stress and uneven voltage stress on the utilized capacitors. To overcome the shortcomings of the voltage boosting ability, the higher voltage stress on switches, and the uneven voltage stress on capacitors, this article is proposing the following key features:

(i).

Single-phase single-stage 7L CG-type inverter that can diminish the leakage current.

(ii).

The voltage gain is 3.

(iii).

The voltage stress of capacitors is even, i.e., equal to the input voltage, Vin.

(iv).

The MBV is equal to 2/3 of the output voltage.

(v).

Capacitors are self-balanced.

(vi).

The proposed topology is capable of reactive power support.

2. Proposed 7LCG-TL Inverter

2.1. Description of 7LCG-TL Inverter

Figure 2 depicts the proposed 7LCG-TL inverter topology. The proposed structure utilizes eleven unidirectional power semiconductor switches (S₁–S₁₁), three diodes (D₁–D₃), and three switched capacitors (C₁–C₃) to generate 7L output voltage with levels of +3V_in, +2V_in, +V_in, 0, −V_in, −2V_in, and −3V_in. When switch S₁ is ON, and S₂ is OFF, the parallel connection of the source and SC-C₁ charges the capacitor to the input voltage V_in. Similarly, the other two SCs C₂ and C₃ are also charged up to the input voltage V_in when they are connected in parallel with the source. Since the proposed topology integrates the utility grid and photovoltaic system, the PV panel is considered the source of the inverter.

2.2. Description of Modes of Operation

As per the switching sequence given in

Table 1. Switching sequence.

Level	Status of Switches											Status of Capacitors			Output Voltage
	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11	C1	C2	C3
+3	1	0	1	0	1	0	0	1	0	1	0	C	D	D	+3Vin
+2	1	0	1	0	1	0	1	0	0	1	0	C	D	-	+2Vin
+1	1	0	1	1	0	0	1	0	1	1	0	C	C	C	+1Vin
0	1	0	1	1	0	0	1	0	1	0	1	C	C	C	0
−1	1	0	0	1	0	1	1	0	0	0	1	C	D	-	−Vin
−2	0	1	0	1	0	1	0	0	1	0	1	D	-	D	−2Vin
−3	0	1	0	1	0	1	0	1	0	0	1	D	D	D	−3Vin

, all seven levels of the 7LCG-TL with its conductive path are shown in Figure 3a–g. The values ‘0’ and ‘1’ in Table 1, represent the OFF and ON states of corresponding switches. The charging path of the capacitor C₁ is represented by the purple dotted line and the other two capacitors C₂ and C₃ are represented by the green dotted line. The functioning of various operating modes of the proposed topology is described as follows:

2.2.1. Maximum Positive Output Voltage Level (+3V_in)

Figure 3a depicts the proposed inverter’s maximum output voltage level. Here, the SC-C₁ is in parallel with the source via the switch S₁ and diode D₃ and is, therefore, charged to V_in. During this mode of operation, the source voltage V_in is connected in series with the capacitors C₁ and C₂ to generate a maximum output voltage of +3V_in.

This can be achieved by turning on the switches S₁, S₃, S₅, S₈, and S₁₀. The mathematical expression for output voltage is written as

$$V_o=V_{in}+V_{C_2}+V_{C_3}=3V_{in}$$

(1)

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_3}=i_{S_5}=i_{S_8}=i_{S_{10}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\\ i_{S_1}=i_{in}=I_{char,C_1}+i_{gd}(t)\end{array}$$

(2)

where $i_{gd}(t)$$I_{g,pk}$ are the grid current and its peak value, and $I_{char,C_1}$ is the capacitor C₁ charging current.

2.2.2. Second Positive Output Voltage Level (+2V_in)

This mode of operation is obtained using the series connection between the input and the capacitor C₂ voltage. The switches S₁, S₃, S₅, S₇, and S₁₀ are turned ON as shown in Figure 3b. The inverter’s output voltage is mathematically written as

$$V_o=V_{in}+V_{C_2}=2V_{in}$$

(3)

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_3}=i_{S_5}=i_{S_7}=i_{S_{10}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\\ i_{S_1}=i_{in}=I_{char,C_1}+i_{gd}(t)\end{array}$$

(4)

2.2.3. First Positive Output Voltage Level (+V_in)

The equivalent circuit to generate the first positive output voltage level is shown in Figure 3c. This level is achieved by triggering ON the switches S₁, S₃, and S₁₀. Additionally, the switches S₄, S₇, and S₉ are triggered ON to charge the capacitors C₂ and C₃. The mathematical expression for the output voltage is

$$\begin{array}{l}{V}_o=V_{in}\\ V_{C_2}=V_{C_3}=V_{in}\end{array}$$

(5)

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_3}=i_{S_5}=i_{S_7}=i_{S_{10}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\\ i_{S_1}=i_{in}=I_{char,C_1}+i_1\\ i_1=I_{char,C_2}+I_{char,C_3}+i_{gd}(t)\\ i_7=I_{char,C_2};i_9=I_{char,C_3}\end{array}$$

(6)

2.2.4. Zero Output Voltage Level (0)

In this mode of operation, the zero-output voltage is obtained by turning ON the switches S₄ and S₁₁ as shown in Figure 3d. Additionally, switches S₁, S₃, S₇, and S₉ are triggered ON to charge the three SCs.

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_{{}_{11}}}=i_{gd}(t)=I_{g,pk}\sin (\omega t)\\ i_{S_1}=i_{in}=I_{char,C_1}+i_1\\ i_1=I_{char,C_2}+I_{char,C_3}\\ i_7=I_{char,C_2};i_9=I_{char,C_3}\end{array}$$

(7)

2.2.5. First Negative Output Voltage Level (−V_in)

Figure 3e illustrates this mode of operation. The capacitor C₂ is discharged to generate this first negative output voltage by switching ON the switches S₄, S₆, S₇, and S₁₁. The SC-C₁ is charged through switch S₁, whereas the capacitor C₃ is bypassed from the circuit. Here, the inverter output voltage equation is

$$V_o=-V_{C_2}=-V_{in}$$

(8)

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_4}=i_{S_6}=i_{S_7}=i_{S_{11}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\\ i_{S_1}=i_{in}=I_{char,C_1}\end{array}$$

(9)

2.2.6. Second Negative Output Voltage Level (−2V_in)

The current flow path for this mode of operation is illustrated in Figure 3f. The capacitors C₁ and C₃ are connected in series through the switches S₂, S₄, S₆, S₉, and S₁₁, and the inverter output voltage equation is written as

$$V_o=-(V_{C_1}+V_{C_3})=-2V_{in}$$

(10)

The current stress of the switches is written as

$$\begin{array}{l}{i}_{S_2}=i_{S_4}=i_{S_6}=i_{S_9}=i_{S_{11}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\end{array}$$

(11)

2.2.7. Maximum Negative Output Voltage Level (−3V_in)

The negative maximum voltage level of the proposed structure is obtained, as depicted in Figure 3g. Here, the capacitors C₁, C₃, and C₃ are connected in series to supply power to the grid. This can be achieved by the on-state switches S₂, S₄, S₆, S₈, and S₁₁. The output voltage equation is expressed as follows:

$$V_o=-(V_{C_1}+V_{C_2}+V_{C_3})=-3V_{in}$$

(12)

The current stress equations of the switches are expressed as

$$\begin{array}{l}{i}_{S_2}=i_{S_4}=i_{S_6}=i_{S_8}=i_{S_{11}}=i_{gd}(t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\end{array}$$

(13)

The voltage stress of all switches during different operating modes is summarized and presented in

Table 2. Voltage stress of switches.

Voltage Level	Voltage Stress of Switches
	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11
+3	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	$2{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	$2{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$
+2	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$
+1	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$
0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0
−1	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0
−2	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0
−3	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	$2{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0	${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	$2{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$	0

. From the working of the proposed structure and Table 2, the MBV and total standing voltage per unit (TSV_p.u.) can be obtained as

$$MBV=2V_{in}$$

(14)

$$TS{V}_{p.u.}=\frac{{\displaystyle \sum _{x=1}^{11}{V}_{sx}}}{V_{o,mx}}=5$$

(15)

2.3. Common Mode Analysis

The common-mode behavior of the proposed topology is analyzed using a generalized common-mode circuit [6], as shown in Figure 4a. Concerning the voltage between the output terminals x and y and a common reference N, as shown in Figure 4a, the common mode voltage of the converter is expressed as [19]

$$V_{CM}=\frac{V_{xN}+V_{yN}}{2}+\left(V_{xN}-V_{yN}\right)\left(\frac{L_n-L_m}{2(L_n+L_m)}\right)$$

(16)

where x and y represent the output terminals of the inverter and N is the common reference. As can be seen from Figure 4b, the negative terminal of the proposed topology is directly connected to the neutral of the grid resulting in V_yN = 0. Additionally, there is only one output inductor, i.e., L_n = 0, as shown in Figure 4b. By assuming the low ground impedance Z_g, the parasitic capacitance C_PV from the PV side to the earth is connected by the common AC and DC ground. By substituting V_yN = 0 and L_n = 0 in (16), the common voltage V_CM synthesized by the inverter is obtained as follows

$$V_{CM}=\frac{V_{xN}-V_{xN}}{2}=0$$

(17)

It is clear from (17) that the suggested topology produces a constant zero common-mode voltage and does not exhibit any high-frequency component; the inverter practically ensures the suppression of the ground current.

3. Calculation of Duty Cycle of Switches

Figure 5 shows the 7L inverter output voltage (V_o) along with the grid-voltage (V_g) waveform. It can be seen that there are six operating zones (Zone-I to Zone-VI). The control method [25] of the proposed topology is obtained based on Figure 3. By applying the inductor volt-second balanced (V-S B) principle for the output inductor over one full operating time period (T_s), the duty cycle of the switches in different operating zones can be calculated. The grid voltage and grid current equations can be written as

$$\begin{array}{l}{v}_g(t)=V_{g,pk}\sin (\omega t)\\ i_{gd}(t)=I_{g,pk}\sin (\omega t)\end{array}$$

(18)

where $V_{g,pk},\mathrm{and}{I}_{g,pk}$ represent the peak value of grid voltage and current.

3.1. Zone-I

As seen in Figure 5, the output voltage varies between 0 and V_in during Zone-I. By using the (V-S B) law for inductor $L_f$, the duty cycle (d₁) for the operating zone-I can be calculated as (19) and (20):

$${\displaystyle \underset{0}{\overset{d_1{T}_s}{\int }}(V_{in}-v_g)}dt+{\displaystyle \underset{d_1{T}_s}{\overset{T_s}{\int }}(-v_g)}dt=0;0\le t\le t_1$$

(19)

$$d_1(t)=\frac{v_g}{V_{in}}=\frac{V_{g,pk}\sin (\omega t)}{V_{in}};0\le t\le t_1$$

(20)

3.2. Zone-II

As seen in Figure 5, during the time interval $t_1\mathrm{to}{t}_2\mathrm{and}{t}_3\mathrm{to}{t}_4$, i.e., Zone-II, the inverter’s output voltage varies between V_in and 2V_in. By using the (V-S B) law for inductor $L_f$, the duty cycle (d₂) for the operating zone-II can be calculated as (21) and (22):

$${\displaystyle \underset{0}{\overset{d_2{T}_s}{\int }}(2V_{in}-v_g)}dt+{\displaystyle \underset{d_2{T}_s}{\overset{T_s}{\int }}(V_{in}-v_g)}dt=0;t_1\le t\le t_2$$

(21)

$$d_2(t)=\frac{v_g}{V_{in}}-1=d_1(t)-1=\frac{V_{g,pk}\sin (\omega t)}{V_{in}}-1;t_1\le t\le t_2$$

(22)

3.3. Zone-III

It is observed from Figure 5 that, during the interval $t_2\mathrm{to}{t}_3$, i.e., Zone-III, the output voltage of the inverter varies in between 2V_in and 3V_in. By using the (V-S B) law for inductor $L_f$, the duty cycle (d₃) for the operating zone-III can be calculated as (23) and (24):

$${\displaystyle \underset{0}{\overset{d_3{T}_s}{\int }}(3V_{in}-v_g)}dt+{\displaystyle \underset{d_3{T}_s}{\overset{T_s}{\int }}(2V_{in}-v_g)}dt=0;t_2\le t\le t_3$$

(23)

$$d_3(t)=\frac{v_g}{V_{in}}-2=d_1(t)-2=\frac{V_{g,pk}\sin (\omega t)}{V_{in}}-2;t_2\le t\le t_3$$

(24)

4. Design of Passive Elements

To obtain the value of the output inductor filter $L_f$ based on the current flowing through the filter inductor $i_L{}_f(t)$, the output inductor current ripple is written as

$$\begin{array}{ll}∆i_{Lf}& =i_{Lf}(t=d_3{T}_s)-i_{Lf}(0)\\ & =\frac{\left(3V_{in}-v_g\right)d_3}{L_f{f}_s}\end{array};t_2\le t\le t_3$$

(25)

From Equations (24) and (25):

$$L_f=\frac{1}{∆i_{Lf}{f}_s}\left(5V_{g,pk}\sin (\omega t)-6V_{in}-\frac{V^2{}_{g,pk}{\sin }^2(\omega t)}{V_{in}}\right)$$

(26)

The inductor current ripple is maximum when the grid voltage is at its peak value, and, thus, the respective $L_f$ value can be calculated as

$$L_f=\frac{1}{∆i_{Lf,mx}\times f_s}\left(5V_{g,pk}-6V_{in}-\frac{V^2{}_{g,pk}}{V_{in}}\right)$$

(27)

The required values of the utilized capacitors C₁, C₂, and C₃ are calculated based on their longest discharge duration (LDC) over one full cycle. Figure 3a–g and Figure 4 show that the LDC of the capacitors C₁ and C₃ is between $t_5\mathrm{and}{t}_8$, and C₂ is between $t_1\mathrm{and}{t}_4$. Thus, the charge on capacitors C₁, C₂, and C₃ during their LDC time can be written as

$$\begin{array}{l}{Q}_{C_2}={\displaystyle \underset{t_1}{\overset{t_4}{\int }}{I}_{g,pk}\sin (\omega t)}\\ Q_{C_1}=Q_{C_3}={\displaystyle \underset{t_5}{\overset{t_8}{\int }}{I}_{g,pk}\sin (\omega t)}={\displaystyle \underset{t_1}{\overset{t_4}{\int }}{I}_{g,pk}\sin (\omega t)}\end{array}$$

(28)

$$Q_C=Q_{C_1}=Q_{C_2}=Q_{C_3}=\frac{I_{g,pk}}{\omega }\times \left(\cos (\omega t_1)-\cos (\omega t_4)\right)$$

(29)

$$Q_{C_x}=C_x\times ∆V_{C_x}$$

(30)

$$C=C_1=C_2=C_3=\frac{Q_C}{∆V_C}=\frac{I_{g,pk}}{\omega \times ∆V_C}\times \left(\cos (\omega t_1)-\cos (\omega t_4)\right)$$

(31)

where $∆V_C$ is the maximum voltage ripple of capacitors.

5. Power Loss Analysis

This section discusses the proposed topology’s conduction and switching power losses [34]. This aim is achieved using the current grid value $I_{oi}$ during its ith voltage level. Based on this, the RMS value of the grid current $\left(I_{o1}\right)$ in the first voltage level (Zone-I) is calculated as

$$\begin{array}{ll}{I}_{o1}& =\sqrt{\frac{1}{\omega t_1}{\displaystyle \underset{0}{\overset{\omega t_1}{\int }}{I}_{g,pk}^2{\sin }^2(\omega t)}d(\omega t)}\\ & =I_{g,pk}\sqrt{\frac{2\omega t_1-\sin (2\omega t_1)}{4\omega t_1}}\end{array}$$

(32)

Additionally, the RMS value of the grid current $\left(I_{o2,}{I}_{o3}\right)$ in the second and third voltage levels (Zone-II and Zone-III) is calculated as

$$\begin{array}{ll}{I}_{o2}& =\sqrt{\frac{1}{\omega t_2-\omega t_1}{\displaystyle \underset{\omega t_1}{\overset{\omega t_2}{\int }}{I}_{g,pk}^2{\sin }^2(\omega t)}d(\omega t)}\\ & =I_{g,pk}\sqrt{\frac{1}{\omega t_2-\omega t_1}\times \left(\frac{1}{2}\left(\omega t_2-\omega t_1\right)\right)+\left(\frac{1}{4}\left(\sin (2\omega t_2)-\sin (2\omega t_1)\right)\right)}\end{array}$$

(33)

$$\begin{array}{ll}{I}_{o3}& =\sqrt{\frac{1}{\pi -\omega t_2-\omega t_2}{\displaystyle \underset{\omega t_2}{\overset{\pi -\omega t_2}{\int }}{I}_{g,pk}^2{\sin }^2(\omega t)}d(\omega t)}\\ & =I_{g,pk}\sqrt{\frac{1}{\pi -2\omega t_2}\times \left(\frac{\pi -2\omega t_2+\sin (2\omega t_2)}{2}\right)}\end{array}$$

(34)

where $t_1=\frac{1}{\omega }{\sin }^{-1}\left[\frac{V_{in}}{v_{g,pk}}\right]\mathrm{and}{t}_2=\frac{1}{\omega }{\sin }^{-1}\left[\frac{2V_{in}}{v_{g,pk}}\right]$.

5.1. During the Time Interval $(0,\omega t_1)$

The power loss of switch S₁₀ can be calculated as follows:

$$i_{S_{10}\to (0,\omega t_1)}=\left\{\begin{array}{ll}{I}_{o1};& 0\le t\le d_1{T}_s\\ 0;& d_1{T}_s\le t\le 0\end{array}\right.$$

(35)

From Equation (35), the RMS value of the switch current $i_{S_{10},RMS}$ is calculated as

$$i_{S_{10}{,}_{RMS}}=I_{o1}\sqrt{\frac{\omega t_1\times d_1}{\pi }}$$

(36)

By using the above Equation (34), the conduction loss $\left(P_{CL}{{}_{,}}_{S_{10}}\right)$ and switching loss $\left(P_{SW}{{}_{,}}_{S_{10}}\right)$ of the switch $S_{10}$ is calculated as follows:

$$P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(0,\omega t_1)}=R_{n-}{}_{S_{10}}\times i_{S_{10}{,}_{RMS\to }{}_{(0,\omega t_1)}}^2=R_{n-}{}_{S_{10}}\times I_{o1}^2\frac{\omega t_1\times d_1}{\pi }$$

(37)

$$P_{SW}{{}_{,}}_{S_{10}}{{}_{\to }}_{(0,\omega t_1)}=\frac{1}{6}{V}_{S_{10}}\times I_{S_{10}}\times \left[t_{on}+t_{off}\right]\times \left[2N_{SW1}\times f_g\right]$$

(38)

5.2. During the Time Interval $(\omega t_1,\omega t_2)$

As the switch $S_{10}$ remains ON throughout this time interval, no switching losses are incurred; therefore, only conduction losses are present. Here, the current equation $i_{S_{10}\to (\omega t,\omega t_2)}$ is written as

$$i_{S_{10}\to (\omega t_1,\omega t_2)}=\left\{\begin{array}{ll}{I}_{o2};& 0\le t\le d_2{T}_s\\ I_{o2};& d_2{T}_s\le t\le d_2\end{array}\right.$$

(39)

From Equation (35), the RMS value of the switch current $i_{S_{10},RMS}$ in this time interval is calculated as

$$i_{S_{10}{,}_{RMS}}=I_{o2}\sqrt{\frac{\omega t_2-\omega t_1}{\pi }}$$

(40)

By using the above Equation (37), the conduction loss $\left(P_{CL}{{}_{,}}_{S_{10}}\right)$ of the switch $S_{10}$ in this interval is calculated as follows:

$$P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(\omega t_1,\omega t_2)}=R_{n-}{}_{S_{10}}\times i_{S_{10}{,}_{RMS\to }{}_{(\omega t_1,\omega t_2)}}^2=R_{n-}{}_{S_{10}}\times I_{o2}^2\frac{\left(\omega t_2-\omega t_1\right)}{\pi }$$

(41)

5.3. During the Time Interval $(\omega t_2,\frac{\pi }{2})$

As the switch $S_{10}$ continues to operate, i.e., ON during this time interval, no switching losses are incurred; therefore, only conduction losses are present. Here, the current equation $i_{S_{10}\to (\omega t,\frac{\pi }{2})}$ is written as

$$i_{S_{10}\to (\omega t,\frac{\pi }{2})}=\left\{\begin{array}{ll}{I}_{o3};& 0\le t\le d_3{T}_s\\ I_{o3};& d_3{T}_s\le t\le d_3\end{array}\right.$$

(42)

From Equation (35), the RMS value of the switch current $i_{S_{10},RMS}$ in this time interval is calculated as

$$i_{S_{10}{,}_{RMS}}=I_{o2}\sqrt{\frac{\pi -2\omega t_2}{2\pi }}$$

(43)

By using the above Equation (43), the conduction loss $\left(P_{CL}{}_{,S_{10}}\right)$ of the switch $S_{10}$ in this interval is calculated as follows:

$$P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(\omega t_2,\pi /2)}=R_{n-}{}_{S_{10}}\times i_{S_{10}{,}_{RMS\to }{}_{\left(\omega t_2,\pi /2\right)}}^2=R_{n-}{}_{S_{10}}\times I_{o3}^2\frac{\left(\pi -2\omega t_2\right)}{2\pi }$$

(44)

The total power loss of the switch $S_{10}$ is obtained as (35)–(44):

$$P_S{}_{{}_{10}}=P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(0,\omega t_1)}+P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(\omega t_1,\omega t_2)}+P_{CL}{{}_{,}}_{S_{10}}{{}_{\to }}_{(\omega t_2,\pi /2)}+P_{SW}{{}_{,}}_{S_{10}}{{}_{\to }}_{(0,\omega t_1)}$$

(45)

In the same way, the conduction and switching losses of the remaining semiconductor switches and diodes can be calculated. Using thermal modeling in PLECS/MATLAB-based simulation software, the power loss distribution of the employed semiconductor devices for various operating powers is calculated and shown in

Table 3. The power loss of semiconductor devices of the proposed topology.

Output Power (W)	PS1	PS2	PS3	PS4	PS5	PS6	PS7	PS8	PS9	PS10	PS11	PD1	PD2	PD3
545	1.300	0.280	1.785	1.794	0.193	0.229	0.601	0.249	0.599	0.300	0.194	1.565	1.883	1.027
625	1.881	0.380	2.724	2.727	0.274	0.315	0.895	0.352	0.895	0.393	0.274	2.484	2.944	1.460
780	2.669	0.558	4.026	3.996	0.382	0.447	1.281	0.484	1.281	0.585	0.379	3.170	3.689	2.054
935	3.728	0.815	5.754	5.662	0.530	0.635	1.795	0.663	1.792	0.870	0.522	4.340	5.045	2.850

. The switch model IKW30N60DTP and a constant ambient temperature of 25 °C with a uniform temperature distribution across the heatsink were used to calculate the power losses. Figure 6 depicts the bar chart of the power loss distribution percentage of the semiconductors in the proposed topology at rated power. It can be seen that the power loss of switches S₃ and S₄ in the capacitor charging path is higher due to their parallel path with the source.

6. Result and Discussion

6.1. Simulation Results

The proposed structure is simulated using MATLAB/Simulink environment, and the performance is verified. Here, the input voltage of 125 V is connected into a 220 V (RMS) and 50 Hz grid power system. The proposed inverter generates a seven-level output voltage waveform of 375 V in steps of 125 V, as shown in Figure 7. Additionally, it verifies the boosting ability of the proposed structure. All voltage waveforms in the simulation results are scaled down by 0.1. The performance of 7LCG-TL under grid-connected mode is seen in Figure 7a. It is seen that the maximum value of the injected grid current is 4 A, and the corresponding injected power is 625 W at the unity power factor. When the magnitude of reference current (i_ref) is changed, a variation of grid current is seen from 3 A to 6 A as shown in Figure 7b. At this unity power factor operating condition, the respective injected power to the grid is 465 W to 935 W. Similarly, the results of a step change in the reactive power mode are illustrated in Figure 7b. It is noticed that, while changing the magnitude of the reference current, the injected power varies from 625 VA to 935 VA. Furthermore, to test the proposed inverter’s performance under varying input voltage conditions, the input voltage is varied from 105 V to 125 V. The respective inverter output voltage, grid voltage, and grid current waveforms at 935 W unity power factor are shown in Figure 8b–d. The inverter output voltage and grid voltage waveforms are scaled down by 0.1. From Figure 8b, it is observed that the inverter output voltage changes from 315 V to 375 V while changing the input from 105 V to 125 V. However, the grid voltage and current remain the same for the 935 W unity power factor. The leakage current suppression capability of the proposed 7LCG-TL topology is tested at 935 W injected power as shown in Figure 9. Here, a 75-nF capacitor has been utilized to figure out the effect of C_PV and the obtained maximum RMS value of leakage current (i_leak) is around 8.5 mA.

6.2. Experimental Results

The performance of the proposed topology is validated experimentally using a 935 W laboratory setup. The details of the components and their specifications used for the laboratory prototype are given in

Table 4. Experimental specifications.

Device	Specification
IGBT switches	SKM75GB063D, 600 V/75 A
Capacitors C1, C2, and C3	SAMWHA HK, 1000 uF/450 V
Diodes D1, D2, and D3	RHRG3060-F085, 600 V/30 A
Inductor Lf	Ferrite core, 2.6 mH
Gate Driver	TLP250-IC
Digital Controller	TMS320F28379D
Input Voltage (Vin)	125 V
Output Voltage (Vo)	375 V
Output power (W)	935 W
Grid Voltage	220 V (RMS)
Switching Frequency	20 kHz
Local Grid Frequency	50 Hz

. Here, an input voltage of 125 V is applied to generate a seven-level peak output voltage of magnitude 375 V. Figure 10 shows the waveforms of the seven-level inverter output voltage, the gird-voltage, and the injected grid-current. It can be seen that the peak value of the inverter’s output voltage is 375 V and the peak value of the injected grid current is 6 A at unity power factor.

Figure 11a,b shows the voltage across capacitors C₁, C₂, and C₃ when the input is set to 125 V and when it is changed from 100 V to 125 V. From Figure 11a,b, it is clear that the capacitor voltages are well balanced at the source voltage without any extra control circuits. Furthermore, the operability of the proposed topology under different power factor conditions such as unity, leading, and lagging is verified, and the corresponding grid-voltage and injected grid-current waveforms are shown in Figure 12a–c. Figure 13a–c shows the different values of power 465 W, 700 W, and 780 W injected into the grid. The grid current value is changed from 3 A to 6 A when the step change in magnitude of reference current (i_ref) is applied, verifying the dynamic operating characteristic of the proposed structure. As seen in Figure 14, the injected grid power varies between 465 W and 935 W during these dynamic variation conditions. During experimentation, a small inductor of 40 uH is inserted in the capacitor charging loop to reduce the high inrush current. The voltage stress of power semiconductor switches is shown in Figure 15a–c. According to Figure 15a–c, the maximum voltage stress for switches S₁–S₄ and S₇–S₉ equals the source voltage, whereas switches S₅, S₆, S₁₀, and S₁₁ are subjected to double the source voltage. Figure 16 shows the efficiency graph between experimental versus simulation at a unity power factor condition. The simulation efficiency is 97.85%, with a total loss of 12 W for ~545 W of output power. However, in the experimental setup, the efficiency is ~97.18% for the unity pf, as depicted in Figure 16.

7. Comparative Study

A comprehensive comparison of the proposed structure against recent seven-level inverter structures has been performed and is provided in

Table 5. Comparative study against recent 7L topologies.

Topology	A	B	C	D	F	G	H	I	J	K	L	M	N (%)
[37]	10	8	0	3	Vin	5.3	1:1.5	1	0.67	No	Yes	No	NR
[38]	10	8	0	4	Vin	7.3	1:1.5	2	1.33	No	Yes	No	[email protected] kW
[39]	10	9	0	3	Vin	6	1:1.5	1	0.67	No	Yes	No	96@1 kW,
[35]	9	9	1	2	Vin	5.7	1:3	3	1	Yes	Yes	No	92.81@150 W
[36]	10	9	1	1	2Vin	7.33	1:3	3	1	Yes	Yes	No	96.68@210 W
[44]	12	12	0	4	Vin	5.5	1:4	4	1	No	Yes	No	97.62@200 W
[40]	12	11	4	4	0.5Vin	8	1:1.5	2	1.33	No	Yes	No	[email protected] kW
[45]	12	10	4	4	2Vin	7.3	1:3	4	1.33	No	Yes	No	94.9@500 W
[41]	10	8	0	2	0.5Vin	5.3	1:1.5	1	0.67	No	Yes	No	97.6@400 W
[42]	9	9	0	4	0.5Vin	5.3	1:1.5	1	0.67	No	Yes	No	NR
[49]	12	11	0	2	Vin	5.3	1:3	2	0.67	No	Yes	No	95@1 kW
[46]	9	9	2	3	Vin	5.7	1:3	3	1	No	Yes	No	93.1@313 W
[43]	10	8	0	4	0.5Vin	5.7	1:1.5	1	0.67	No	Yes	No	NR
[47]	8	8	4	3	2Vin	5.3	1:3	3	1	No	No	Yes	NR
[48]	10	10	0	3	Vin	6.8	1:2	2	1	No	No	Yes	NR
Proposed	11	11	3	3	Vin	5	1:3	2	0.67	No	No	Yes	96.5@935 W

A—Switch Count, B—Gate Driver Count, C—Diode Count, D—Capacitor Count, E—Maximum No. of. ON Switches, F—Maximum Capacitor Voltage Rating, G—TSV (per unit), H—Boost factor (V_in:Vo), I—MBV (×V_in), J—MBV/Maximum output voltage (should be low), K—H-Bridge, L—Leakage Current, M—CG Structure, N—Efficiency η (%), NR—Not Reported.

. The comparison is performed based on features such as the number of power semiconductor devices, total standing voltage per unit, boosting ability, maximum blocking voltage, leakage current alleviation, and efficiency. As seen from Table 5, it is clear that the topologies [35,36] use a lower number of devices than the proposed topology to generate the triple voltage gain. However, they require four higher rating switches due to the utilization of the H-bridge structure at their back-end. The topologies [37,38,39,40,41,42,43] also use lower power components than the proposed inverter, but their voltage gain is only 1.5. Additionally, the total standing voltage of the proposed structure is 5, which is the lowest value in the comparison study. The MBV of the proposed structure is 2V_in, which is the second lowest in the comparison table. Even though the proposed topology and topology [44] both have the same number of power components, [44] has a higher peak inverse voltage, so the ratio of MBV to maximum output voltage is also high. For the same seven-level triple voltage gain, the topology [45] uses a higher number of components than the proposed structure, and their TSV, MBV, and ratio of MBV to maximum output voltage are also high. The MBV and TSV of the topology [46] is higher than the proposed topology. Similar to the proposed topology, the topologies presented in [47,48] are also of the common ground-type structure where the neutral terminal of the grid is directly connected to the negative terminal of the DC source. Due to this structure, the leakage current can be alleviated. This feature is absent in all other topologies listed in Table 5. Though the topology [47] offers a common ground feature similar to the proposed topology, they use three capacitors, out of which two capacitors are of the voltage rating V_in and the rating of the third capacitor is 2V_in, whereas the proposed topology uses three capacitors of the same voltage rating V_in.

By keeping the duty cycle of the switch S₁ of the structure presented in [48] at 50%, it will generate an output voltage with a voltage gain of 2. Still, the MBV is equal to the output voltage. So, even if the duty cycle changes to increase the boosting factor, 5 out of 10 switches have to withstand voltage equal to the output voltage.

8. Conclusions

This article presents a novel 7L transformerless inverter topology with a common ground feature and voltage boosting. The common ground-type structure ensures the elimination of leakage current. The proposed topology uses three switched capacitors of the same voltage rating, i.e., equal to the input, to generate the triple boost output voltage. Additionally, the capacitors are balanced without any additional control requirements. The obtained experimental results prove that the voltages across all the switches were lower than the maximum output voltage, avoiding the use of high-voltage semiconductor devices. The ability to handle reactive power with the grid’s lagging/leading pf condition is verified from the experimental results. The RMS value of the leakage current is 8 mA for the proposed topology, which verifies its leakage current suppression capability. Furthermore, the design of passive components and power loss analysis have been presented. The outcome of a comprehensive comparison against other 7L topologies has been presented to show the merits of the proposed structure. Furthermore, to validate the performance of the proposed structure, experimental results were obtained from a 935 W laboratory prototype. Both simulation and experimental results are in good agreement, confirming the feasibility of the proposed topology. At ~935 W, 96.5% is the efficiency value while using PLECS simulation software, and 95.8% is an experimental value. Given the benefits highlighted in this study, the proposed structure is a strong candidate for grid-connected PV applications.