A Review of Non-Isolated High-Gain Y-Source Converters Topologies

Abstract

Due to the low voltage and high randomness of renewable energy, high-performance grid-connected converters are needed. With the advantages of a high boost ratio, flexible design, and simple control, the Y-Source Converter (YSC) is widely concerned. However, there are a few drawbacks to the traditional Y-source converter, including significant switching stress, voltage voltage overshoot, and discontinuous current. To solve the problems above, a series of improved topologies are proposed. Moreover, the voltage gain, current ripple, and soft switching characteristics have also been optimized. So far, the existing literature lacks the collation and comparison of different topologies of Y-source, as well as the analysis of its evolution process. Therefore, this paper provides a comprehensive overview of Y-source converters’ topologies. According to their features and applications, different topologies are classified and described, leading to guidance for the selection of YSCs under different scenarios. Meanwhile, the working principle, evolution process, and vital issues are analyzed. By revealing their deductive rules, valuable suggestions are provided for the future development of YSCs.

1. Introduction

With the increasingly serious environmental issues, the low-carbon transformation of energy has become a challenge faced by the global world. However, the renewable energy represented by photovoltaics is generally characterized by low voltage levels, intermittency, and randomness, which requires a high-performance grid-connected converter [1]. To solve the problems, Z-source network, as the earliest impedance source network, was proposed in 2002 [2], which is shown in Figure 1a. Through the introduction of passive components, a high step-up ratio is achieved, while the operational reliability is improved [3,4,5,6,7].

However, the traditional Z-Source network still has many shortcomings [8,9,10,11]. Firstly, due to the diode is directly connected to the power supply, the input current is discontinuous. To solve the problem, a quasi Z-Source network was proposed [12], which is shown in Figure 1b. By shifting L₂ to the input side to smooth the current, the continuous input current is achieved without changing the boost ratio. Moreover, the voltage stress of C₂ is reduced, which is beneficial for improving power density. On this basis, a switched inductor quasi Z-source network was proposed [13,14,15]. As shown in Figure 1c, by using a switched inductor to replace L₁, the boost ratio was further improved. However, the cost of the converter was increased as well as the flexibility of duty cycle adjustment was reduced. Compared with it, Figure 1d shows a cascaded quasi Z-Source network [16], which allows a larger range of duty cycles. Nevertheless, due to the influence of parasitic effects, its efficiency will be degraded, which limits its practical application in industrial applications.

As the bus voltage increases, the boosting capacity of Z-source cannot meet the requirements. Therefore, coupled inductors have been introduced into impedance source networks [17]. By using turn ratio as a new degree of freedom, LCCT-source [18], T-source [19], Γ-Source [20], Δ-Source [21], Y-source [22], and other new topologies are proposed, as shown in Figure 2. Their boosting capability is determined by duty ratio and turn ratio, which means that the design flexibility is improved.

In Figure 2a, with the L₁ of the Z-source network replaced by LCCT-coupled inductors, an LCCT-source impedance network was proposed [18], which was named because of its component arrangement. Its boost ratio increases with the turn ratio. Due to its connection mode of windings, the influence of parasitic parameters is not obvious. Moreover, the input current is easy to work in Discontinuous Conduction Mode (DCM), which is beneficial for the application under light load conditions. However, the design of windings is relatively complex. Compared with it, the T-source network [19], as shown in Figure 2b, is more straightforward in design. Moreover, The T-source network can also increase the boost ratio.

However, when the voltage of the bus further increases, the turn ratios of the coupled inductors cannot be kept relatively small, leading to the design difficulty. A Γ-source impedance network is proposed to address the above issues, as shown in Figure 2c [20]. Its boost ratio increases with the decrease in turn ratio, which is beneficial for reducing the volume of the coupled inductance. However, when the turn ratio approaches 1, even a tiny change will significantly impact the boost ratio, leading to higher requirements for the accuracy of the design. Otherwise, it will be challenged to maintain a stable boost ratio. To further improve the characteristics of the impedance source network, the ∆-source impedance network was proposed, as shown in Figure 2d [21]. With the three coupled inductors introduced, the influence of leakage inductance and parasitic parameters are suppressed. However, the boost ratio is only related to the two windings, which means that it does not lift the limitation of the turn ratio.

To improve the boost ratio and simplify the design of coupled inductors, the Y-source network was proposed in 2014, as shown in Figure 2e [22]. Its step-up ratio is controlled by the winding factor and duty ratio, equivalent to providing three degrees of freedom. Therefore, its design flexibility is greatly improved, and able to achieve higher voltage gain with fewer total turns. Moreover, as shown in Figure 3, Γ-Source, T-source, and LCCT-source can all be derived from Y-source. Therefore, the Y-source impedance network has more generality.

In addition, although the impedance source network was initially proposed in the form of a DC-AC inverter [23,24,25,26], it has been applied to various converters, such as [27,28,29] for AC-AC converters, [30,31,32,33] for DC-DC converters, [34] for AC-DC bidirectional converters and [35] for three-port converters. The flexibility is also reflected in the Y-source network. In this paper, a series of Y-source impedance networks will be systematically introduced, including the deduction of its basic topology, the suppression methods of voltage overshoot, and the design principles of optimized converters. Moreover, the characteristics of each topology will be analyzed and compared, which may provide inspiration for future research on Y-source converters.

2. Basic Topology of Y-Source Converters

2.1. Traditional Y-Source Converter (YSC)

As shown in Figure 4, YSC consists of two diodes (D₁ and D₂), two capacitors (C₀ and C₁), and a three-winding coupled inductor (N₁, N₂, and N₃). The coupled inductors are charged by the capacitor under the Shoot-Through (ST) state and discharge to the load together with the power supply under the Non-Shoot-Through (NST) state. Its step-up ratio is determined by the turns of the coupled inductors and the duty ratio. Due to the introduction of the coupling inductors, fewer components and the flexible turns ratio are allowed in YSCs.

When the switch S is turned on, the converter is in ST state, as shown in Figure 5a, and the magnetization voltage in the ST state v_{Lm_ST} is derived as follows:

$$\frac{N_3}{N_1}{v}_{Lm\_ST}-\frac{N_2}{N_1}{v}_{Lm\_ST}=V_{C1}\Rightarrow v_{Lm\_ST}=\frac{N_1}{N_3-N_2}{V}_{C1}$$

(1)

where N₁, N₂, and N₃ are the number of turns of the windings, V_C1 is the voltage across C₁, and V_NX is the voltage across N_X.

In the NST state, as shown in Figure 5b, according to the KVL, the magnetic voltage in the NST state v_{Lm_NST} is derived as follows:

$$v_{Lm\_NST}+\frac{N_2}{N_1}{v}_{Lm\_NST}=V_{in}-V_{C1}\Rightarrow v_{Lm\_NST}=\frac{N_1}{N_1+N_2}(V_{in}-V_{C1})$$

(2)

$$v_{Lm\_NST}+\frac{N_3}{N_1}{v}_{Lm\_NST}=V_{in}-V_o\Rightarrow v_{Lm\_NST}=\frac{N_1}{N_1+N_3}(V_{in}-V_o)$$

(3)

where V_in is the input voltage, V_o is the output voltage, and v_{Lm_NST} is the voltage of L_m in the NST state.

According to the volt-second balance of v_Lm in one switching period, the equation is as follows:

$${\displaystyle {\int }_0^{T_S}{v}_{Lm}}=0\Rightarrow d{v}_{Lm\_ST}+(1-d)v_{Lm\_NST}=0$$

(4)

Based on the above analysis, the expression for the boost ratio is as follows:

$$V_o=\frac{1}{1-Kd}{V}_{in}\Rightarrow B=\frac{V_o}{V_{in}}=\frac{1}{1-Kd}$$

(5)

K is defined as the winding factor, and its expression is as follows:

$$K=\frac{N_3+N_1}{N_3-N_2},$$

(6)

It can be seen from Equation (5) that the boost ratio is determined by the winding factor and the duty ratio. However, the duty ratio has the following restrictions:

$$1-Kd>0\Rightarrow d<\frac{1}{K}$$

(7)

The corresponding relationship among the number of turns, winding factor K, duty cycle d, and boost ratio B is shown in

Table 1. Factors influencing the YSC boost ratio.

K	dmax	B	N1:N2:N3
2	1/2	${(1-2d)}^{-1}$	(1:1:3), (2:1:4), (1:2:5)
3	1/3	${(1-3d)}^{-1}$	(1:1:2), (3:1:3), (4:2:5)
4	1/4	${(1-4d)}^{-1}$	(2:1:2), (1:2:3), (5:1:3)
5	1/5	${(1-5d)}^{-1}$	(3:1:2), (2:2:3), (1:3:4)
6	1/6	${(1-6d)}^{-1}$	(4:1:2), (3:2:3), (2:3:4)

:

It can be seen from Table 1, that although the turn ratio is different, the winding factor K is the same as the first column of Table 1. Therefore, the number of turns of the coupled inductor winding is variable, which has greater design flexibility.

Figure 6 shows the voltage gain of improved YSC with different winding factors. It can be seen that the duty cycle adjustment range of YSC is less than 0.5 when K > 2.

Table 2. Comparison of key parameters of impedance source network.

Class	Topology	B	dmax	Degrees of Freedom
Class of Z-Source	Z-Source [8]	${(1-2d)}^{-1}$	$\frac{1}{2}$	1
	qZ-Source [12]	${(1-2d)}^{-1}$	$\frac{1}{2}$	1
	SI-qZ-Source [13]	$\frac{1+d}{1-2d-d^2}$	$\sqrt{2}-1$	1
	C-qZ-Source [16]	${(1-(2+n)d)}^{-1}$	${(2+n)}^{-1}$	2
other coupled-inductance impedance Source converters	LCCT-Source [18]	${(1-(1+n_{LZ})d)}^{-1}$	${(1+n_{LZ})}^{-1}$	2
	T-Source [19]	${(1-(1+n_{TZ})d)}^{-1}$	${(1+n_{TZ})}^{-1}$	2
	Γ-Source [20]	${(1-(1+\frac{1}{n_{\mathsf{\Gamma }Z}-1})d)}^{-1}$	${(1+\frac{1}{n_{\mathsf{\Gamma }Z}-1})}^{-1}$	2
	Δ-source [21]	$\frac{1+n_{23}}{1-\left(2+n_{23}\right)d}$	${\left(2+n_{23}\right)}^{-1}$	2
Class of Y-Source	Y-Source [22]	$\frac{1}{1-Kd}$	$\frac{1}{K}$	3

shows that the Y-Source has the highest voltage gain and design flexibility among the networks mentioned above. In addition, if n₁₃ and n₃₂ of the YSC are considered as the turn ratio of the T-source and Γ-source, then the voltage gain satisfies the following relationship:

$$B_{TZ}={(1-(1+n_{13})d)}^{-1}={(1-V_{TZ}d)}^{-1}$$

(8)

$$B_{\mathsf{\Gamma }Z}={(1-(1+\frac{1}{n_{32}-1})d)}^{-1}={(1-V_{\mathsf{\Gamma }Z}d)}^{-1}$$

(9)

The expression for V_TZ and V_ΓZ are as follows:

$$V_{TZ}=(1+n_{13})$$

(10)

$$V_{\mathsf{\Gamma }Z}=(1+\frac{1}{n_{32}-1}).$$

(11)

According to Equations (8)–(11), it can be calculated as follows:

$$B_Y={\left(1-Kd\right)}^{-1}=((1-\frac{1+n_{13}}{1-n_{23}})d{)}^{-1}={(1+(1+n_{13})(1+\frac{1}{n_{32}-1}d))}^{-1}=((1+V_Y)d{)}^{-1}$$

(12)

$$V_Y=(1+n_{13})(1+\frac{1}{n_{32}-1})=V_{TZ}{V}_{\mathsf{\Gamma }Z}$$

(13)

According to Equation (13), the gain of the Y-source is a combination of T-source and Γ-source gains. Compared with them, Y-source appears to have a wider application.

2.2. Quasi Y-Source Converters (qYSCs)

Compared with other existing impedance networks, YSC has a higher gain with a small duty ratio and better design flexibility. However, the input current of the YSC is discontinuous, and the inrush current is induced when it starts up.

In response to the issue of discontinuous input current, Figure 7a shows a method to smooth the input current using an additional capacitor. However, the charging process of the capacitors will cause a large start-up pulse current. Moreover, capacitors C₁ and C₂ need to maintain a particular proportional relationship, and they are prone to resonate with the input side parasitic inductance, which increases the design difficulty.

In Figure 7b, a new method is proposed, which adds an input inductor and a capacitor to solve the discontinuity of the input current [36,37]. It can effectively suppress the pulse current, but high voltage stress for the input diode is inevitable.

On this basis, a new topology was proposed by exchanging the positions of capacitor C₂ and diode D₁, as shown in Figure 7c [38]. It can achieve continuous input current without increasing the voltage stress on its components. Moreover, a capacitor is placed to block the current flowing through the coupled inductor, which is beneficial for preventing its core from saturation. However, its boost ratio is lower than YSC.

By changing the position of the D₁ in Figure 7c, a new topology can be obtained. The Power supply charges capacitor C₁ through inductor L₁ and diode D₁ at startup. It is not until C₁ reaches a steady state that the current flows into the coupled inductors. Although this method protects the primary circuit from the impact of the inrush current, the voltage stress of the power components is still high.

Because the curves coincide, the voltage gains of the qYSCs are represented separately, as shown in Figure 8. Both qYSC-I and qYSC-IV maintain the boost ratio of traditional YSC, therefore the voltage gains of the YSC and the qYSC-I, qYSC-IV are the same as YSC, as shown in Figure 8a,d. The winding factor of qYSC-III is defined as δ = (N₁ + N₂)/(N₂ − N₃). By replacing K with δ, the boosting capacity curve of qYSC-III can be obtained, as shown in Figure 8c. In addition, qYSC-II can achieve the same boost ratio as traditional YSC with a smaller K, and its boost capability curve is shown in Figure 8b.

2.3. Modified Y-Source Converter (M-YSC)

To solve the problems of high voltage stress on switches, based on Figure 7b, a Modified Y-source converter was proposed [39]. As shown in Figure 9, the switch is moved from the output side to the input side, avoiding the impact of high voltage on the output side. According to Equation (5), the boost ratio of M-YSC can be obtained.

$$B=\frac{1+Kd}{1-d}$$

(14)

According to Equation (14), the corresponding relationship among the number of turns, winding factor K, duty cycle d, and boost ratio B is shown in

Table 3. The voltage gain of the M-YSC with different winding factor (K) and turns ratio.

K	dmax	B	N1:N2:N3
2	1	(1 + 2d)/(1 − d)	(1:1:3), (2:1:4), (1:2:5)
3	1	(1 + 3d)/(1 − d)	(1:1:2), (3:1:3), (4:2:5)
4	1	(1 + 4d)/(1 − d)	(2:1:2), (1:2:3), (5:1:3)
5	1	(1 + 5d)/(1 − d)	(3:1:2), (2:2:3), (1:3:4)
6	1	(1 + 6d)/(1 − d)	(4:1:2), (3:2:3), (2:3:4)

:

Table 3 shows that different turn ratios can obtain the same winding factor, indicating that M-YSC has high design flexibility. From Figure 10, it also can be seen that M-YSC has a wide duty cycle adjustment range. Therefore, it can achieve high voltage gain with different winding factors.

2.4. Properties Comparison among Different Impedance Source Networks

Table 4. Properties comparison among different impedance source networks.

Class	Topology	B	dmax	Continuous Input Current	Inrush Current	Inductive Volume	Switching Stress	Component Voltage Stress
								VC1, MAX /Vin	VC2, MAX /Vin	VD1, MAX /Vin	VS, MAX /Vin
Traditional Y-Source	YSC [22]	$\frac{1}{1-Kd}$	$\frac{1}{K}$	no	high	big	high	$(1-d)B$	-	$(K-1)B$	$\frac{1}{1-Kd}$
Quasi Y-source	qYSC-II [36]	$\frac{1}{1-(1+K)d}$	$\frac{1}{1+K}$	yes	low	big	high	$(1-d)B$	$KdB$	$(K-1)B$	$\frac{1}{1-(1+K)d}$
	qYSC-III [38]	$\frac{1}{1-\delta d}$	$\frac{1}{\delta }$	yes	low	small	high	$(1-d)B$	$(\delta -1)dB$	$(\delta -1)B$	$\frac{1}{1-\delta d}$
Modified Y-Source	M-YSC [39]	$\frac{1+Kd}{1-d}$	1	yes	low	big	low	$\frac{1+KB}{1+K}$	$\frac{KB-K}{1+K}$	$\frac{K^2+KB+2K}{1+Kd}$	$\frac{1}{1-d}$

Here, δ = (N₁ + N₂)/(N₂ − N₃).

shows that the voltage stress of the qYSC in Figure 7a is the same as that of the YSC in Figure 4, and its input current is continuous, which is beneficial for the application in new energy generation systems. Under the same voltage gain, the voltage stress on D₁ in Figure 7b,d is higher than that in Figure 7a,c. The qYSC in Figure 7c can block input current from flowing through the coupled inductor, but its boost ratio has decreased. Compared with the topology mentioned above, the M-YSC in Figure 9 has the widest duty cycle adjustment range and the lowest switching stress. However, it still has the problem of a large input current ripple, which needs further optimization.

In summary, both the qYSC and M-YSC achieve continuous input current, while their characteristics are different. They provided a foundation for optimizing the Y-source topology, and most of the new structures have evolved from them.

3. Effects of Leakage Inductances on Y-Source Network

3.1. The Analysis of the Effects of Leakage Inductances

The coupled inductors have been used with YSC for high boost capability and design flexibility. However, the above analysis is based on an ideal model without considering the effects of leakage inductance. In response to this issue, the traditional Y-source network is analyzed as an example in [40,41]. When the transition from ST to NST state happens, leakage inductances prevent D₁ from immediately turning off, resulting in an intermediate state, as shown in Figure 11b. During this process, its current might increase rapidly in a short time, resulting in a significant voltage overshoot appearing in the circuit, which decreases the utilization of DC voltage and limits the application of YSCs.

The voltage of coupled inductors in different states is shown in

Table 5. The voltages of coupled inductors in different states.

Mode	VL
Non-Shoot-Through state	$V_{L(NST)}=\frac{n_{12}}{n_{12}+1}(V_{in}-V_{C1})$
Intermediate state	$V_{L(INT)}=\{\begin{array}{l}{V}_{L(NST)}-\frac{n_{12}}{n_{12}+1}(V_{L1}+V_{L2})\\ V_{L(ST)}-\frac{n_{12}{n}_{13}}{n_{12}-n_{13}}(V_{L3}-V_{L2})\end{array}$
Shoot-Through state	$V_{L(ST)}=\frac{n_{12}{n}_{13}}{n_{12}-n_{13}}{V}_{C1}$

. According to [39], the expression for Δd is as follows:

$$\Delta d=|\frac{L_{N1}{I}_{in(NST)}}{V_{L1}T}|\approx |\frac{L_{N1}P}{V_{L1}{V}_{dc}(1-d)T}|$$

(15)

Due to the presence of intermediate states, the effective duty cycle is shortened to d′ = d − Δd < d. Moreover, the voltages of the inductors L_m satisfy the volt-second balance in one switching cycle. Therefore, the equation is as follows:

$$d^{\prime }{V}_{L(ST)}+\Delta d{V}_{L(INT)}+\left(1-d^{\prime }-\Delta d\right)V_{L(NST)}=0$$

(16)

According to Equation (5), the more the duty cycle decreases, the lower the voltage gain. Moreover, when the converter switches from ST to NST state, the influence is related to the types of load. If there is a capacitive load, that can rapidly absorb the changing currents, as shown in Figure 12a, it will not generate voltage overshoot. However, if there is an inductive load, the current through L_N3 will be pulled down to the load current value almost instantaneously. At this point, the rapidly changing current, which acts on the leakage inductance, will generate a high voltage overshoot, as shown in Figure 12b. The connection between the converter and the inductive load is shown in Figure 13b, which is unlike the capacitive arrangement shown in Figure 13a. By arranging the load in this way, different behaviors during the transitions between the ST and NST states can be demonstrated.

3.2. The Low-Voltage-Overshoot Y-Source Converters

To solve the problem caused by leakage inductance, scholars have proposed a series of new topologies with voltage-clamp cells. According to their structures and characteristics, they can be divided into the following classes:

3.2.1. The Voltage-Double Quasi Y-Source Converters (VD-qYSCs)

To eliminate the influence of leakage inductance, diodes D₂, and D₃ are added to the qYSC in Figure 14a. In the intermediate state, D₁, D₂, C₁, and C₂ form the clamped circuit, which limits the voltage overshoot. However, in the circuit formed by D₂, D₃, and coupled inductor, there is a significant voltage drop at the dc-link in comparison to the NST state, resulting in a sharp increase in the circuit current. To simplify the topology, As shown in Figure 14b, the capacitance C₂ and diode D₃ are reduced, while the boost ratio of the new topology has been decreased [42,43].

3.2.2. The Low-Voltage-Overshoot High-Efficiency Quasi Y-Source Converters (LH-qYSCs)

To reduce the voltage stress of the power device, a family of low-voltage-overshoot and high-efficiency converters (LH-qYSC) [44] is proposed. A clamped circuit is formed by adding a diode D₂ and a capacitor C₃, which can absorb the leakage inductance energy and improve the efficiency of the YSC. Figure 15 shows six topological structures. Among them, LH-YSC-I, II, and III are only different in the connection of capacitor C₃, while LH-qYSC-IV, V, and VI have been modified from LH-qYSI-I, II, and III. These topologies can effectively clamp the bus voltage, with only different voltage and current stress across the capacitors.

3.2.3. The Low-Voltage-Overshoot High-Step-Up Quasi Y-Source Converters (HS-qYSCs) and the Diode-Assisted Quasi Y-Source Converter (DA-qYSC)

To further improve the boost ratio of the converter, an inductor, and a capacitor were added to the clamped circuit of the LH-YSC, forming a family of low-voltage-overshoot High-Step-up Y-Source Converters (HS-qYSC). However, they are different in the selections of the basic topology, which leads to differences in their characteristics. Moreover, the position of the absorbing circuits relative to the basic topology is different, resulting in a difference in the voltage and current stress. Specifically, if capacitor C₄ in Figure 16c is replaced with a diode, a Diode-Assisted quasi Y-Source Converter (DA-qYSC) can be obtained. As shown in Figure 17, the absorbing circuits of it are identical to that of HS-YSC, so it is not discussed in detail here [45,46].

3.2.4. The Low- Voltage-Overshoot High-Step-Up Cascaded Quasi Y-Source Converters (HSC-qYSCs)

As shown in Figure 18, by cascading the absorbing circuits of the HS-YSC, two Low-voltage-overshoot High-Step-up Cascaded quasi Y-Source Converters (HSC-qYSC) can be obtained. When D_n is on, C_2n and C_2n−1 are in series across the dc-link, which clamps the bus voltage. Moreover, the two topologies have a common gain, which can be expressed as

$$B=\frac{1}{1-(1+n+K)d}$$

(17)

3.2.5. The Optimized Quasi Y-Source Converter (O-qYSC) and the Inductor-Capacitor-Diode Quasi Y-Source Converter (LCD-qYSC)

Although the above topologies have a significant effect in terms of clamping voltage overshoot, they ignore the volume of the coupled inductor. In the YSC, the minimum value of the DC magnetizing current equals the input current. Due to the high input current, the DC magnetization current is large. Therefore, a large volume of the coupled inductors is required to prevent magnetic core saturation. By adding the same absorbing circuits as HS-qYSC (or DA-qYSC) to the qYSC shown in Figure 7c, an Optimized Y-Source Converter (O-qYSC) is proposed in Figure 19a [47]. Due to the zero average magnetizing current, the windings’ current is low, reducing the volume of the coupled inductor significantly. Therefore, it is conducive to achieving higher power density. Similarly, instead of cascade technology by an Inductor-Capacitor-Diode (LCD) buffer, as shown in Figure 19b, an Inductor-Capacitor-Diode Y-Source Converter (LCD-qYSC) is proposed. It can absorb the energy of the leakage inductance without damage, but the component stress of LCD is related to the value of the leakage inductance, leading to difficulty in design [48].

3.2.6. The Active Clamped Quasi Y-Source Converters (AC-qYSCs)

In addition to the impact of voltage overshoot, the value of the ST current cannot be ignored. In the ST state, the current flowing through the circuit is proportional to the ST current. The direct current increases with the decrease of the duty cycle, increasing device stress and circuit loss [49]. To address this issue, one more winding is integrated into the input inductor magnetic core of the quasi-switched boost inverter. However, the switch experiences high voltage overshoot and the input current deteriorates. By replacing the discrete inductor with a switch-coupled inductor, a new topology structure is proposed in [50]. But it still has voltage overshoot on the DC bus. Besides, the magnetizing current of these converters is always larger than the input current, and a large coupled inductor is required.

For this reason, the AC-qYSCs are proposed in [51], which add only two diodes, a switch, and a capacitor compared to qYSC. As shown in Figure 20, these converters use D₂, D₃, and C₃ to form an absorbing circuit of the leakage inductance and clamp the bus voltage by C₃, and the volume of coupled inductors is reduced. However, due to the increasing number of switches, the control strategy of the AC-qYSCs becomes complex.

3.3. Properties Comparison among Different Y-Source Converters with the Absorbing Circuit

As can be seen from

Table 6. The key Properties Comparison among Y-source converters with the absorbing circuit.

Topology	B	ILO,MAX/Iin	IS1,MAX/Iin	IS2,MAX/Iin	Average Magnetizing Current
VD-qYSC-I [42]	$\frac{1-\delta }{1+(\delta -2)d}$	-	$\delta$	-	high
LH-qYSC-I [44]	$\frac{1}{1-(1+K)d}$	-	$\delta$	-	high
DA-qYSC [45]	$\frac{1}{1-(2+K)d+K{d}^2}$	1	$\delta$	-	high
O-qYSC [47]	$\frac{1}{1-(2+K)d}$	1	$\delta$	-	0
LCD-qYSC [48]	$\frac{1}{1-(1+K)d}$	$\frac{{V_{C3}}^{LCD}d{T}_S}{L_O}$	$\delta$	-	0
AC-qYSC-I [51]	$\frac{1}{1-2(1+K)d}$	-	$0.5\delta$	$0.5\delta$	0

and

Table 7. Other Properties Comparison among Different Y-source converters with the absorbing circuit.

Topology	VC1,MAX/Vin	VC2,MAX/Vin	VC3,MAX/Vin	VD1,MAX/Vin	VD2,MAX/Vin	VD3,MAX/Vin
VD-qYSC-I [42]	$\frac{(1-d)}{1+(\delta -2)d}$	$\frac{(d-\delta )}{1+(\delta -2)d}$	$\frac{(d-1)\delta }{1+(\delta -2)d}$	$B$	0	$\frac{\delta B}{\delta -1}$
LH-qYSC-I [44]	$(1-d)B$	$(\delta -1)dB$	$(1-(\delta -1)d)B$	$(\delta -2)B$	$B$	-
DA-qYSC [45]	$(1-2d)B$	-	$(1-d)B$	$(\delta -2)B$	$B$	$(\delta -2)dB$
O-qYSC [47]	$(1-2d)B$	$(\delta -2)dB$	$(1-d)B$	$(\delta -2)B$	$B$	-
LCD-qYSC [48]	$(1-d)B$	$(\delta -1)dB$	${V_{C3}}^{LCD}$	$(\delta -1)B$	$(1-d)B+{V_{C3}}^{LCD}$	$V_{PN}-{V_{C3}}^{LCD}$
AC-qYSC-I [51]	$(1-2d)B$	$(\delta -2)dB$	$B$	$(\delta -2)B$	$B$	$B$

Here, ${V_{C3}}^{LCD}=0.5dB+0.5\sqrt{{(DB)}^2+\frac{4L_K{L}_O{I_{N1}}^2}{{(D{T}_S{V}_{in})}^2}}$.

, the O-qYSC, and AC-qYSC have high boosting ability, while the DA-qYSC, and O-qYSC have lower voltage and current stresses. Regarding the effect of the DC magnetization current, the coupled inductors of the O-qYSC, LCD-qYSC, and AC-qYSC can be designed to be smaller, which is beneficial for obtaining higher power density. Moreover, only the AC-qYSC suppresses the ST current to 0.5δI_in, while it is δI_in for others. It indicates that with the same ST current, the value of δ of the AC-qYSC can be doubled, which provides greater design flexibility. Nevertheless, when δ is large, the ST current and voltage stress of the AC-qYSC are relatively high. Therefore, the value of δ should be appropriate.

4. The Optimization of YSCs’ Key Indicators

4.1. The Y-Source Converters Combined with Various Boosting Structures

To further improve the gain, various boosting structures are combined with the Y-source converter. The main topology structure is as follows:

4.1.1. The Y-Source Converters Combined with a Boost Converter

• The Quasi Y-Source Converters combined with a Boost Converter (CB-qYSC)

By combining the qYSC with a boost converter, an improved quasi-Y-source converter was proposed in [52], as shown in Figure 21a, which inherits all the advantages of qYSC. Moreover, a high boost radio can be realized by controlling two switches of S₁ and S₂. Nevertheless, two switches increase the converter cost, and the design of the control strategy becomes more difficult.

2.

The Modified Y-Source Converters combined with a Boost Converter (CB-M-YSC)

Based on the M-YSC, a single-switch Y-source converter is proposed in [33], as shown in Figure 21b. Due to the active switch being shared between the M-YSC and the traditional boost converter, the design of the control strategy is simpler than that of the CB-qYSC. In addition, all advantages of the M-YSC, high voltage boost, and low voltage stress, are inherited. However, the adjustment of the boost ratio is more dependent on the duty cycle, and the effect of the winding factor is weakened. Therefore, it is considered to combine the y source with different boost units to further improve the voltage gain.

4.1.2. YSC Combined with Different Step-Up Cells

• The quasi Y-Source Converter with series Inductance modules (L-qYSC)

To further improve the boost ratio of the converter, a family of new High-Step-up Y-source converters was proposed in [53], which combined the qYSC with different step-up cells, including switch inductors (SL) [54,55,56,57], Quasi-Z-source networks (QZ) [58], and Switch-Coupled Inductors (SCL). After being connected with qYSC, SL-Y-Sources Converter (L-qYSC-I), QZ-Y-sources converter (L-qYSC-II), and SCL-Y-sources converter (L-qYSC-III) are sequentially obtained, as shown in Figure 22. Although the step-up cells provided continuous input current and higher voltage gain than qYSC, the disadvantages of qYSC, such as the high voltage stress of the switch and the narrow duty cycle control range, are inherited.

2.

The Modified Y-Source Converter with Series Inductance Modules (L-M-YSC)

On this basis, the step-up cells mentioned above were combined with M-YSC to form a series of new topologies, which are shown in Figure 23 [59]. Compared with Figure 22, They further reduced the switch voltage stress, as shown in

Table 8. Properties Comparison among the Y-source converters combined with various boosting structures.

Topology	B	VS,MAX/Vin	VD1,MAX/Vin	VD2,MAX/Vin	VC1,MAX/Vin	VC2,MAX/Vin
M-YSC [39]	$\frac{1+Kd}{1-d}$	$\frac{1}{1-d}$	$\frac{(K^2+2K)(1-d)+K(1+Kd)}{{(1-d)}^2}$	$\frac{(1+Kd)+K(1-d)}{(1+K)(1-d)}$	$\frac{(1-d)+K(1+Kd)}{(1+K)(1-d)}$	$\frac{K(1+Kd)-K(1-d)}{(1+K)(1-d)}$
CB-qYSC [52]	$\frac{1}{[1-(1+K)d](1-d)}$	$\frac{1}{[1-(1+K)d](1-d)}$	$\frac{(\frac{d}{1-d}-1)K}{[1-(K+1)d](1-d)}$	$\frac{1}{[1-(K+1)d](1-d)}$	$\frac{Kd}{(1-Kd)}$	$\frac{1-d}{1-Kd}$
CB-M-YSC [33]	$\frac{1+dK}{{(1-d)}^2}$	$\frac{1}{{(1-d)}^2}$	$\frac{1+K-2Kd+K^{2}d}{{(1-d)}^2}$	$\frac{1}{(1-d{)}^2}$	$\frac{1}{1-d}(1+\frac{Kd}{1-d})$	$\frac{Kd}{(1-d{)}^2}$
L-qYSC-I [53]	$\frac{1+d}{1-(1+K)d-K{d}^2}$	$\frac{1+d}{1-(1+K)d-K{d}^2}$	$\frac{K(1+d)}{1-(1+K)d-K{d}^2}$	$\frac{1+d}{1-(1+K)d-K{d}^2}$	$\frac{(1+d)(1-d)}{1-(1+K)d-K{d}^2}$	$\frac{(1+d)dK}{1-(1+K)d-K{d}^2}$
L-qYSC-II [53]	$\frac{1}{1-(2+K)d}$	$\frac{1}{1-(2+K)d}$	$\frac{K}{1-(2+K)d}$	$\frac{1}{1-(2+K)d}$	$\frac{1-d}{1-(2+K)d}$	$\frac{dK}{1-(2+K)d}$
L-qYSC-III [53]	$\frac{2+n}{1-(1+2K+nK)d}$	$\frac{2+n}{1-(1+2K+nK)d}$	$\frac{(2+n)K}{1-(1+2K+nK)d}$	$\frac{1+n}{1-(1+2K+nK)d}$	$\frac{(2+n)(1-d)}{1-(1+2K+nK)d}$	$\frac{(2+n)dK}{1-(1+2K+nK)d}$
L-M-YSC-I [59]	$\frac{1+dK}{1-d}(1+d)$	$\frac{1+dK}{1-d}$	$\frac{1+d}{1-d}K$	$\frac{1+dK}{1-d}$	$\frac{d(1+d)}{1-d}K$	$[(K-1)d+1]\frac{1+d}{1-d}$
L-M-YSC-II [59]	$\frac{1+dK}{1-2d}$	$\frac{1}{1-2d}$	$\frac{K}{1-2d}$	$\frac{1}{1-2d}$	$\frac{dK}{1-2d}$	$\frac{1-d+dK}{1-2d}$
L-M-YSC-III [59]	$\frac{1+dK}{1-d}(2+n)$	$\frac{2d}{1-d}(2+n)$	$\frac{K}{1-d}(2+n)$	$\frac{1+Kd}{1-d}(2+n)$	$\frac{dK}{1-d}(2+n)$	$\frac{1-d-dK}{1-d}(2+n)$

Here, n is the turns ratio of the switch-coupled inductance.

. Nevertheless, complex components increase the cost of converters, and further consideration needs to be given to improving their power density.

In addition, if the allowable adjustment range of duty cycle is small, the boost ratio will change significantly with the change of the duty cycle, and a small duty cycle disturbance will have a great impact on the output voltage, making the control more difficult. In addition, if the change of boost ratio with the duty cycle is too small, considering that the duty cycle of the converter is usually less than 0.8 in actual operation, the ideal boost ratio cannot be achieved in actual operation. Therefore, the ideal condition is that the allowable adjustment range of the converter duty cycle is as wide as possible, and the ideal boost ratio can be achieved in the range where the duty cycle does not exceed 0.8. As shown in Figure 24, the relationship between the duty cycle and boost ratio of L-M-YSC-III is the most suitable.

4.2. YSC with Low Input Current Ripple

Although M-YSC has achieved continuous input current, it still has the disadvantage of the large input current ripple. When used in photovoltaic power generation systems, it will reduce the life of the photovoltaic arrays. Therefore, it is necessary to reduce the ripple of the input current [60,61].

There are quite a few approaches to reducing the current ripple. The primary method is to use passive L, LC, or LCL filters, but larger filter inductance and capacitance will increase the volume and cost of the Y-source converters [62]. To reduce the volume of the components, an interleaved paralleled converter is proposed in [63]. However, it has complex control methods, and the input current ripple cannot be completely filtered out. Increasing the switching frequency is also an effective method, which can reduce the current ripple without increasing the application of components. Nevertheless, a large switching loss will be caused. Therefore, a new Y-source converter with low input current ripple and higher performance is required.

4.2.1. A Family of Modified Y-Source Converter with Zero Input Current Ripple (ZICR-M-YSC)

To reduce the ripple of the input current, A family of Modified Y-Source Converters with Zero Input Current Ripple (ZICR-M-YSC) is proposed in [64]. As shown in Figure 25a, it is based on the qYSC, while Figure 25b is based on the M-YSC. Compared to the qYSC or M-YSC, only one capacitor and two windings are added. Moreover, the advantages of M-YSC, such as the high boost ratio and low voltage stress on switches, are inherited by ZICR-M-YSC.

Figure 26 shows the theoretical waveform of ZICR-M-YSC, and the simulation results are shown in Figure 27. It can be seen that the current ripples of the inductors L₁ and L₂ cancel each other out so that the input current ripple can be reduced to close to zero.

4.2.2. A Modified Y-Source Converter Using the Conventional Coupled Inductor Filter (CIF-M-YSC)

Figure 28 proposes a modified Y-source converter using a conventional coupled inductor filter [65]. Compared to ZICR-M-YSC, an additional magnetic core is required.

When the switch S turns on, the current of the inductor L₁ in the ZICR-M-YSC and the CIF-M-YSC can be expressed as follows:

$$i_1(t_0)=\frac{N_1}{N_1+N_3}{i}_m(t_0)+\frac{N_3-N_2}{N_1+N_3}(I_{in}-(n+1)\frac{\Delta i_{L1}}{2})$$

(18)

$$i_{1,CIF}(t_0)=\frac{N_1}{N_1+N_3}{i}_{m,CIF}(t_0)+\frac{N_3-N_2}{N_1+N_3}(I_{in}-\frac{1}{1-n^{\prime }}\frac{\Delta i_{L1}}{2})$$

(19)

According to the expression, when n = n′, the current of the CIF-M-YSC is less than that of the ZICR-M-YSC. Therefore, the CIF-M-YSC is more likely to operate in DCM, leading to the current stress of the components increasing, which may reduce the lifespan of the components.

The typical topologies with low input current ripple are compared in

Table 9. Properties Comparison among the typical topologies with low input current ripple.

Topology	B	VS,MAX/Vin	Input Current Ripple	Component Count
				Magnetic Cores	D	C	S
YSC	$\frac{1+Kd}{1-d}$	$\frac{1}{1+Kd}B$	$\frac{d{V}_{in}}{Lf}$	2	2	3	1
[64]	$\frac{1+Kd}{1-d}$	$\frac{1}{1+Kd}B$	0	2	2	4	1
[65]	$\frac{1+d+nd}{{(1-d)}^2}$	$\frac{1}{1+d+nd}B$	0	3	4	4	1
[66]	$\frac{1+(n_2+n_3)d}{1-d}$	$\frac{1}{1+(n_2+n_3)d}B$	${(\frac{N_4}{N_1})}^2\sqrt{\frac{C_4}{L_{lk4}}}{V}_{in}+\frac{\pi }{2}\frac{V_{in}}{L_m}\sqrt{L_{lk4}{C}_4}+\frac{N_3}{N_1}{I}_{D1}(t_0)$	1	4	4	1
[67]	$\frac{n+2}{1-d}$	$\frac{1}{n+2}B$	$\frac{d{V}_{in}}{Lf}$	2	2	4	2

, which shows that YSC and ZICR-M-YSC [63] have fewer components, while YSC has a larger input current ripple. Compared with them, ZICR-M-YSC and the topologies in [64] can achieve zero input current ripple when D > 0.2, and the voltage gain of ZICR-M-YSC is higher than the topologies in [63,64,65,66]. However, the efficiency of the ZICR-M-YSC is lower than M-YSC. Therefore, it is necessary to reduce the losses of the converter.

4.3. High-Efficiency Y-Source Converters

With the widespread application of renewable energy, the requirements for efficiency are higher. However, the switches of all the topologies mentioned above work in a hard-switching state, which leads to large switching loss. Therefore, it is necessary to achieve soft switching, which can reduce the loss of the converter.

4.3.1. The Isolation Type Zero Current Switching Quasi Y-Source Converter (I-ZCS-qYSC)

As is shown in Figure 29, an Isolation type Zero Current Switching quasi Y-Source Converter (I-ZCS-qYSC) is proposed in [68]. By utilizing the parasitic capacitance and leakage inductance of the transformer, Zero Current Switching (ZCS) of all S_X and D_X is achieved. However, with the introduction of redundant components, the power density of the converter is significantly reduced.

4.3.2. The Modified Y-Source Converter with Soft Switching Characteristic and High Voltage Gain (SH-M-YSC)

As is shown in Figure 30, a Modified Y-Source Converter with Soft switching characteristics and High voltage gain( SH-M-YSC) is proposed in [69], which has fewer components than I-ZCS-M-YSC. Its resonant cell, composed of the capacitor C_Q, C₁, C₂, and the winding N₂, N₃, operates in the DCM so that all the switches and diodes of the SH-M-YSC work in ZVS and ZCS.

Figure 31 shows the theoretical waveform of SH-M-YSC, while the simulation results are shown in Figure 32 and Figure 33. It can be seen that both the diodes and switch can work in ZCS and ZVS, which is beneficial for improving the efficiency of the system.

As the switch works in ZCS and ZVS, the switching loss is greatly reduced. Moreover, it is feasible to obtain high-boost radio in DCM. When Considering the maximum resonance time, the expression of voltage gain in DCM is given in [69]:

$$G=\frac{1+\sqrt{1+2D^2\frac{T}{\mathsf{\tau }}}}{2}$$

(20)

According to Equation (20), it can be seen that the voltage gain of the converter is determined by the duty cycle, operating frequency, and the time constant. As the inductance of the coupled inductors decreases, the circuit enters DCM mode, and the output voltage increases with the load, leading to higher voltage gain. Therefore, if the time constant is appropriately selected, soft switching and higher voltage gain can be achieved simultaneously.

In addition, the properties comparison among the converters in [39,64,69] is shown in

Table 10. Properties Comparison among the Y-source converters.

Topology	B	VS,MAX/Vin	Soft Switching	Frequency (kHz)	Component Count
					C	L	Coupled Inductor	D
[39]	$\frac{1+KD}{1-D}$	$\frac{1}{1-D}$	-	100	3	1	1 (3w)	2
[64]	$\frac{1+KD}{1-D}$	$\frac{1}{1-D}$	-	50	4	2	1 (3w)	2
[69]	$\ge \frac{1+KD}{1-D}$	$\frac{1}{1-D}$	ZVS + ZCS	500	3	1	1 (3w)	2

, and the efficiency curves of the converters are compared in the same power range in Figure 34. The results show that the SH-M-YSC, which has a simple structure and soft switching characteristic, has higher efficiency when the output power is higher than 150 W. However, under the light load condition, the efficiency of the system is dropped by 2% for the magnetic core loss under higher frequency operation conditions. Therefore, further consideration should be given to achieving high efficiency under light load, which will further improve the performance of YSCs.

5. Conclusions

Due to the advantage of high boost radio and design flexibility, the Y-source network has received widespread attention. In this paper, the derivation of the Y-source converter is summarized, and the characteristics of similar topologies are compared and analyzed. The main conclusions can be summarized as follows:

• To reveal the corresponding relationship between topology and function, a YSC topology can be divided into basic structure and characteristic circuits. The basic structure (YSC, qYSC, M-YSC) determines the general properties of topology, as shown in Table 2. The clamping circuits, absorption circuits, boost circuit, filtering circuits and resonant circuit in Section 3 and Section 4 are characteristic circuits, which determine the additional functions of the topology. According to the application scenario, the basic structure and characteristic circuits can be selected relatively independently, and the most appropriate topology can be obtained.
• To solve the problem of voltage overshoot caused by leakage inductance, an additional voltage clamp circuit is added to the basic topology. Changing the position of components will result in different stresses of components, with the clamping principle unchanged. Similarly, the position of boost circuit and absorption circuit is also flexible, which is conducive to improving the comprehensive performance of topology while the key characteristics remained.
• The absorption circuit of ZICR-M-YSC makes the input current ripple close to zero and can operate in DCM, but its efficiency is reduced, which can be compensated by the resonant circuit of SH-M-YSC. Therefore, in order to inherit the advantages of both, ZICR-M-YSC and SH-M-YSC can be combined to form a new topology. Taking this as an example, by merging different characteristic circuits, topologies with multiple excellent characteristics can be obtained.
• As analyzed above, most characteristic circuits are relatively independent of the Y-source structure, resulting in limited ability to adjust the winding current. Through the magnetic connection with the y-source winding, the impedance source structure can be fundamentally optimized, and better performance can be achieved.