Research on a Three-Phase Soft-Switching Inverter Based on a Simple Auxiliary Snubber Circuit

Abstract

This study presents a novel soft-switching inverter distinguished by a simplified topology and an innovative modulation approach. The design aims to optimize the energy conversion processes commonly found in auxiliary snubber circuits. By minimizing the number of auxiliary switches, the control method is streamlined, thereby enhancing system reliability and cost-efficiency. The principles of operation and conditions for soft-switching are thoroughly analyzed using equivalent circuit models. A 3 kW/16 kHz inverter prototype was constructed, and the experimental results confirm the effectiveness and benefits of the proposed inverter.

1. Introduction

Soft-switching technology, when integrated with ASCs in hard-switching inverters, offers a notable advantage. The ability of soft-switching inverters to operate in environments with either zero-voltage or zero-current conditions effectively reduces switching losses. This reduction is pivotal for accommodating higher switching frequencies, enhancing the overall performance and efficiency of inverter systems. Moreover, the incorporation of soft-switching techniques leads to a substantial reduction in dv/dt and di/dt across the switches. This mitigation is essential for diminishing electromagnetic interference, a common issue that can compromise the reliability and efficiency of power electronic devices [1,2].

Among various soft-switching inverters, the auxiliary resonant inverter stands out. It includes resonant DC-link inverters [3,4,5,6,7] and auxiliary resonant commutated pole (ARCP) inverters [8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24], depending on the position of the ASC in the inverter. The ASC of the ARCP inverter is active only for a short duration during the switching cycle, which greatly reduces the losses generated by the ASC. Due to these advantages, ARCP inverters have attracted considerable interest from researchers and professionals in the field.

The ARCP inverter introduced in [9,10] is renowned for its ability to achieve comprehensive soft-switching. After that, there are various ARCP inverter variants, including delta or star inverters [11,12], coupled inductor inverters [13,14,15,16], and transformer-assisted inverters [17,18,19], among others. Despite their advancements, these inverters face significant challenges. For instance, the use of large electrolytic capacitors can lead to inherent issues, such as neutral point voltage variation, which can affect the stability and performance of the inverter. Furthermore, in practical implementations, three-phase ASCs are often interconnected, which not only complicates the control strategies but also increases the overall physical size and complexity of the system. These complications can hinder the efficiency and feasibility of deploying such inverters in real-world applications, highlighting the need for more streamlined and effective design solutions.

In [21], a novel ARCP inverter was introduced to overcome the limitations of previous soft-switching inverter designs. This innovative approach effectively reduced switching losses and enhanced overall efficiency by implementing indirect soft-switching for the auxiliary switches. This design successfully resolved several critical issues found in earlier topologies, such as high switching stress and energy inefficiencies. However, despite these advancements, the new inverter still encounters significant challenges in high-power applications. Specifically, parasitic parameters negatively impact the ZVS turn-off process, causing inefficiencies and raising potential reliability concerns. These parasitic effects can degrade performance under high-power conditions, underscoring the necessity for further refinement and optimization to fully realize the soft-switching inverter’s potential.

To address the above challenges, a series of double ARCP inverters have been proposed [22,23,24]. In [22], a reliable zero-voltage switching (ZVS) turn-off condition is achieved by directly connecting capacitors in parallel with the auxiliary switches. Despite this improvement, the inverter still experiences high losses and significant current stress on the auxiliary switches. Building on this work, [23] introduces an additional set of auxiliary switches and proposes an optimized modulation strategy, effectively reducing the current stress on these switches. However, the complexity and coupling of the commutation resonance process in this topology lead to system oscillations. To address these issues, [24] presents an auxiliary circuit using only two resonant inductors, which helps decouple the resonant process and enhances system reliability. Nonetheless, the use of multiple auxiliary switches in [23,24] results in high hardware costs, complicated control schemes, and reduced reliability.

Recognizing the limitations of the abovementioned double ARCP inverters, this paper proposes a novel ARCP inverter design that aims to resolve these issues. The key features and benefits of the proposed inverter include the following:

(1)

All switches can reliably achieve soft-switching, reducing switching losses and improving efficiency;

(2)

The ASC is designed with a simple structure, requiring fewer components, which simplifies the overall system design;

(3)

The proposed inverter operates with fewer modes and achieves higher transmission efficiency, further enhancing performance and reducing complexity.

2. Circuit Topology and Operation Principle

2.1. Circuit Topology

The layout of the proposed soft-switching inverter is illustrated in Figure 1. As shown, the structure and commutation principles are uniform across all phases, allowing phase A to serve as a representative example for analysis [21]. Given the short switching period, it is reasonable to assume that the current remains constant during this interval.

Figure 2 presents the equivalent circuit for phase A. The dashed section highlights the ASC, which is designed to optimize the switching conditions of switches (S₁, S₂). The ASC includes resonant capacitors (C₁, C₂), resonant inductors (L₁, L₂), auxiliary switches (S₃, S₄), and auxiliary diodes (D₃, D₄). C₁(C₂) is connected in parallel with S₁ and S₃ (S₂ and S₄), which limits the voltage change rate and switches can achieve ZVS turn-off. L₁ (L₂) is connected in series with S₃ (S₄), which limits the rate of change of the current through S₃(S₄), thereby minimizing turn-on losses and ensuring ZCS turn-on for S₃ (S₄).

2.2. Operation Principle

The modulation strategy and theoretical waveforms are depicted in Figure 3. The action sequence of switches is as follows: initially, S₁ (S₂) is turned OFF, followed immediately by the activation of S₄ (S₃). After a delay period δ_t1, S₂ (S₁) is then turned on. Subsequently, after another delay δ_t2, S₄ (S₃) is turned off. This sequence ensures effective soft-switching with minimal losses. (S₁, S₂) are modulated according to the sinusoidal pulse width modulation (SPWM), and they operate under the complementary conduction mode with a 180-degree phase difference.

The auxiliary resonant capacitances and auxiliary resonant inductances are designed as C₁ = C₂ = C and L₁ = L₂ = L. Due to the short duration of the commutation time, i_a remains approximately constant. The commutation process of the inverter is structured into eight distinct modes, with each mode’s equivalent circuit illustrated in Figure 4.

Mode 0 [~t₀]: Before t₀, S₁ is conducting, while S₂, S₃ and S₄ are non-conducting. At this stage, i_a flows through S₁. The initial conditions of the resonant elements are specified as v_C1(t₀) = 0, v_C2(t₀) = E, i_L1(t₀) = i_L2(t₀) = 0.

Mode 1 [t₀~t₁]: At t₀, S₁ is switched off, and S₄ is immediately turned on. This initiates resonance in C₁, C₂, and L₂, causing the currents through L₂ to rise. The voltage across C₁ begins increasing from zero, while the voltage across C₂ starts decreasing from E. Under the effect of L₂, S₄ achieves a pseudo-ZCS turn-on. When S₁ is turned off, v_C1 rises resonantly from zero, so S₁ achieves a pseudo-ZVS turn-off. v_C1, v_C2, i_L1, and i_L2 are as follows:

$$i_{C1}(t)=-i_{C2}(t)={\displaystyle \frac{1}{2}}\left({\displaystyle \frac{E}{\omega L}}\sin \omega t+i_a\cos \omega t\right)$$

(1)

$$i_{L2}(t)={\displaystyle \frac{E}{\omega L}}\sin \omega t+i_a(\cos \omega t-1)$$

(2)

$$v_{C1}(t)=E\left(1-\cos \omega t\right)+\omega L{i}_a\sin \omega t$$

(3)

$$v_{C2}(t)=E\cos \omega t-\omega L{i}_a\sin \omega t$$

(4)

where: $\omega ={\displaystyle \frac{1}{\sqrt{2LC}}}$.

When v_C1 rises to E, v_C2 drops to zero and i_L2 reaches the maximum value, i_L2max. At this point, D₂ and D₄ start conducting, signaling the end of mode 1. The duration t_0–1 of mode 1 is given by the following:

$$i_{L2\max }=\sqrt{{\left({\displaystyle \frac{E}{\omega L}}\right)}^2+{i_a}^2}-i_a=\sqrt{{\displaystyle \frac{2C{E}^2}{L}}+{i_a}^2}-i_a$$

(5)

$$t_{0-1}={\displaystyle \frac{1}{\omega }}\arctan ({\displaystyle \frac{E}{\omega L{i}_a}})$$

(6)

Mode 2 [t₁~t₂]: At t₁, v_C1 rises to E, v_C2 drops to zero, and D₂ and D₄ start conducting. Because the sum of the forward voltages of S₄ and D₂ is greater than the forward voltage of D₄, i_L2 flows through D₄, rather than D₂. i_a is carried by D₂, and i_L2 flows through D₄. v_L2 equals the forward voltage of D₄, and i_L2 starts to decrease from i_L2max linearly. When i_L2 decreases to zero, the process concludes, which is independent of other modes. S₂ is turned on during D₂ conduction, and S₂ realizes the ZVZCS turn-on. Mode 2 ends when S₄ is turned off.

The discharge time of L₂ is as follows:

$$t_{L2}={\displaystyle \frac{L{i}_{L2\max }}{V_D}}$$

(7)

where V_D is the forward voltage of the diode.

Mode 3 [t₂~t₃]: At t₂, S₄ is switched off, and the load current i_a flows through D₂. v_S4 and i_S4 are zero during turn-off transient, and S₄ realizes the ZVZCS turn-off.

Mode 4 [t₃~t₄]: At t₃, S₂ is switched off, while S₃ is activated immediately. With E applied across L₁, i_L1 rises from zero linearly. Concurrently, i_D2 decreases from i_a accordingly. As L₁ limits the change rate of current through S₃, S₃ realizes the pseudo-ZCS turn-on. Additionally, S₂ realizes the ZVZCS turn-off, as it is switched off during D₂ conduction. The equations for i_L1 and i_D2 are as follows:

$$i_{L1}(t)={\displaystyle \frac{E}{L}}t$$

(8)

$$i_{D2}(t)=i_a-{\displaystyle \frac{E}{L}}t$$

(9)

When i_L1 rises to the load current i_a, i_D2 drops to zero, and D₂ achieves turn-off naturally, concluding mode 4. According to Equation (8), the duration of mode 4 is as follows:

$$t_{3-4}={\displaystyle \frac{L}{E}}{i}_{\mathrm{a}}$$

(10)

Mode 5 [t₄~t₅]: At t₄, D₂ achieves turn-off naturally. C₁, C₂, and L₁ begin to resonate, v_C2 rises from zero resonantly, and v_C1 decreases from E resonantly. i_L1 rises from i_a resonantly. i_C1, i_C2, v_C1, v_C2, and i_L1 are as follows:

$$i_{C1}(t)=-i_{C2}(t)={\displaystyle \frac{E}{2\omega L}}\sin \omega t$$

(11)

$$i_{L1}(t)={\displaystyle \frac{E}{\omega L}}\sin \omega t+i_a$$

(12)

$$v_{C1}(t)=E\cos \omega t$$

(13)

$$v_{C2}(t)=E\left(1-\cos \omega t\right)$$

(14)

When v_C2 rises to E, v_C1 drops to zero and i_L1 reaches the maximum value i_L1max, D₃ conducts, and mode 5 ends. Because the sum of the forward voltages of S₃ and D₁ is greater than the forward voltage of D₃, the current in L₁ flows through D₃, rather than D₁. i_L1max and the duration of mode 5 is as follows:

$$i_{L1\max }(t)={\displaystyle \frac{E}{\omega L}}+i_a=E\sqrt{{\displaystyle \frac{2C}{L}}}+i_a$$

(15)

$$t_{4-5}={\displaystyle \frac{\pi }{2}}\sqrt{2LC}$$

(16)

Mode 6 [t₅~t₆]: At t₅, i_L1 reaches the maximum value i_L1max and D₃ conducts. v_L1 is equal to the forward voltage of D₃, and i_L1 starts to decrease from i_L1max linearly. When i_L1 decreases to zero, the process ends, which is independent of other modes. S₁ is turned ON during this process, and S₁ realizes the ZVZCS turn-on. Mode 6 ends when S₃ is turned OFF.

The discharge time of L₁ is as follows:

$$t_{L1}={\displaystyle \frac{L{i}_{L1\max }}{V_D}}$$

(17)

Mode 7 [t₆~t₇]: At t₆, S₃ is switched off, and i_a commutates to S₁ immediately. The circuit transitions back to mode 0 and awaits the subsequent switching cycle. The voltage across C₁ is zero during the turn-off transient of S₃, and S₃ realizes the true ZVS turn-off.

In conclusion, compared with the inverters in [22,23], the inverter in [24] and the proposed inverter use two inductors in each phase to solve the coupling problem in the resonance process. Compared with the inverters in [23,24], the inverter in [22] and the proposed inverter use two auxiliary switches in each phase, which reduces control complexity and improves system reliability. Therefore, based on maintaining the advantages of the inverters in [22,23,24], the ASC in the proposed inverter is greatly simplified, and the working modes are minimized (there are 14, 10, and 10 working modes in [22,23,24], respectively).

3. Steady-State Characteristics

3.1. Soft-Switching Realization Condition

Since the switches (S₁, S₂, S₃, S₄) are directly connected in parallel with auxiliary resonant capacitors (C₁, C₂), all switches (S₁, S₂, S₃, S₄) can realize the ZVS turn-off under any condition. To realize the ZVZCS turn-on for (S₁, S₂), the circuit operation must ensure that modes 1, 4, and 5 are completed within the commutation time δ_t1. This commutation time should not exceed the dead time t_dead typically found in conventional inverters. From Equations (6), (10) and (16), it can be inferred that the combined duration of modes 4 and 5 is greater than that of mode 1. Hence, the following inequality must be satisfied:

$$t_{3-5}={\displaystyle \frac{L}{E}}{i}_{a\max }+{\displaystyle \frac{\pi }{2}}\sqrt{2LC}\le {\delta }_{t1}\le t_{dead}$$

(18)

To realize the ZCS turn-on for (S₃, S₄), it is necessary to ensure that the currents through L₁ and L₂ decline to zero before S₃ and S₄ are turned on in the next switching period. According to (5) and (15), i_L1max > i_L2max. Therefore, as long as i_L1 declines to zero before S₃ is activated, S₃ can realize ZCS turn-on, subsequently enabling S₄ to also achieve ZCS turn-on.

As shown in Figure 5, the duration of the current in L₁ declines to zero should be less than or equal to T_zcs, which can be expressed by the following:

$$t_{L1}={\displaystyle \frac{L{i}_{L1\max }}{V_D}}\le T_{ZCS}$$

(19)

$$T_{ZCS}=T_S-t_{3-5}$$

(20)

where V_D is the forward voltage of the diode, and T_s is the switching period. For a switching frequency of f_s, T_s =1/f_s. T_zcs is the duration within which the auxiliary switches can achieve ZCS turn-on.

3.2. Number of Components and Soft-Switching Action

Table 1. Number of components and soft-switching action.

Components	Auxiliary Switch	Auxiliary Diode	Resonant Inductor	Resonant Capacitor
[22]	2	8	4	6
[23]	4	8	4	6
[24]	4	4	2	6
This paper	2	2	2	2
Switching		(S1, S2)	(S3, S4)	(S5, S6)
[22]	Turn-on	ZVZCS	Pseudo ZCS	—
	Turn-off	Pseudo ZVS	Pseudo ZVS	—
[23]	Turn-on	ZVZCS	Pseudo ZCS	ZVZCS
	Turn-off	Pseudo ZVS	Pseudo ZVS	ZVZCS
[24]	Turn-on	ZVZCS	Pseudo ZCS	ZVZCS
	Turn-off	Pseudo ZVS	Pseudo ZVS	True ZVS
This paper	Turn-on	ZVZCS	Pseudo ZCS	—
	Turn-off	Pseudo ZVS	True ZVS	—

compares the number of components and their soft-switching performance. The key findings are as follows: (1) The proposed inverter employs the fewest auxiliary components relative to [22,23,24], leading to lower hardware costs and enhanced power density and reliability. (2) In the referenced works [22,23,24], auxiliary switches (S₃, S₄) achieve pseudo ZVS turn-off. In contrast, the proposed inverter’s auxiliary switches attain true ZVS turn-off, thereby significantly reducing turn-off losses.

3.3. Voltage and Current Stress of Components

Table 2. Electrical stress comparison.

Voltage Stress	(S1, S2)	(S3, S4)	(S5, S6)
[22]	E	E	—
[23]	E	E	E
[24]	E	E	E
This paper	E	E	—
Current stress	(S1, S2)	(S3, S4)	(S5, S6)
[22]	iamax	$E\sqrt{{\displaystyle \frac{2C_a+C_c}{L_a}}}+i_{a\max }$	—
[23]	iamax	$E\sqrt{{\displaystyle \frac{2C_m}{L}}}+i_{a\max }$	$E\sqrt{{\displaystyle \frac{2C_m}{L}}}+i_{a\max }$
[24]	iamax	$E\sqrt{{\displaystyle \frac{2(C_m+C_a)}{L}}}+i_{a\max }$	$\max \left\{{\displaystyle \frac{E}{3}}\sqrt{{\displaystyle \frac{2(C_m+C_a)}{L}}},{\displaystyle \frac{C_a{i}_{a\max }}{2C_m+C_a+C_b}}\right\}$
This paper	iamax	$E\sqrt{{\displaystyle \frac{2C}{L}}}+i_{a\max }$	—

provides a comparative analysis of the voltage and current stresses on the switches. Components that are not present in a particular topology are indicated with dashes. The main points from the table are as follows:

(1)

The proposed inverter and the inverter in [22] utilize the fewest switches compared to those in [23,24], which simplifies control and reduces hardware costs;

(2)

The voltage stress on all switches in both the proposed inverter and those in [22,23,24] is constrained to the DC power supply E;

(3)

(S₁, S₂) in the proposed inverter and those in [22,23,24] experience current stress limited to the peak output current i_amax;

(4)

The auxiliary switches in the proposed inverter are subjected to the lowest current stress. This stress can be further minimized by increasing the auxiliary resonant inductance L and decreasing the auxiliary resonant capacitance C.

In summary, the voltage stress on all switches and the current stress on the main switches (S₁, S₂) in the proposed inverter are on par with those in [22,23,24]. However, the proposed inverter shows advantages in terms of lower current stress on auxiliary switches and a reduced number of auxiliary components.

4. Parameter Design

Considering the input DC voltage E and the maximum output load current i_amax, the design parameters must adhere to the following criteria:

(1)

To facilitate soft-switching, the conditions specified in Equations (18)–(20) must be met;

(2)

The change rate of voltage should be constrained to a set limit (dv/dt)_set, and similarly, the current change rate should remain within the set limit (di/dt)_set. These conditions can be mathematically represented as follows:

$${\displaystyle \frac{dv}{dt}}\le \sqrt{{\displaystyle \frac{2C{E}^2+L{i}_{\mathrm{a}max}^2}{4L{C}^2}}}\le {\left(dv/dt\right)}_{\mathrm{set}}$$

(21)

$${\displaystyle \frac{di}{dt}}={\displaystyle \frac{E}{L}}\le {\left(di/dt\right)}_{set}$$

(22)

(3)

To optimize the efficiency of the system, this paper tries to minimize the circulation loss of inductance current. The total circulation loss is as follows:

$$\begin{array}{ll}W=& {\displaystyle \frac{1}{2}}L{i}_{L1\max }^2+{\displaystyle \frac{1}{2}}L{i}_{L2\max }^2\\ & <2C{E}^2+{\displaystyle \frac{3}{2}}L{i}_a^2\end{array}$$

(23)

As detailed in (23), meeting these parameters requires minimizing capacitors (C) and inductors (L). This reduction is crucial to decrease circulating losses and improve the overall efficiency of the system. According to (15), to mitigate the current stress on the auxiliary switches, it is essential to prioritize selecting the smallest feasible capacitance (C).

Therefore, the optimal design involves carefully balancing these components to achieve the desired soft-switching performance while minimizing losses and stress on the auxiliary switches. By appropriately selecting smaller values for (C) and (L), the system can operate more efficiently, with reduced thermal and electrical stress on its components.

5. Experimental Results

To validate the correctness of the analysis presented, a prototype with a capacity of 3 kW and operating at 16 kHz was constructed. The specific components and their parameters are detailed in

Table 3. Components and parameters of the prototype.

Components	Parameters
Control board	DSP TMS320F2812
Driver chip	SKHI23/17
Input DC voltage (E)	200 V
Switching frequency (fs)	16 kHz
S1(D1)–S2(D2)	SKM75GB063D (600 V, 100 A)
S3–S4	IRG4PC50K (600 V, 52 A)
D3~D4	RHRG7560(600 V, 75 A)
C1–C2	10 nF
L1–L2	2 μH

.

5.1. Waveforms Evaluation

Figure 6 presents the turn-on waveforms of the main switch S₁. From Figure 6, it is apparent that both the voltage and current of S₁ are zero just before the switch is turned on. This condition ensures that S₁ achieves ZVZCS during turn-on, thereby minimizing switching losses.

The turn-off waveforms of S₁ are shown in Figure 7. The voltage across S₁ can be seen to rise gradually from zero when S₁ transitions from on to off. This slow rise in voltage indicates a pseudo-ZVS turn-off, which helps in reducing the turn-off losses and prolongs the lifespan of the switch by minimizing the stress during the transition.

Figure 8 illustrates the voltage and current waveforms of S₃ during both turn-on and turn-off transitions. The figure shows that the current through S₃ increases at a lower rate, which is indicative of a pseudo-ZCS turn-on. Additionally, the voltage across S₃ remains at zero during the turn-off transition, demonstrating a true ZVS turn-off. These conditions help in significantly reducing the switching losses and improving the overall efficiency of the inverter.

Figure 9 depicts the current waveforms of L₁ and L₂. From Figure 9, it is evident that the currents through L₁ and L₂ decay rapidly to zero within each switching cycle. This rapid decline ensures that S₃ and S₄ can achieve a pseudo-ZCS turn-on, which is crucial for minimizing switching losses. The i_L1 and i_L2 exhibit an exponential decay pattern, which can be attributed to the inherent parasitic resistances within the circuit components.

5.2. Efficiency Comparison

Figure 10 compares the efficiency of the proposed soft-switching inverter with those of inverters presented in [22,23,24] and a conventional hard-switching inverter. The data reveal that the proposed inverter achieves an efficiency of 97.8% at an output power of 3 kW. This efficiency is significantly higher than that of other inverters within 1–3 kW. The superior efficiency of the proposed inverter is primarily due to the simplification of the commutation process, which reduces the associated switching losses. Additionally, the implementation of soft-switching techniques in the proposed inverter further enhances its efficiency by lowering the thermal and electrical stresses on the components. Overall, the experimental results validate the effectiveness of the proposed inverter design in achieving high efficiency and reliable performance through reduced switching losses and enhanced soft-switching capabilities.

6. Conclusions

This paper introduces a novel soft-switching inverter topology. From theoretical analysis and experimental research, the following conclusions can be drawn:

(1)

The proposed topology features a simplified structure with fewer components and reduced operating modes. This simplification not only lowers the overall cost but also enhances the inverter’s performance by making it more efficient and reliable;

(2)

All switches are capable of achieving soft-switching. Specifically, while auxiliary switches in [22,23,24] manage the pseudo-ZVS turn-off, the auxiliary switches in the proposed inverter achieve a true ZVS turn-off. This true ZVS turn-off significantly reduces switching losses and improves the overall efficiency and longevity of the switches by minimizing stress during transitions;

(3)

When compared to the ARCP inverters detailed in [22,23,24], the proposed inverter demonstrates superior transmission efficiency. This improvement is primarily due to the enhanced soft-switching capabilities and the reduced number of components, which collectively contribute to lower power losses and higher operational efficiency.