A Modified Nearest Level Control Scheme for Improved Submodule Current Sharing in a CHB Converter with Integrated EDLCs

Abstract

This study investigates a Cascaded H-Bridge converter with Electric Double-Layer Capacitors as integrated energy storage components. As the DC-link voltages are variable, the modulation index and number of submodules contributing to the active power delivery vary according to state of charge. The nearest level control algorithm for this application is studied, and expressions for the duty cycle of conventional Nearest Level Modulation are derived. A modification of the sort and select algorithm to determine which submodule is to be inserted and bypassed when using the Nearest Level Control algorithm is proposed to distribute the activation time and the experienced RMS current of the submodules. Expressions for the duty cycle of each inserted submodule for the proposed algorithm is presented and compared to the conventional. Simulation experiments of current sharing between submodules under active power delivery for the conventional and proposed Nearest Level Control is conducted for an 11- level, 41-level and 61-level converter. Simulation experiments show a reduction in RMS current for the submodule experiencing the highest thermal stress. Over the course of power delivery and increasing modulation index, the peak RMS current increase for the conventional nearest level modulation while it is kept constant for the proposed modulation scheme.

1. Introduction

The electric double layer capacitor (EDLC), commonly referred to as a supercapacitor, is a popular choice of energy storage technology for high power applications where the energy density is not prioritized. Power-dense energy storage systems are increasingly being utilized in hybrid systems, where they support existing functions with larger energy content but insufficient response times. Several studies have explored the use of EDLCs to support hydropower units to qualify for the provision of frequency regulation services in strong grids [1,2,3,4], as well as in weak grid conditions to support island operation and black start [5].

Multilevel inverter systems and the integration of EDLCs have been investigated for the integration of ESS to MV levels [6,7]. Integrating or enhancing existing inverter infrastructures such as static VAR compensators (STATCOMs) with energy storage systems [8,9] or MMCs for grid interconnection [10,11,12,13] is another topic where the use of EDLCs as energy storage components has been explored.

EDLCs have an inherent dependency between the voltage and state of charge, usually addressed by adding a DC-DC inverter step to ensure a stable output voltage from the energy storage device to the switching bridge. The additional DC-DC interface, however, induces additional losses and active switching components, which may decrease the redundancy of the inverter system. In ref. [14], the authors suggest that removing the DC-DC inverter interface can reduce the power losses by 14%.

As the DC-DC converter interface is removed, initially redundant submodules are added to ensure the continued operation of the inverter as the voltage of each EDLC varies with the state of charge. As the number of submodules increases, modulation schemes that depend on a large number of submodules to produce a sinusoidal voltage without unacceptable levels of harmonics can be employed [15]. In this case, the nearest level modulation (NLM) algorithm is investigated, and an important question is how to modify the selection and activation times of the submodules to ensure the even discharge of the EDLC modules comprising the energy storage.

Energy balancing in capacitors has been widely studied. This work builds on the general principle first described in [16]. As the number of submodules connected in series varies over the course of active power delivery, the balancing of the submodule voltages is ensured by determining which submodules are inserted according to their voltage level. Energy imbalances over the course of a fundamental cycle can occur when using NLM in multilevel inverters due to the fact that the submodule first inserted discharges to a larger degree than the submodule last inserted. Solutions that address this imbalance include selecting which submodules are to be inserted and bypassed to ensure an improved energy balance, as outlined in [17]. In the proposed application, the energy content of the EDLCs is several magnitudes larger than that of conventional DC-link capacitors, and the inter-fundamental energy imbalance is not an issue. The goal of this study is rather to examine the nearest level control modulation strategy for the application of EDLC integration, as well as a modification of the voltage inserting and bypassing algorithm based on the symmetry of the voltage reference. The state-of-charge balancing of the submodules in the phase arm and the current sharing between submodules is investigated regarding the modulation methods. The duty cycles for the arbitrary submodules in the phase arms are derived for the two modulation schemes, and the length of the duty cycle is utilized to propose two balancing algorithms to ensure the even discharge of the submodules in the phase arm over time. Hardware limitations are considered, ensuring that the submodules operate within their rated limits in terms of the peak current and series-connected voltage and adhere to RMS current limitations. The conduction loss in the supercapacitor is one of the primary drivers of losses in the proposed converter [18], but investigations of the switching loss are not included in this study. Efficiency issues with high current discharge have been explored in [19], and, to ensure uniform heating in energy storage components, the distribution of the RMS current is investigated in this study as the RMS current per submodule affects the dimensioning process of the EDLC storage. The temperature is an important parameter driving degradation in EDLCs [20], and the proposed modulation scheme reduces the peak thermal stress in the submodules due to the decreased maximum RMS current compared to the conventional case.

This study is related to previous work within a project aiming to utilize the modular structure of the cascaded H-bridge (CHB) topology for the application of hybridization projects. The project builds on the topology proposed in [6]. This topology is modified according to [2] to mitigate overvoltage exposure in the EDLC arising from the energy stored in the (relatively large) parasitic inductance of the EDLC modules, which is dissipated as commutating currents at turn-off. A schematic illustration of the inverter with N submodules in each phase leg is presented in Figure 1.

2. Materials and Methods

This section describes the converter and the application of integrated EDLC modules. The nearest level modulation scheme and the proposed nearest level modulation scheme are described, along with the associated sorting algorithms to ensure vertical voltage balancing. The distribution of the current and the discharge of the submodules are analyzed initially by deriving the duty cycle per submodule as a function of the number of submodules in the CHB converter.

Simulations are conducted to demonstrate the discharge of the energy storage systems during active power delivery, and the details of the simulations conclude this section.

2.1. Converter Outline and General Assumptions

A description of the converter model is provided in Figure 1. A more detailed description of each submodule and the necessary absorption circuits can be found in [21].

This paper focuses on the discharge of one phase leg in a CHB converter, where the current distribution effects of two modulation schemes and vertical voltage balancing are investigated. A horizontal voltage balancing scheme, such as that proposed in [22], to ensure the even discharge of the phase arms is not within the scope of this paper. The generation of voltage references in the model is summarized in Figure 2. The measured grid voltage $V_g,d$, the voltage of the converter $V_{chb}$ and the power reference value are used to generate the phase difference $\varphi$ between the grid and converter voltages to generate the inductor current needed to supply the power set-point value. The phase shift is added to the grid voltage derived from the PLL to generate the voltage reference used to track the active power reference. This study then focuses on the modulation of the phase arm to generate this reference, with a specific focus on current sharing in the submodules.

The utilization of directly integrated EDLCs as the DC voltage supply in the submodules has some implications for the control of the converter. A simplified relationship between the voltage and stored energy of an EDLC is as follows:

$$W_{EDLC}={\displaystyle \frac{1}{2}}{C}_{EDLC}(V_{rated}^2-V_{min}^2)$$

(1)

where $C_{EDLC}$ is the capacitance of the EDLC. If the energy stored in the EDLC ($W_{ELDC}$) is allowed to decrease to 25% of the rated energy (75% utilization), the voltage will fluctuate within 1–0.5$V_{rated}$. To be able to employ the topology described in Figure 1, a method must be used to compensate for the variable voltages of the energy storage components. A method is proposed by introducing a number of redundant submodules in the inverter and varying the modulation index of the inverter, dependent on the voltage in each submodule. A graphical representation is presented in Figure 3; as the voltage in each submodule decreases, a larger number of submodules must be connected in series to maintain the output voltage of the inverter.

While variable over large time scales, the EDLC voltage will still remain close to constant over half a fundamental cycle due to the large energy content compared to film capacitors. The voltage drop from the EDLCs over half a fundamental period is in the range of millivolts (depending on the discharged current). Using (1) and assuming an initial voltage of 50 V, current discharge at 1 kA for half a fundamental cycle and EDLC capacitance of 166 F, the voltage drop is 60 mV. This can be compared to the voltage drop due to the ESR of 5.3 mΩ, amounting to 5.3 V. This assumption that $\Delta V_{dc}\simeq 0$ over the course of half a fundamental period makes it possible to derive duty cycles for the nearest level modulation scheme and the proposed nearest level modulation scheme. See

Table 1. Electrical properties of the reference EDLC module [23].

Property and Unit	Symbol	Value
Rated voltage [V]	$V_{SM}$	51
Capacitance [F]	C	166
Maximum peak current 1 s [A]	$I_{max}$	2252
Maximum series voltage [V]	$V_{ser}^{max}$	750
Maximum continuous current (ΔT = 40 °C) [${\mathrm{A}}_{RMS}$]	$I_{RMS}^{max}$	137
ESR [mΩ]	$R_{ESR}$	5.3

for electrical properties of the EDLC parameters utilized.

2.2. Voltage and Current Limitations

Some hardware limitations must be maintained for the safe operation of the EDLCs, such as limitations on the connected voltage in series, the peak current levels and the RMS current levels to be drawn from each submodule.

2.2.1. Voltage Limitations

Initially, the maximum series voltage limitation is addressed by limiting the number of series-connected submodules, representing the initial configuration of the inverter.

$$m_i={\displaystyle \frac{V_{ser}^{max}}{N_{SM}{V}_{SM}}}$$

(2)

where $m_i$ is the modulation index in this context, denoting the number of active submodules needed to meet the peak voltage of a fundamental period compared to the available submodules in the arm. The output voltage peak from the converter becomes

$$V_p=m_i{N}_{SM}{V}_{SM}\le V_{ser}^{max}$$

(3)

$V_{SM}$ decreases as the SOC is depleted and more submodules are connected in series until $m_i>1$, after which the submodules are not able to produce the reference voltage peak.

2.2.2. Current Limitations

The limitations relating to the current are the peak current and temperature increase from the RMS current; values from the datasheet are presented in Table 1. The losses arising from the ESR in EDLCs may be large if operating at excessively high currents [19]. This study investigates the peak RMS values and considers whether the distribution of the RMS current is affected by the two modulation schemes.

2.3. Conventional Nearest Level Modulation with Voltage Balancing

NLM utilizes a rounding mechanism to select the voltage output from each phase leg to fit the voltage reference produced by the higher-order control of the inverter.

$$N\left(t\right)=round\left({\displaystyle \frac{V^{*}}{V_{dc}}}\right)$$

(4)

where $V^{*}$ is the reference voltage to be produced, and $V_{dc}$ denotes the submodule voltages. As the voltages are variable within 1–0.5$V_{dc}$, the comparison algorithm constantly compares the voltage reference to the next submodule’s voltage in an array of stored values. The sorting of the submodules to be compared to the voltage reference ensures the SOC control of the submodules over time in each phase arm, i.e., vertical voltage balancing. This vertical balancing scheme, usually called sort and select, was proposed by [16] and explored further in [17,24]. Due to the large energy content of the EDLCs, the sort and select implementation proposed in [2] considers only which submodules to insert, knowing that the first submodule inserted in each half fundamental cycle will discharge the furthest. A fundamental cycle consisting of the voltage reference and the nearest-level-controlled submodules is presented in Figure 4. Voltage sensors are needed in the submodules to communicate the submodule voltage to the master controller.

Figure 5 presents the control scheme of the inverter. The voltage levels of each submodule are stored in an array $\overline{V_{dc}}$. For every $N_{ZC}$ zero crossings of the grid voltage per phase, $\overline{V_{dc}}$ is sorted according to the voltage level to ensure that the highest-voltage submodules are activated first. The sorting is performed at zero crossings to avoid unnecessary switching.

Duty Cycle in Conventional NLM

The duty cycle per submodule of the conventional nearest level modulation (NLM) scheme varies as a function of how many switching levels are available to meet the peak fundamental voltage. Below is a mathematical description of the duty cycle of the conventional NLM algorithm for a CHB converter. As stated, the nearest level modulation scheme is defined by a rounding function of the voltage reference,

$$V^{*}=V_{p}sin\left(\omega t\right)$$

(5)

where $V_p$ is the peak voltage, and $\omega$ is the frequency of the voltage reference. When the reference value increases above the mean value of the currently active and next active submodule in the arm, the next submodule is activated. The absolute value is used as the below equations are used for reproducing positive and negative voltages. The sign of the reference affect which switches to modulate.

$$\left|V^{*}\right|\ge \left|{\displaystyle \frac{{\sum }_1^{k-1}{V}_{dc}+{\sum }_1^k{V}_{dc}}{2}}\right|=\left|{\displaystyle \frac{2{\sum }_1^{k-1}{V}_{dc}+V_{dc}}{2}}\right|$$

(6)

The voltage at the switching instant can be described as

$$V^{*}=V_{p}sin\left(\omega t_{on}\right)=\left|{\displaystyle \frac{2{\sum }_1^{k-1}{V}_{dc}+V_{dc}}{2}}\right|$$

(7)

The turn-on instant of the submodule k is thus

$$t_{on}={\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_1^{k-1}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)$$

(8)

Assuming a symmetrical sinusoidal voltage, and that the discharge of each submodule over the course of a fundamental cycle is negligible (an assumption that is valid when working with EDLC modules compared to film capacitors), the active duration of submodule k can be expressed as twice the time from $t_{on}$ to the peak of the sine, occurring at $t_{\pi /2}$.

$$\begin{array}{cc}\hfill V^{*}=V_p& \forall sin\left(\omega t\right)=1\hfill \end{array}$$

(9)

$$\begin{array}{cc}\hfill t_{\pi /2}& ={\displaystyle \frac{\pi }{2\omega }}\hfill \end{array}$$

(10)

$$\begin{array}{cc}\hfill {\displaystyle \frac{1}{2}}D& =t_{\pi /2}-t_{on}=t_{\pi /2}-t_{off}\hfill \end{array}$$

(11)

$$\begin{array}{cc}\hfill T& ={\displaystyle \frac{\pi }{\omega }}\hfill \end{array}$$

(12)

T is the total period, i.e., half a fundamental cycle.

$$D_k=2(t_{\pi /2}-t_{on})=2\left({\displaystyle \frac{\pi }{2\omega }}-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_1^{k-1}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)\right)$$

(13)

The submodule with the shortest D will be the last submodule activated to meet the peak voltage, and the submodule with the longest D is the first submodule to be activated. The longest duty cycle can be expressed as

$$\begin{array}{cc}\hfill D& =D_{max}\forall k=1\hfill \end{array}$$

(14)

$$\begin{array}{cc}\hfill D_{max}& =2\left({\displaystyle \frac{\pi }{2\omega }}-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{V_{dc}}{2V_p}}\right|\right)\right)\hfill \end{array}$$

(15)

The shortest D can be expressed as the last submodule activated to meet the peak voltage. This submodule is denoted as $N_k=m_i{N}_{dc}$.

$$D_{min}=2\left({\displaystyle \frac{\pi }{2\omega }}-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_0^{N_k-1}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)\right)$$

(16)

2.4. Modified Nearest Level Modulation Algorithm

Below is a description of the modified NL algorithm, where the instant at which the submodules are bypassed is modified. The addition to the control schematic is presented in Figure 6, and it can be summarized as tracking the change in the sign of the derivative of the voltage reference, which occurs when $N_k$ submodules needed to deliver the reference voltage are active. The indices of the submodules that are active at this instant are flipped, so that the submodule that was last turned on will be the last to be turned off in each half-fundamental cycle; see Figure 7.

Using the same assumptions as in the previous section, the duty cycle of each submodule can be expressed with $t_{on}$$t_{off}$. Using $D_{max}$ and $D_{min}$, the most intuitive example is derived. The duty cycle is balanced in such a way that the turn-on instant for the submodule that was first activated is combined with the turn-off instant of the submodule that was last activated. While we previously had $D_{max}=D_1$ and $D_{min}=D_{N_k}$, we now have, through the simplification of (13),

$$\begin{array}{cc}\hfill D_1& ={\displaystyle \frac{1}{2}}(D_{N_k}+D_1)={\displaystyle \frac{1}{2}}(D_1+D_{N_k})=D_{N_k}\hfill \end{array}$$

(17)

$$\begin{array}{ccc}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}& D_1& ={\displaystyle \frac{\pi }{\omega }}-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_1^{N_k}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{V_{dc}}{2V_p}}\right|\right)=D_{N_k}\hfill \end{array}$$

(18)

This is expanded to the general case. We can express D for submodule k such that

$$\begin{array}{cc}\hfill D_k& =t_{off}^{N_k-(k-1)}-t_{on}^k={\displaystyle \frac{1}{2}}(D_{N_k-(k-1)}+D_k)\hfill \end{array}$$

(19)

$$\begin{array}{ccc}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}& \hfill D_k& ={\displaystyle \frac{\pi }{\omega }}-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_1^{N_k-k}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)-{\displaystyle \frac{1}{\omega }}arcsin\left(\left|{\displaystyle \frac{2{\sum }_1^{k-1}{V}_{dc}+V_{dc}}{2V_p}}\right|\right)\hfill \end{array}$$

(20)

This section can be summarized by looking at the relationship between N and $D_{max}$, $D_{min}$ (for the conventional NLM) and $D_1=D_{N_k}$ (for the proposed NLM algorithm), as presented in Figure 8. It is clear that $D_{max}$ for the conventional NLM converges to $\pi /2\omega$ within a range of N that is feasible for the actual implementation of the converter; in this case, ($15\le N\le 30$) is a range that is deemed suitable. Due to the quadratic nature of arcsin, $D_{min}$, while converging to 0 for a large N, does not converge for a feasible N and stays within a $D=0.15–0.1$ of T in the range of interest. $D_1=D_{N_k}$ converges to $\pi /2/\omega$ for a large N, but, for the region of interest, $0.55\le D_1\le 0.57$ of T.

The D per submodule for converters with $N_k$ varying from 5 to 100 with increments of 10, including the 11-level case, which is studied in the simulations, is presented in Figure 9, where additional information can be drawn from the two modulation schemes. The data presented in Figure 9a correspond to the duty cycle of each submodule $D_k$, where the x-axis represents $N_k$. In Figure 9b, the duty cycle is plotted against the index in the order of selection over the course of half a fundamental cycle; the x-axis thus represents k. For the conventional NLM, it is clear that, if selected first, as N increases, $D\to 1$, and, if selected last, $D\to 0$. The proposed NLM is symmetrical in such a way that $D_1=D_N\to \pi /2\omega$, or 0.5, while the longest D occurs for the submodules inserted closest to $\pi /4\omega$.

2.5. Sorting and Vertical Voltage Balance

To ensure the vertical balancing of the submodule voltages in the phases, two sorting approaches are thus employed; for the conventional NL, the indexing is straightforward. If the voltages are sorted in descending order at intervals of $NZ$, the submodule with the highest voltage is selected for the longest D. This approach is suitable for the case of EDLCs with a relatively small voltage discharge per fundamental cycle. The $NZ$ interval may differ depending on the capacitance of the EDLCs and the rate of discharge.

Utilizing the results from the previous section, a sorting algorithm is proposed that adds a second distribution step to the initial descending sorting. The longest duty cycle for the proposed modulation scheme occurs for the submodules inserted at $\pi /4w$, and the shortest D occurs for the submodules inserted closest to 0 and $\pi /2w$. The distribution of the index vector when selecting the submodules to be activated in the upcoming cycles should thus be arranged according to a normal distribution to avoid uneven discharging. An additional step that involves determining how many submodules will be connected in the upcoming cycle must also be included. The sequence of changes to the sorting algorithm is presented in Figure 10.

Determining the number of submodules to be activated requires the assumption that the number of activated submodules will be the same as in the last fundamental cycle, which is determined through $round\left(m_{i}N\right)$. The distribution step of arranging the vector such that the submodules with the highest DC-link voltage is selected first may be achieved in many ways; in the current simulation tool, a for loop is employed, but the use of an indexing pattern for rearrangement would reduce the computational time. Finally, the two vectors of the assumed submodules to be connected and the submodules assumed not to be connected are concatenated, with M being sorted in a descending manner to connect the submodule with the highest state of charge.

2.6. Simulations

A simulation tool has been developed in Matlab to simulate the inverter system during active power discharge, allowing for adjustments in the numbers of submodules, energy storage components and switching devices [18]. This tool may be used to evaluate the overall switching loss and to validate the vertical balancing of the submodules of the sorting algorithms proposed for the two modulation schemes. Three cases are studied, with 5 N per phase arm, i.e., 11-level, 20 N (41-level) and 30 N (61-level) inverter cases are studied. The active power delivery and arm inductor value vary between simulations of different levels to enable comparable modulation and discharge between the three inverter cases. The active power delivery is sustained for 8 s of nominal power.

Table 2. Description of simulation details, number of submodules and sorting intervals of the conventional (and proposed) nearest level modulation schemes.

	Symbol	Value
Time step	dt	1 × 10−6 [s]
Voltage sorting interval (zero crossings)	$N_{ZC}$	3
Case 1
Number of submodules	$N_{DC}$	5
Nominal power output	$P^{*}$	0.325 [MW]
Filter inductance value	$L_f$	0.17 [mH]
Case 2
Number of submodules	$N_{DC}$	20
Nominal power output	$P^{*}$	1.3 [MW]
Filter inductance value	$L_f$	0.47 [mH]
Case 3
Number of submodules	$N_{DC}$	30
Nominal power output	$P^{*}$	1.95 [MW]
Filter inductance value	$L_f$	0.7 [mH]

specifies the primary simulation parameters.

3. Results

This section examines the differences between the proposed and conventional NLM schemes under active power delivery. First, the basic assumptions of EDLC discharge are affirmed, and the duty cycle for each submodule in the simulations is investigated and compared to the theoretical description. The distribution of the current in the submodules is investigated over active power delivery. Results regarding the vertical voltage balancing capabilities of the modulation scheme are also presented.

Figure 11 shows that the two modulation schemes produce the same inductor current and line-to-neutral voltage per phase, but the activation times of the submodules differ. Figure 11a reproduces the conventional NLM and Figure 11b reproduces the proposed NLM. Each submodule is represented by an integer as an index, and the figures indicate when corresponding submodules are active.

The EDLC discharge being small over the course of one fundamental cycle is one of the basic assumptions of the proposed modulation method. The voltage drop of the EDLCs due to energy discharge for the three simulation cases is presented in Figure 12, where (a) corresponds to 5 N, (b) corresponds to 20 N and (c) corresponds to 30 N. The discharge corresponds to approximately 0.01 V, with a minor variation according to D and the amount of current. The current is between 930 and 950 A in all simulations, close to the peak current capability of the EDLCs.

The duty cycle of each submodule in the simulated cases for half a fundamental cycle is presented in Figure 13, in the same format as in Figure 9 in Section 2.

3.1. Distribution of RMS Current

A fundamental cycle beginning when the modulation index of each simulation case was close to 1 was used to conduct a comparison of the RMS currents between the proposed and conventional NL schemes. The mean and maximum RMS currents were derived for each submodule in the modulation schemes. The maximum values were compared, and a ratio is presented in

Table 3. A comparison between the submodules exposed to the highest RMS current values is presented as a ratio. The mean RMS current value for all submodules is also presented.

N	Performance Indicator	Compared to Conventional Case [%]
5	max $I_{SM}$ [A rms]	97.6
5	mean $I_{SM}$ [A rms]	100.3
20	max $I_{SM}$ [A rms]	97.1
20	mean $I_{SM}$ [A rms]	100.3
30	max $I_{SM}$ [A rms]	96.5
30	mean $I_{SM}$ [A rms]	100.7

. A reduction in the maximum RMS current was identified in all three cases.

A visualization of the RMS current in each submodule is presented in Figure 14a. During power delivery, when $m_i$ is lower than 1, the submodule’s RMS current is zero for some fundamental cycles, which explains the large spread. A decrease in the maximum RMS current for the submodules is identifiable in Figure 14a. The standard deviation of the RMS current in the submodules at each timestep is presented in Figure 14b. The identifiable plateaus are a result of the additional submodules required to meet $V_p$.

The maximum, minimum and mean submodule RMS currents during active power delivery for all cases are presented in Figure 15, with (a) corresponding to N = 5, (b) corresponding to N = 20 and (c) corresponding to N = 30. A detailed view of the case with N = 20 is presented in Figure 16.

3.2. Vertical Voltage Balancing

The vertical voltage balance of the three simulation cases was investigated through the visualization of the DC voltage in each submodule at the end of active power delivery, as presented in Figure 17.

4. Discussion

The duty cycles for the two modulation schemes were derived and are presented in Figure 9, and they are compared to the simulation in Figure 13. The comparison affirms that the assumed behavior of the proposed algorithm is valid and the assumption of EDLC discharge is reasonable.

The simulation experiments demonstrated that, for a 20-submodule (41-level) converter, the peak RMS current was reduced in all simulation cases. The mean RMS current increased slightly when looking at one fundamental cycle; see Table 3. As can be seen in Figure 15, the reduction in the maximum RMS current is clear during active power delivery. The maximum RMS current per submodule increases for the conventional NLM algorithm as the modulation index increases; in turn, the length of the longest duty cycle increases. The proposed NLM scheme does not have the same relationship, and there is a slight decrease in the longest duty cycle and thus the maximum experienced RMS current as the modulation index increases. The proposed balancing algorithm is suitable for this application if dimensioning the converter for an operating case approaching the maximum current capability of the EDLC. The proposed nearest level algorithm reduces the maximum current experienced in the submodules, which may affect the dimensioning criteria.

The sorting algorithm used for the conventional NL presents good vertical voltage balancing, and it is robust and easy to implement. The proposed modulation strategy results in the even discharge of all submodules; however, at the end of power delivery, there is some drift in one of the submodules. The experimental verification of the method and a more in-depth investigation of the method to distribute the voltage vector per phase would be appropriate topics for future research.

While this study has investigated the cascaded H-bridge topology, the modulation scheme is transferable to the modular multilevel converter topology as each half period is studied separately. The separate sorting of the the upper and lower legs is needed in the MMC case. Attention must also be paid to the circulating currents in the arms of the MMC when modifying the algorithm.

Additional future work could include the experimental verification of the simulation results in a laboratory setting, quantifying the conduction losses and temperature increases per submodule. The robustness of the sorting algorithms, as well as the combination with horizontal voltage balancing, is needed for practical implementation. The construction of a prototype is ongoing and will be documented in future studies.

The proposed method is a passive thermal sharing design, as the redistribution algorithm departs from the point at which the voltage reference changes sign. A comparison with active thermal sharing controls, such as in [25], would be a relevant task for future study.

5. Conclusions

The two modulation schemes presented in this work for the direct integration of EDLCs show satisfactory vertical voltage balancing capabilities for the conventional nearest level modulation with the descending sorting algorithm, as well as the proposed nearest level modulation with the sorting and distribution algorithm. The comparison of the distribution of the RMS current in the submodules shows a reduction in the maximum RMS current per submodule over the course of active power delivery, which may decrease the dimensioning current used when designing the converter. For the conventional nearest level modulation scheme, as the modulation index increases, the maximum RMS current per submodule increases. Meanwhile, for the proposed nearest level modulation scheme, it is kept constant.