A Multi-Condition-Based Junction Temperature Estimation Technology for Double-Sided Cooled Insulated-Gate Bipolar Transistor Modules

Abstract

A method considering thermal boundary conditions and thermal coupling effects is proposed to estimate the junction temperature of double-sided cooling insulated-gate bipolar transistor (IGBT) modules. Traditional methods, which rely on negative temperature coefficient (NTC) measurements, often overlook mutual thermal interactions among chips, leading to inaccuracies under varying cooling boundary conditions. In this paper, a Foster thermal network model incorporating chip thermal coupling is developed to estimate the junction temperature of double-sided cooling IGBT power modules. The thermal model parameters are extracted through a combination of finite element simulation and experimental analysis. The effects of different cooling boundary conditions on the thermal model and the module’s heat channeling behavior are examined, and compensation strategies for various cooling boundaries are proposed. Experimental and simulation results indicate that the estimated junction temperature error of the proposed method remains within 5 °C under different operating conditions.

1. Introduction

The insulated-gate bipolar transistor (IGBT) is extensively utilized in electrified vehicles, wind turbine generators, railway transit, and other advanced power electronics applications. Compared to traditional single-sided cooling power modules, double-sided cooling power modules offer superior cooling capabilities and lower parasitic parameters [1]. The adoption of double-sided cooling modules enhances the efficiency, power density, and reliability of vehicle motor controllers, gradually drawing attention from both the academia and the industry. Although internationally renowned manufacturers such as Toyota [2], General Motors (GM) [3], and Infineon [4] have successfully deployed double-sided cooling IGBT devices, studies on junction temperature estimation for these modules remain limited.

Currently, four typical methods are used for junction temperature measurement and estimation in single-sided heat dissipation systems, based on physical contact measurement [5], optical non-contact measurement [6], thermal-sensitive electrical parameter (TSEP) method [7], and thermal resistance model estimation [8,9,10]. The first two methods compromise the module’s original packaging structure, making them suitable only for laboratory verification and offline testing rather than industrial applications [11]. The thermal-sensitive electrical parameter method determines the junction temperature of a chip based on on-state voltage (Vce) [12], short-circuit current [13], turn-on time [14], turn-off time [15], and other temperature-sensitive electrical parameters. However, this method is limited by its complex circuit design, susceptibility to electromagnetic interference, and equipment noise, which constrain its practical applications [16]. Additionally, numerical calculation methods, such as the finite element method (FEM) [17], finite difference method (FDM) [18], and finite volume method (FVM) [19], have been widely employed to analyze the thermal behavior of IGBT modules. Although these methods provide high accuracy in thermal simulations, their substantial computational complexity and long processing time render them unsuitable for real-time temperature estimation. To address this limitation, Feng [20] proposed a three-dimensional, fast temperature field prediction model based on the improved POD–Galerkin method, significantly reducing computational time while maintaining accurate temperature predictions for IGBT modules. However, the accuracy and efficiency of this model depend on the comprehensiveness of the snapshots generated using FVM, and complex operating conditions may further increase the computational burden in the initial stages.

The thermal network model is the primary method for the real-time junction temperature monitoring of IGBT modules and can be categorized into the Foster model [21] and the Cauer model [22]. Based on the loss information of an IGBT module, the junction temperature can be readily determined using thermal impedance, represented as a one-dimensional RC network. However, the parameters of the thermal network model are influenced by boundary conditions [23] and thermal coupling between chips [24], while the parameter extraction process remains complex. Yang [25] introduced a temperature-dependent Cauer thermal network model in which finite element analysis was employed to simulate the heat flow distribution of IGBT modules. The effective heat transfer area of each layer was calculated analytically to extract temperature-dependent thermal parameters with high accuracy, significantly reducing computational time and simplifying parameter extraction. Lu [26] proposed a three-dimensional Cauer thermal network model that incorporates the temperature dependence of constituent materials, effectively capturing the impact of material temperature on thermal parameters. Bahman [27] introduced a lumped 3D thermal model that accounts for the thermal coupling effect between different chips, while Heng [28] developed a novel 3D physical RC network model capable of accurately reflecting the temperature distribution at critical locations within IGBT chips by considering temperature effects and non-uniform power loss distribution. Although extensive research has focused on advanced thermal models for single-sided IGBT modules, relatively few studies address junction temperature estimation in double-sided IGBT modules. The application of complex thermal models to double-sided modules introduces additional challenges in modeling and parameter extraction, making practical implementation difficult. Furthermore, most existing studies focus on individual IGBT modules, overlooking the heat channeling effect between multiple IGBT modules.

In this paper, a Foster thermal network model based on coolant temperature is proposed for the electric vehicle motor controller. The model accounts for the thermal coupling effect among four chips within the same phase arm and adapts to varying cooling conditions. First, a chip power loss calculation model is developed, where power loss is determined using a lookup table generated offline and electrical parameters provided online. Next, the temperature difference between the chip and the reference temperature is computed using a thermal resistance model that incorporates both thermal coupling and cooling conditions. Finally, the reference temperature of the IGBT module is adjusted based on the cooling boundary to mitigate the impact of inter-IGBT module heat channeling on junction temperature estimation. This method offers a simplified modeling and parameter extraction process while ensuring accurate junction temperature estimation under diverse and complex operating conditions, making it highly suitable for industrial applications.

2. System Model Construction

2.1. IGBT Power Loss Model

The heat loss in the IGBT module primarily arises from the IGBT power transistor and the freewheeling diode [29], including IGBT conduction loss, IGBT switching loss, diode conduction loss, and diode reverse recovery loss. The IGBT can be modeled as a PiN diode and a MOSFET operating in series in the linear region. Thus, the on-state voltage drop of the IGBT is the sum of the voltage drops across the PiN diode and the MOSFET. The voltage drop is calculated as follows:

$${\mathrm{V}}_{\mathrm{F},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}={\mathrm{V}}_{\mathrm{F},\mathrm{M}\mathrm{O}\mathrm{S}\mathrm{F}\mathrm{E}\mathrm{T}}+{\mathrm{V}}_{\mathrm{F},\mathrm{P}\mathrm{i}\mathrm{N}}$$

(1)

$${\mathrm{V}}_{\mathrm{F},\mathrm{M}\mathrm{O}\mathrm{S}\mathrm{F}\mathrm{E}\mathrm{T}}={\mathrm{I}}_{\mathrm{C}}{\mathrm{R}}_{\mathrm{C}\mathrm{H}}$$

(2)

$${\mathrm{V}}_{\mathrm{F},\mathrm{P}\mathrm{i}\mathrm{N}}={\displaystyle \frac{2\mathrm{k}{\mathrm{T}}_{\mathrm{j}}}{\mathrm{q}}}\ln {\displaystyle \frac{{\mathrm{J}}_{\mathrm{c}}{\mathrm{W}}_{\mathrm{N}}}{4\mathrm{q}{\mathrm{D}}_{\mathrm{a}}{\mathrm{n}}_{\mathrm{i}}\mathrm{F}\frac{{\mathrm{W}}_{\mathrm{N}}}{2{\mathrm{L}}_{\mathrm{a}}}}}$$

(3)

where ${\mathrm{V}}_{\mathrm{F},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}$, ${\mathrm{V}}_{\mathrm{F},\mathrm{M}\mathrm{O}\mathrm{S}\mathrm{F}\mathrm{E}\mathrm{T}}$, and ${\mathrm{V}}_{\mathrm{F},\mathrm{P}\mathrm{i}\mathrm{N}}$ represent the forward voltage drop of IGBT, MOSFET, and PiN diode respectively; ${\mathrm{I}}_{\mathrm{C}}$ represents the collector current, ${\mathrm{R}}_{\mathrm{C}\mathrm{H}}$ represents the internal resistance, k represents the Boltzmann coefficient, ${\mathrm{T}}_{\mathrm{j}}$ represents the junction temperature of the IGBT, q represents the charge constant, and ${\mathrm{J}}_{\mathrm{c}}$ represents the collector current surface density. ${\mathrm{W}}_{\mathrm{N}}$ for drift zone width, ${\mathrm{D}}_{\mathrm{a}}$ for the bipolar diffusion coefficient, ${\mathrm{n}}_{\mathrm{i}}$ for intrinsic carrier density, ${\mathrm{L}}_{\mathrm{a}}$ for bipolar diffusion length.

Equations (1)–(3) can help to understand the relationship between voltage drop, current, and temperature. Figure 1a shows the typical conduction characteristic curve of the IGBT. At a high current, the MOSFET voltage drop dominates, resulting in a linear relationship between current and voltage. At low current, the PiN diode voltage drop dominates, leading to an exponential relationship between current and voltage. In terms of temperature, carrier drift motion predominates at a high current. As temperature increases, carrier mobility decreases, causing an increase in on-resistance and a positive temperature coefficient. At low current, PiN minority carrier expansion dominates, and diffusion is enhanced by rising temperature, which reduces the conduction voltage drop and results in a negative temperature coefficient. Figure 1b shows the typical conduction characteristic curve of the diode, which exhibits a negative temperature coefficient at both high and low currents. Figure 1c,d presents the switching loss curves for the IGBT and the diode, respectively. The relationship between switching loss and current is nonlinear, and the power loss increases with the device junction temperature.

Currently, the common conduction loss model uses linear fitting to approximate the relationship between current and voltage at high currents, which speeds up the calculation. However, since the temperature impact on conduction characteristics is nonlinear at different currents, linear fitting causes loss distortion at low currents. Therefore, a lookup table is used to obtain the required on-state loss and switching loss. The IGBT and diode losses in the loss model are calculated as follows:

$${\mathrm{P}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}=\mathrm{d}\mathrm{u}\mathrm{t}\mathrm{y}·{\mathrm{P}}_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}}+{\mathrm{f}}_{\mathrm{s}\mathrm{w}}·{(\mathrm{E}}_{\mathrm{o}\mathrm{n}}+{\mathrm{E}}_{\mathrm{o}\mathrm{f}\mathrm{f}})$$

(4)

$${\mathrm{P}}_{\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}=\mathrm{d}\mathrm{u}\mathrm{t}\mathrm{y}·{\mathrm{P}}_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}}+{\mathrm{f}}_{\mathrm{s}\mathrm{w}}·{\mathrm{E}}_{\mathrm{r}\mathrm{r}}$$

(5)

where duty represents the duty cycle, ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}$ represents the switching frequency, ${\mathrm{P}}_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}}$ represents the on-state loss of the IGBT or diode, and ${\mathrm{E}}_{\mathrm{o}\mathrm{n}}$ and ${\mathrm{E}}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ represent the on-state and off-state losses of the IGBT, respectively. ${\mathrm{E}}_{\mathrm{r}\mathrm{r}}$ represents the reverse recovery loss of the diode. The on-state and off-state losses of the device under different currents and temperatures can be obtained using static test equipment, and the on-state loss lookup table can be generated through double-pulse testing. During the online operation of the loss model, the transient loss value can be obtained by using the lookup table generated offline.

2.2. Thermal Network Model

Figure 2 shows the structure of a 750 V/600 A three-phase double-sided power module sandwiched between two heatsinks. Double-sided package modules enhance the electrical and mechanical properties of single-sided package modules [30]. This design reduces the thermal resistance and the stray inductance of the power module while also decreasing its volume and mass.

Single-sided package modules typically feature only one cooling boundary, resulting in a relatively straightforward heat dissipation path. In contrast, double-sided cooling (DSC) modules possess two distinct heat transfer paths, which are coupled simultaneously, leading to different boundary conditions. In the modeling process, the dual-channel heat transfer path of a DSC power module is often simplified into a parallel single-channel heat transfer path. The thermal network model is then established, with the thermal resistance of the two heat transfer channels obtained through two independent tests [31,32]. However, unlike single-sided cooling modules, the two heat transfer channels of DSC modules are not fully decoupled, causing the dual-channel thermal resistance to deviate from the parallel combination of the two single-channel thermal resistances, which introduces significant transient thermal resistance errors. Nonetheless, under ideal conditions, the heat flow ratio on both sides of the double-sided cooling module is unaffected by boundary conditions such as coolant flow and temperature. Therefore, a single Foster model can be used to model the double-sided cooling IGBT module.

The thermal impedance between the junction temperature and the reference point temperature can be expressed as follows:

$${\mathrm{Z}}_{\mathrm{t}\mathrm{h}}=\sum _{\mathrm{n}=1}^{\mathrm{N}}{\mathrm{R}}_{\mathrm{n}}·(1-{\mathrm{e}}^{-\mathrm{t}/\tau })$$

(6)

$${\mathrm{T}}_{\mathrm{j}}\left(\mathrm{t}\right)={\mathrm{Z}}_{\mathrm{t}\mathrm{h}}·\mathrm{P}\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}\left(\mathrm{t}\right)+{\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}$$

(7)

where ${\mathrm{Z}}_{\mathrm{t}\mathrm{h}}$ represents the total thermal impedance, ${\mathrm{R}}_{\mathrm{n}}$ represents the n-th order thermal resistance, $\tau$ = ${\mathrm{R}}_{\mathrm{n}}·{\mathrm{C}}_{\mathrm{n}}$ represents the n-th order time constant, ${\mathrm{C}}_{\mathrm{n}}$ represents the n-th order heat capacity. Taking the fourth-order RC model as an example, with chip loss $\mathrm{P}\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}$ and reference temperature ${\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}$, the equation for estimating the junction temperature of a single chip can be written as follows:

$${\displaystyle \frac{\mathrm{d}∆\mathrm{T}}{\mathrm{d}\mathrm{t}}}=\mathrm{A}∆\mathrm{T}+\mathrm{B}\mathrm{U}$$

$${\mathrm{T}}_{\mathrm{j}}=\mathrm{C}∆\mathrm{T}+\mathrm{D}\mathrm{U}$$

$$∆\mathrm{T}=\left[\begin{array}{c}{∆\mathrm{T}}_1\\ {∆\mathrm{T}}_2\\ {∆\mathrm{T}}_3\\ {∆\mathrm{T}}_4\end{array}\right], \mathrm{U}=\left[\begin{array}{c}{\mathrm{P}}_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}\\ {\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}\end{array}\right]$$

$$\mathrm{A}=\left[\begin{array}{cccc}-{\displaystyle \frac{1}{{\tau }_1}}& 0& 0& 0\\ 0& -{\displaystyle \frac{1}{{\tau }_2}}& 0& 0\\ 0& 0& -{\displaystyle \frac{1}{{\tau }_3}}& 0\\ 0& 0& 0& -{\displaystyle \frac{1}{{\tau }_4}}\end{array}\right],\mathrm{B}=\left[\begin{array}{cc}{\displaystyle \frac{1}{{\mathrm{C}}_1}}& 0\\ {\displaystyle \frac{1}{{\mathrm{C}}_1}}& 0\\ {\displaystyle \frac{1}{{\mathrm{C}}_1}}& 0\\ {\displaystyle \frac{1}{{\mathrm{C}}_1}}& 0\end{array}\right]$$

$$\mathrm{C}=\left[\begin{array}{cccc}1& 1& 1& 1\end{array}\right],\mathrm{D}=\left[\begin{array}{cc}0& 1\end{array}\right]$$

(8)

where A and B are the system matrix and input matrix; C and D are the output matrix and the feed matrix, respectively. ΔT represents the temperature rise of the chip, and Tn is the temperature rise corresponding to the n-th order RC. The formula can be discretized as follows:

$$∆{\mathrm{T}}_{\mathrm{n}}(\mathrm{k})=(∆{\mathrm{T}}_{\mathrm{n}}(\mathrm{k}-1)·{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{n}}}}})+{\mathrm{R}}_{\mathrm{n}}\mathrm{P}(\mathrm{k})·(1-{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{n}}}}})$$

(9)

$${\mathrm{T}}_{\mathrm{j}}(\mathrm{k})={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}+\sum _1^{\mathrm{N}}∆{\mathrm{T}}_{\mathrm{n}}(\mathrm{k})$$

(10)

where k represents the current time step, k – 1 represents the previous time step, and Δt is the sampling step in time.

The junction temperature calculated using this formula only considers the heating of a single chip. However, in a traction inverter, the IGBT module is typically packaged in a 6-in-1 configuration, meaning multiple chips would generate losses during operation. The thermal coupling effect between different chips leads to a higher temperature rise for chips operating simultaneously compared to a single chip operating alone [33]. Figure 3 illustrates the chip distribution in a three-phase inverter. When calculating the junction temperature of a switch, it is necessary to account for the influence of adjacent IGBTs and diodes within the same phase, as well as the thermal coupling effects between different phases.

To address the thermal coupling of the chips packaged in the same power module, a thermal network model is established for four chips, considering the coupling between adjacent chips. Figure 4 illustrates the equivalent thermal resistance network, accounting for the thermal coupling between the four chips within the same phase-leg. P_IGBT1, P_Diode1, P_IGBT2, and P_Diode2 represent the loss values for the upper arm IGBT, upper arm diode, lower arm IGBT, and lower arm diode, respectively. T_IGBT1, T_Diode1, T_IGBT2, and T_Diode2 represent the junction temperatures of these four chips. Z_ij denotes the thermal impedance between chips I and j. When i and j are the same, it indicates self-thermal resistance; meanwhile, when i and j are different, it indicates coupling thermal resistance. Each Z_ij consists of a fourth-order RC model. The junction temperature of a chip can thus be calculated based on the losses of the four chips and the thermal resistance parameters between these chips. While a thermal network model can also be constructed to represent the thermal coupling between different phases by considering all 12 chips in a three-phase inverter, this method is more complex, requiring more parameters and increasing computational load. Since the mutual thermal influence between different phases is relatively small, and the inverter typically operates in a three-phase balanced state, it is sufficient to apply the thermal resistance parameters obtained for each phase collectively.

Thermal resistance parameters can be obtained using the finite element method and thermal resistance bench testing. The loss P1 is applied to the three upper bridge arm IGBTs, corresponding to the three phases. By analyzing the transient change in the junction temperature of the upper bridge arm IGBT, the self-heating impedance curve Z₁₁(t) can be derived. From the temperature transient response curves of the other three chips, the coupled thermal impedance curves—Z₂₁(t), Z₃₁(t), and Z₄₁(t)—representing the thermal impedance between the upper bridge IGBT and the other three chips can be obtained. Repeating this procedure allows the self-thermal resistance and coupling thermal resistance of all four chips to be calculated. The thermal impedance is expressed as follows:

$${\mathrm{Z}}_{\mathrm{i}\mathrm{j}}(\mathrm{t})={\displaystyle \frac{{\mathrm{T}}_{\mathrm{j}\_\mathrm{i}\mathrm{j}}(\mathrm{t})-{\mathrm{T}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{P}}_{\mathrm{j}}}}$$

(11)

where ${\mathrm{Z}}_{\mathrm{i}\mathrm{j}}(\mathrm{t})$ represents the thermal impedance response of the j-th chip to the i-th chip, ${\mathrm{T}}_{\mathrm{j}\_\mathrm{i}\mathrm{j}}$ is the junction temperature of the upper bridge arm IGBT during the i-th test, ${\mathrm{P}}_{\mathrm{j}}$ is the loss value of the j-th chip, and ${\mathrm{T}}_{\mathrm{r}\mathrm{e}\mathrm{f}}$ represents the reference temperature. Each Zth can be fitted into a multi-order RC model based on the transient thermal resistance curve. Using this, the steady-state junction temperature of the upper bridge arm IGBT can be expressed as follows:

$${\mathrm{T}}_{\mathrm{i}}={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}+({\mathrm{Z}}_{11}·{\mathrm{P}}_1+{\mathrm{Z}}_{12}·{\mathrm{P}}_2+{\mathrm{Z}}_{13}·{\mathrm{P}}_3+{\mathrm{Z}}_{14}·{\mathrm{P}}_4)$$

(12)

where ${\mathrm{T}}_{\mathrm{i}}$ represents the estimated junction temperature of chip i. By extending this formula to the four chips in the same phase, we can derive the thermal resistance network matrix that incorporates thermal coupling. The corresponding junction temperature formula is expressed as:

$$\left[\begin{array}{c}{\mathrm{T}}_1\\ {\mathrm{T}}_2\\ {\mathrm{T}}_3\\ {\mathrm{T}}_4\end{array}\right]={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}+\left[\begin{array}{cccc}{\mathrm{Z}}_{11}& {\mathrm{Z}}_{12}& {\mathrm{Z}}_{13}& {\mathrm{Z}}_{14}\\ {\mathrm{Z}}_{21}& {\mathrm{Z}}_{22}& {\mathrm{Z}}_{23}& {\mathrm{Z}}_{24}\\ {\mathrm{Z}}_{31}& {\mathrm{Z}}_{32}& {\mathrm{Z}}_{33}& {\mathrm{Z}}_{34}\\ {\mathrm{Z}}_{41}& {\mathrm{Z}}_{42}& {\mathrm{Z}}_{43}& {\mathrm{Z}}_{44}\end{array}\right]·\left[\begin{array}{c}{\mathrm{P}}_1\\ {\mathrm{P}}_2\\ {\mathrm{P}}_3\\ {\mathrm{P}}_4\end{array}\right]$$

(13)

Combining Equations (9) and (13), the discretized junction temperature can be calculated as follows:

$${\mathrm{T}}_{\mathrm{j}}\_\mathrm{i}(\mathrm{k})={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}(\mathrm{k})+∆$$

(14)

$$∆\mathrm{T}\_\mathrm{i}(\mathrm{k})=\sum _{\mathrm{j}=1}^4∆\mathrm{T}\_\mathrm{i}\mathrm{j}(\mathrm{k})$$

(15)

$$∆\mathrm{T}\_\mathrm{i}\mathrm{j}(\mathrm{k})=\sum _{\mathrm{n}=1}^4∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k})$$

(16)

$$∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k})=∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k}-1)·{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}}+{\mathrm{R}}_{\mathrm{i}\mathrm{j}\mathrm{n}}·{\mathrm{P}}_{\mathrm{j}}(\mathrm{k})·(1-{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}})$$

(17)

where i represents the i-th chip, j represents the j-th chip thermally coupled with i-th chip, and n denotes the n-th order RC parameter. ${\mathrm{R}}_{\mathrm{i}\mathrm{j}\mathrm{n}}$ corresponds to the thermal resistance of order n, and ${\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}$ represents the associated time constant. $∆\mathrm{T}\_\mathrm{i}$ indicates the temperature rise of chip i, $∆\mathrm{T}\_\mathrm{i}\mathrm{j}$ represents the temperature rise of chip i caused by chip j, and $∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}$ denotes the n-th order component of the temperature rise caused by chip j to chip i. Thus, the junction temperature calculation formula can be expressed in the following form:

$$\begin{gathered} {\mathrm{T}}_{\mathrm{j}}\_\mathrm{i}(\mathrm{k})={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}(\mathrm{k})+\sum _{\mathrm{j}=1}^4\sum _{\mathrm{i}=1}^4(∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k})) \\ ={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}(\mathrm{k})+\sum _{\mathrm{j}=1}^4\sum _{\mathrm{i}=1}^4(∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k}-1)·{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}}+{\mathrm{R}}_{\mathrm{i}\mathrm{j}\mathrm{n}}·{\mathrm{P}}_{\mathrm{j}}(\mathrm{k})·(1-{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}})) \end{gathered}$$

(18)

2.3. Model Optimization Considering Cooling Conditions

The boundary conditions of the power module vary during the actual operation of the motor controller. Since thermal resistance models differ under various cooling boundary conditions, it is essential to compensate for thermal resistance based on the prevailing cooling boundary conditions.

The schematic diagram of a three-phase inverter and its cooling water channel is shown in Figure 5. Theoretically, the extracted thermal resistance represents the resistance between the module and the temperature of the water channel directly below it. However, during actual operation, the water temperature increases along the channel, resulting in the outlet temperature ${\mathrm{T}}_{\mathrm{o}\mathrm{u}\mathrm{t}}$ being higher than the inlet temperature ${\mathrm{T}}_{\mathrm{i}\mathrm{n}}$. It can be approximated that the water temperature at the U-phase ${\mathrm{T}}_{\mathrm{u}}$ is roughly equal to the inlet temperature ${\mathrm{T}}_{\mathrm{i}\mathrm{n}}$, and the W-phase water temperature ${\mathrm{T}}_{\mathrm{w}}$ is approximately equal to the outlet temperature ${\mathrm{T}}_{\mathrm{o}\mathrm{u}\mathrm{t}}$. Using ${\mathrm{T}}_{\mathrm{i}\mathrm{n}}$ as a uniform reference temperature would underestimate the estimated temperature of the W-phase. To address this, compensation is acquired by calculating the temperature difference across the water channel based on the inlet temperature and flow rate ${\mathrm{F}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}$. The temperature difference is calculated as follows:

$$∆{\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}={\mathrm{T}}_{\mathrm{o}\mathrm{u}\mathrm{t}}-{\mathrm{T}}_{\mathrm{i}\mathrm{n}}(\mathrm{k})={\displaystyle \frac{{\mathrm{P}}_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}}{\mathrm{c}·\rho ·{\mathrm{F}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}}}$$

(19)

where $∆{\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}$ represents the temperature difference between the inlet and outlet, ${\mathrm{P}}_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}$ denotes the total system loss, c is the specific heat capacity of the coolant, and $\rho$ is the coolant density. During operation, the software calculates the real-time inlet-outlet temperature difference based on the actual system loss and flow rate. Using the computed temperature difference, the reference temperature for each phase is adjusted accordingly to ensure accurate thermal compensation.

Additionally, the thermal resistance parameters are influenced by the cooling boundary conditions. Typically, lower flow rates lead to higher thermal resistance. As a result, the thermal resistance matrix must be adjusted according to the cooling conditions.

In summary, the overall estimation model is depicted in Figure 6. The offline parameter acquisition process consists of two parts: the loss parameters are obtained through a double-pulse test, and the loss calculation model is introduced. Additionally, finite element simulations and thermal resistance bench tests are used to determine the thermal resistance matrix parameters, which are then incorporated into the thermal network model. During operation, the loss calculation model computes the transient loss value based on the input electrical parameters and the feedback junction temperature. The model then calculates the flow-compensated thermal resistance and the reference temperature for each phase, considering the cooling boundary conditions. Finally, the thermal network model estimates the junction temperature based on the input loss and reference temperature.

3. Parameter Acquisition and Experimental Verification

3.1. Loss Parameter Acquisition

Based on the previous analysis, the loss calculation module must first obtain the on-state and switching losses of the IGBTs and diodes offline. Figure 7 illustrates the 3D loss lookup chart derived from the double-pulse test. As shown in the figure, the relationship between the actual loss, junction temperature, and current aligns with the theoretical analysis. All losses are proportional to the current. The IGBT on-loss is inversely proportional to temperature at low currents and directly proportional to temperature at high currents. Diode conduction loss is consistently inversely proportional to temperature. The transient on-loss of the power module can be calculated based on the current and junction temperature during operation. Switching loss, however, is not only dependent on current and junction temperature but is also proportional to the bus voltage. Therefore, after calculating the switching loss, it must be adjusted according to the bus voltage.

3.2. Obtain Thermal Resistance Parameters Using the Finite Element Method

For the thermal network model to be accurate, the thermal resistance parameter is one of the most important parameters to obtain. Thermal resistance parameters can be obtained based on the finite element simulation method mentioned above. In order to improve the accuracy of thermal resistance parameters, a thermal resistance parameter extraction method combining a finite element simulation and bench test is proposed in this paper. Bench testing is highly reliable and can be used to validate the accuracy of finite element models. Finite element simulations provide high flexibility and strong repeatability, allowing thermal resistance values under different conditions to be efficiently and repeatedly simulated by adjusting the model’s parameters and boundary conditions. Additionally, finite element simulations can assist in verifying the accuracy of junction temperature estimation. The time cost for a single finite element simulation is approximately 30 min. The thermal network model in MATLAB software (R2023a) takes about 5 s to run once, demonstrating favorable convergence properties.

The high-level flowchart is shown in Figure 8 and can be divided into three main steps. First, a thermal model is constructed based on the material parameters using commercial finite element simulation software. The self-thermal resistance and coupling thermal resistance parameters are then derived using the injection loss method. Next, the thermal resistance values of the module are measured using a thermal resistance test bench, and the finite element simulation thermal model is optimized based on the measured results until the simulation outputs align closely with the experimental data. Finally, the thermal model is adjusted to account for varying operational and cooling conditions by comparing the measured junction temperature with the temperature estimated by the thermal model.

Figure 9a presents the three-dimensional structure diagram of the finite element simulation corresponding to the three-phase inverter.

Table 1. Finite element model material settings.

Layer	Material	Thickness (mm)	Density (g/cm3)	Thermal Conductivity (W/m*K)	Specific Heat (J/g*K)
Outer_baseplate	Al3003	\	2.74	160	0.893
Outer_TIM	TIM	0.15	2.70	2.2	0.800
Outer_Cu1	Cu	0.40	8.96	380	0.381
Outer_Ceramic	ZTA	0.32	4.00	20	0.720
Outer_Cu2	Cu	0.30	8.96	380	0.381
Spacer_solder1	SnSb5	0.10	7.40	55	0.230
Spacer	WCu	2.32	15.5	200	0.170
Spacer_solder2	SnSb5	0.10	7.40	55	0.230
Chip	Si	0.08	2.33	98.9	0.741
Chip_solder	SnSb5	0.1	7.40	55	0.230
Inner_Cu2	Cu	0.30	8.96	380	0.381
Inner_Ceramic	ZTA	0.32	4.00	20	0.720
Inner_Cu1	Cu	0.40	8.96	380	0.381
Inner_TIM	TIM	0.15	2.70	2.2	0.800
Inner_baseplate	Al6063	\	2.72	200	0.896
	Al6061	\	2.72	155	0.896

shows the material settings for finite element modeling. The boundary conditions are set as a 65 °C water temperature, an 8 L/min flow rate, and an average convective heat transfer coefficient of 4000 W/m²·K. The self-thermal resistance and coupling thermal resistance for each chip were determined by sequentially allocating power losses to the four chips.

Figure 9b shows the thermal cloud image when a 300 W loss is injected into the upper bridge arm IGBT. From the figure, it can be observed that the adjacent upper bridge arm diode exhibits a significant temperature rise, while the temperature rise in the IGBT and diode of the lower bridge arm is less pronounced. The corresponding thermal impedance value can be derived from the temperature response curve.

Figure 10 illustrates the temperature response curve and the corresponding self-thermal resistance curve for the IGBT in the bridge arm. The coupling thermal resistance between the IGBT and the adjacent diode is relatively large, while the coupling thermal resistance between the IGBT and the diode of the opposite bridge arm is smaller. The fourth-order RC parameters can be obtained through curve fitting, as shown in Table 1. From the data, it is evident that the first two thermal resistance values (Rth) of the coupling thermal resistance are quite small, suggesting a slow thermal coupling response of the chip. Therefore, the smaller two orders of the time constant in the coupling thermal resistance can be neglected, which also reduces the computational load of the model.

Table 2. Thermal impedance matrix parameters.

	Top IGBT		Top Diode		Bot IGBT		Bot Diode
Top IGBT	Rth	τ	Rth	τ	Rth	τ	Rth	τ
	0.03845	0.00145	4.3 × 10−7	0.01	4.32 × 10−7	0.009	3.5 × 10−6	0.009
	0.07424	0.03788	7 × 10−13	0.1	3.9 × 10−10	0.1	3.8 × 10−9	0.099
	0.0678	0.2306	0.006412	0.2228	0.001734	1	0.001429	1
	0.1126	1	0.04212	1.532	0.004806	3.427	0.003774	3.278
Top Diode	Rth	τ	Rth	τ	Rth	τ	Rth	τ
	9.6 × 10−7	0.009	0.01875	0.00165	5.42 × 10−7	0.009	4.51 × 10−6	0.009
	9 × 10−12	0.099	0.05987	0.04122	4.2 × 10−10	0.099	3.84 × 10−9	0.1
	0.05146	0.214	0.05789	0.2106	0.002834	1	0.002697	1
	0.00668	1.689	0.1014	1	0.003786	3.326	0.004884	3.297
Bot IGBT	Rth	τ	Rth	τ	Rth	τ	Rth	τ
	5.03 × 10−7	0.01	7.1 × 10−7	0.01	0.02978	0.00201	7.8 × 10−12	0.009
	6.4 × 10−11	0.1	4.6 × 10−13	0.1	0.07945	0.04013	4.5 × 10−9	0.099
	0.00198	1	0.002812	1	0.06124	0.2256	0.002189	0.1947
	0.00765	3.147	0.003179	3.332	0.1269	1	0.04134	1.624
Bot Diode	Rth	τ	Rth	τ	Rth	τ	Rth	τ
	6.5 × 10−8	0.01	6.14 × 10−6	0.01	7.7 × 10−12	0.009	0.02812	0.00171
	5.6 × 10−11	0.1	7.4 × 10−11	0.1	6.34 × 10−9	0.099	0.06478	0.03325
	0.00151	1	0.00478	1	0.001364	0.2023	0.04215	0.2314
	0.00319	3.049	0.00115	3.198	0.004145	1.678	0.1098	1

represents a 4 × 4 order thermal impedance matrix. Each thermal impedance in the table is composed of a fourth-order thermal resistance and time constant, and each thermal impedance corresponds to Zij in Figure 4.

3.3. Thermal Resistance Test Platform Modified Thermal Model

The accuracy of the thermal resistance obtained through finite element simulation depends on the precision of the simulation model. Therefore, it is necessary to verify whether the junction temperature estimation model meets the required accuracy. This can be achieved by validating the simulation model and thermal resistance parameters using a thermal resistance test bench.

The thermal resistance test in this study primarily employs the TSEP method. As shown in Formula 1, when the IGBT is switched on at a high current, the first term in the voltage drop formula dominates. At a low current (100 mA), the first term becomes negligible, and the second term prevails, causing the IGBT collector current to increase exponentially with the on-voltage drop. In this scenario, the relationship between the saturation voltage drop UCE and junction temperature Tj is approximately negative. This principle forms the basis of the junction temperature estimation method using the saturation voltage UCE as the thermally sensitive electrical parameter. However, since this method requires disconnecting the load current, it is not suitable for online junction temperature measurement and is typically used for offline testing.

Figure 11 shows the thermal resistance test bench and the IGBT module to be tested. The junction temperature of the chip is obtained using the TSEP method, and the thermal resistance value of the module can be calculated according to the junction temperature. Different coolant temperatures and flow rates can be set through the water channel. Figure 12 illustrates the circuit diagram for measuring the junction temperature thermal resistance using the low-current saturation voltage drop method. The device under test (DUT) is the switching device being evaluated. Initially, the power module is passively heated by increasing the coolant temperature, while a constant test current Ic1 is supplied to the module. The low-current saturation voltage drop is then measured at various temperatures, from which the calibration curve and the K coefficient are derived.

Next, the device is heated using a high current Ic2, and the junction temperature is adjusted by varying the current. The case temperature ${\mathrm{T}}_{\mathrm{c}}$ is dynamically observed and recorded until it stabilizes, at which point the pressure drop ${\mathrm{V}}_{\mathrm{c}\mathrm{e}}$ is recorded. The high current $\mathrm{I}\mathrm{c}2$ is then disconnected by the switch at time ton, and the pressure drop and shell temperature variations during the cooling process are recorded in real time. Finally, the junction temperature ${\mathrm{T}}_{\mathrm{j}}$ is calculated using the K coefficient. Figure 13 illustrates the current and temperature curves for the test process. The thermal impedance is then calculated as follows:

$${\mathrm{Z}}_{\mathrm{t}\mathrm{h}}(\mathrm{t})={\displaystyle \frac{{\mathrm{T}}_{\mathrm{j}}(\mathrm{t})-{\mathrm{T}}_{\mathrm{c}}(\mathrm{t})}{{\mathrm{P}}_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}}}={\displaystyle \frac{{\mathrm{T}}_{\mathrm{j}}(\mathrm{t})-{\mathrm{T}}_{\mathrm{c}}(\mathrm{t})}{{\mathrm{V}}_{\mathrm{c}\mathrm{e}}\mathrm{I}\mathrm{c}2}}$$

(20)

The accuracy of the finite element thermal model can be validated by comparing the thermal resistance parameters obtained from the thermal resistance bench with those from the simulation. The steady-state thermal resistance deviation between the simulation and measurement is within 1.5%, indicating the high accuracy of the thermal resistance parameters.

3.4. Cooling Condition-Based Thermal Resistance Parameters Compensation

The influence of cooling boundary conditions on the thermal network cannot be overlooked. Thermal resistance test data under different cooling conditions can be obtained using a combination of simulation and experiment. Figure 14 presents the thermal resistance test curves at different water temperatures and flow rates. As shown in Figure 14a, the self-thermal resistance varies with flow rates, with the impact most evident in the steady state (where the time constant is large). As flow velocity increases, the system reaches a steady state more quickly, and the steady thermal resistance decreases. The coupling thermal resistance between the IGBT and adjacent diodes at different flow rates follows a similar trend as the self-thermal resistance. Figure 14b shows that the thermal resistance decreases only slightly with increasing temperature, and the effect on the final estimated junction temperature is almost negligible. Therefore, the influence of water temperature can be neglected in the subsequent analysis.

Figure 15 illustrates the variation in thermal resistance at different water flow rates. R11 represents the relationship between the steady-state self-thermal resistance and flow rate of the IGBT on the bridge. R21, R31, and R41 represent the relationships between the steady-state coupling thermal resistances and flow for the upper bridge IGBT to the upper bridge diode, as well as the lower bridge IGBT to the lower bridge diode, respectively. The figure shows that the change in steady-state thermal resistance across different water flows can be approximately linearized within a small range.

Based on the previous conclusion that the influence of the flow rate on thermal resistance is primarily observed in the steady state, the model can be compensated for the term with the largest time constant in the fourth-order RC thermal resistance model. This term, which is most affected by the coolant flow rate, is also the one located closest to the coolant. Figure 16 illustrates the self-thermal resistance network after compensating for cooling conditions. Here, Rn and ${\mathrm{C}}_{\mathrm{n}}$ represent the n-th steady-state thermal resistance and heat capacity values, with C4 corresponding to the term with the highest time constant. A thermal resistance compensation term ${\mathrm{R}}_{\mathrm{c}\mathrm{m}\mathrm{p}}$, calculated based on the coolant flow rate, is added to the fourth-order thermal resistance R4. The value of ${\mathrm{R}}_{\mathrm{c}\mathrm{m}\mathrm{p}}$ can be obtained using steady-state thermal resistance values at different flow rates. Consequently, the temperature rise of the chip can be expressed as the sum of the chip’s heating temperature rise and the flow compensation temperature rise. After corrections to Equations (17) and (18), the junction temperature calculation formula can be expressed as follows:

$$\begin{gathered} {{\mathrm{T}}_{\mathrm{j}}}_{\mathrm{i}}\left(\mathrm{k}\right)={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}\left(\mathrm{k}\right)+\sum _{\mathrm{j}=1}^4\left(∆{\mathrm{T}}_{\mathrm{i}}\mathrm{j}\left(\mathrm{k}\right)+∆{{\mathrm{T}}_{\mathrm{i}}\mathrm{j}}_{\mathrm{c}\mathrm{m}\mathrm{p}}\left(\mathrm{k}\right)\right) \\ ={\mathrm{T}}_{\mathrm{c}\mathrm{o}\mathrm{o}\mathrm{l}}(\mathrm{k})+\sum _{\mathrm{j}=1}^4(\sum _{\mathrm{i}=1}^4(∆\mathrm{T}\_\mathrm{i}\mathrm{j}\mathrm{n}(\mathrm{k})+∆{\mathrm{T}\_\mathrm{i}\mathrm{j}}_{\mathrm{c}\mathrm{m}\mathrm{p}}(\mathrm{k})) \end{gathered}$$

(21)

$$∆{\mathrm{T}}_{\mathrm{i}\mathrm{j}\mathrm{n}}\left(\mathrm{k}\right)=∆{\mathrm{T}}_{\mathrm{i}\mathrm{j}\mathrm{n}\left(\mathrm{k}-1\right)}·{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}}+{\mathrm{R}}_{\mathrm{i}\mathrm{j}\mathrm{n}}·{\mathrm{P}}_{\mathrm{j}}\left(\mathrm{k}\right)·\left(1-{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}\mathrm{n}}}}}\right)$$

(22)

$$∆{{\mathrm{T}}_{\mathrm{i}}\mathrm{j}}_{\mathrm{c}\mathrm{m}\mathrm{p}}\left(\mathrm{k}\right)=∆{{\mathrm{T}}_{\mathrm{i}}\mathrm{j}}_{\mathrm{c}\mathrm{m}\mathrm{p}}\left(\mathrm{k}-1\right)·{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}4}}}}{+\mathrm{R}}_{\mathrm{i}\mathrm{j}\mathrm{c}\mathrm{m}\mathrm{p}}·{\mathrm{P}}_{\mathrm{j}}\left(\mathrm{k}\right)·\left(1-{\mathrm{e}}^{{\displaystyle \frac{-∆\mathrm{t}}{{\tau }_{\mathrm{i}\mathrm{j}4}}}}\right)$$

(23)

where $∆{\mathrm{T}}_{\mathrm{i}\mathrm{j}\mathrm{n}}$ represents the n-th order temperature rise caused by the j-th chip to the i-th chip, and $∆{\mathrm{T}\_\mathrm{i}\mathrm{j}}_{\mathrm{c}\mathrm{m}\mathrm{p}}$ represents the temperature rise compensation value of the j-th chip to the i-th chip. Rijcmp is the compensation value for the fourth-order thermal resistance from the j-th chip to the i-th chip, with its corresponding time constant being the largest time constant of the fourth-order RC. This estimated junction temperature, based on the formula, can be adjusted according to the coolant flow rate, making it applicable to a wider range of operating conditions.

3.5. Bench-Top Verification

To validate the accuracy of the junction temperature estimation method presented in this paper, a motor controller-inductance load test platform was built, as shown in Figure 17. The ambient temperature is controlled via an EXPLORE environmental chamber, and the coolant temperature and flow rate are regulated using an LNEYA water chiller (Wuxi Guanya Refrigeration Technology Co., Ltd., Wuxi, Jiangsu, China). The temperature of the coolant can be measured using Agilent thermometers (Agilent Technologies, Inc; Santa Clara, CA, USA). An IGBT module equipped with an on-chip temperature sensor is employed to monitor the temperature during operation. The maximum operating junction temperature of the IGBT is 175 °C. Key parameters influencing IGBT heating include current, voltage, switching frequency, power factor angle, and modulation scheme. By selecting an appropriate external inductance load for the motor, the heating conditions of the IGBT can be effectively evaluated during the motor’s forward operation.

The upper computer is used to set the ambient temperature to 85 °C, the coolant temperature to 65 °C, and the coolant flow rate to 8 L/min. The inverter operates in Constant Current Variable Frequency (CCVF) mode, with a switching frequency of 10 kHz and a fundamental frequency of 300 Hz. The junction temperature estimation is verified under different operating conditions by varying the voltage and current.

Figure 18 presents the schematic diagram of the measured maximum junction temperature of the sensor under the rated voltage of 385 V and current of 250 A. Since the sensor measures the average temperature of the chip, the average temperature estimated by the software is also used for comparison. As shown in the figure, both the dynamic and static errors of the software estimate are within 5 °C. Overheating is a significant cause of IGBT failure, making accurate temperature estimation during peak conditions crucial.

Table 3. Estimation error at different voltages and currents.

Bus Voltage (V)	Load Current (A)	Fundamental Frequency (Hz)	Inverter Loss (J)	Measured Temperature (°C)	Estimated Temperature (°C)	Error (°C)
385	100	300	567	83.97	84.31	0.34
385	250	300	1612	111.65	110.32	1.33
385	350	300	2889	147.62	149.31	1.69
385	350	50	2896	148.32	148.89	0.57
260	350	300	1964	120.12	121.35	1.23
450	350	300	3325	160.34	158.41	1.93

provides the test data for different voltage and current combinations. The total inverter loss varies synchronously with the rise in IGBT temperature. It is evident that the temperature estimation error for various voltage and current levels is around 3 °C. Even under peak conditions of 450 V and 350 A, the estimation error does not exceed 3 °C.

To investigate the effect of cooling boundary conditions on junction temperature estimation, experiments were conducted by setting different water temperatures and flow rates in the chiller. The ambient temperature was set to 85 °C, the water temperature to 65 °C, the bus voltage to 385 V, the current to 250 A, the switching frequency to 10 kHz, and the fundamental frequency to 300 Hz. The flow rates were gradually set to 1 L/min, 2 L/min, 3 L/min, 4 L/min, 6 L/min, 8 L/min, and 10 L/min. The flow rate was maintained for a sufficient period until the temperature stabilized, allowing the study of the influence of flow rate changes on junction temperature.

Figure 19 shows the measured steady-state average temperature of the three-phase IGBT at different flow rates. As observed, the IGBT temperature at the outlet is higher than at the inlet, and the temperature difference between the outlet and inlet IGBT increases as the flow rate decreases. At a flow rate of 1 L/min, the temperature difference exceeds 20 °C, highlighting the necessity of flow rate compensation. Additionally, the inlet IGBT temperature increases with the decrease in flow rate, which is attributed not only to the chip’s inherent heat but also to the increased thermal resistance caused by the reduced flow rate. The figure also shows that the temperature difference across the three-phase IGBT follows a roughly isometric distribution, meaning the reference temperatures for the intermediate and outlet phases can be compensated based on the inlet temperature and loss. Since the focus is on the highest temperature within the module, this study primarily compares the outlet phase IGBT temperature. However, in certain operating conditions, the highest temperature IGBT may not be in the outlet phase, necessitating the monitoring of each phase IGBT. Figure 20a presents the statistics of the estimated IGBT temperature and the sensor-measured temperature at different flow rates. The figure shows that as the flow rate increases, the IGBT temperature decreases, with the estimated error remaining within 5 °C.

Figure 20b shows the statistical comparison of the estimated IGBT temperature and the sensor-measured temperature under different water temperatures. The bus voltage was set to 385 V, current to 250 A, switching frequency to 10 kHz, and fundamental frequency to 300 Hz. The water temperature was successively set to 25 °C, 45 °C, 65 °C, and 85 °C. The figure demonstrates that the estimation error for different water temperatures remains within 5 °C.

4. Conclusions

This paper presents a method for accurately estimating the junction temperature of double-sided cooling insulated-gate bipolar transistor (IGBT) modules, incorporating thermal boundary conditions and chip-level thermal coupling effects. By analyzing chip distribution and the impact of cooling boundaries on the thermal model, the proposed method offers reliable junction temperature estimation under various operating conditions. To improve the accuracy of thermal resistance parameters, a novel parameter extraction method is introduced, combining ANSYS (2024R1) finite element simulations and thermal resistance tests. The effects of different cooling boundaries on thermal resistance parameters are systematically examined through simulations and experiments, revealing that coolant temperature has minimal influence, while the effect of flow rate on thermal resistance is more than 20%. Lower flow rates result in higher thermal resistance and intensify the heat channeling effect within the module. The proposed thermal model dynamically adjusts its parameters in response to varying cooling conditions. Experimental validation conducted under diverse operating conditions using an inductance test bench confirms that the junction temperature estimation error of the proposed method is within 5 °C for double-sided cooling IGBT modules.