Design and Performance Analysis of New Multilevel Inverter for PV System

Abstract

Multilevel inverters (MLIs) have recently attracted more attention in medium-voltage and high-power applications as they can provide an effective interface with photovoltaic (PV) systems. Conventional MLIs are used to generate higher voltage levels, which improve power quality and reduce the requirement for passive filters. However, recent research has focused on designing new MLI topologies using reduced switch counts and less voltage stress. This study, as such, proposes a new nine-level symmetric MLI for PV systems with a minimum number of switches. This decrease in the number of switches reduces the voltage stress across the switches and the number of driving circuits, which lowers the complexity of the control circuit and, as a result, lowers the cost and size of the system. This article compares the proposed MLI with other topologies based on the DC sources, switches count, gate driver circuits (N_gd), total standing voltage per unit (TSV_PU), cost function (CF), and components count per level (CC/L). The proposed topology is integrated with the PV system. MATLAB software is used to evaluate the performance of MLI at step change in irradiance and under variable load conditions. The total harmonic distortion (THD) of the proposed topology is reduced with the implementation of phase disposition pulse width modulation (PD-PWM). In addition, PD-PWM is compared with phase opposition disposition pulse width modulation (POD-PWM) and alternative phase opposition disposition pulse width (APOD-PWM) modulation techniques. The simulation results reveal the improved performance of the proposed topology at variable irradiance and under varying load conditions. The comparison results reveal minimum (TSV_PU), CC/L, CF, and switch count compared to existing topologies. Hence, the proposed topology of MLI is cost-effective and superior in all aspects compared to other topologies. In summary, it offers overall improved performance, and thus, it is feasible for the PV system.

1. Introduction

Due to the high cost and scarcity of fossil fuels, as well as the necessity to minimize greenhouse gas emissions, renewable resources are becoming more desirable in the field of research [1]. PV is a commonly used renewable energy source. PV energy has many advantages, such as a pollution-free energy resource with a low operating cost, low maintenance cost, and longer life [2]. Inverter is the main component of the PV system that converts DC power to AC, as required by the load [3]. Previously, 2-level inverters were used in a PV, but these are less efficient devices and generate more losses in the system [4].

Furthermore, two-level inverters are limited to low-voltage sectors [5]. In high-power and medium-voltage applications, MLI topologies are employed instead of two-level inverters [6]. The ability of MLIs to meet the demand for power quality and rating has led to their deployment in power systems [7]. MLIs have numerous advantages over 2-level inverters, such as high modularity, smaller common-mode voltage, and reduced electromagnetic compatibility [8]. However, with the increase in voltage levels, more switches are required in this topology, thus increasing the number of components, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, and the cost of the system [9]. Therefore, great attention has been given to the new topologies of an MLI having a reduced device count structure with minimum switches, minimum $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$ and low CF [10].

Many topologies of MLIs have been discussed in this article. The topology in [11] examined the new topology of MLI, which has 11 switches for the nine-level inverter. This topology has high $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, high CF, and more CC/L. The author in [12] presents a symmetric MLI. It consists of 10 switches for the nine-level inverter, but the $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, CF, and CC/L are high. In [13], the author proposed a nine-level symmetric MLI, which uses 12 switches to enhance the voltage levels. In [14], the modified topology of the MLI is proposed. A nine-level MLI requires 11 switches for the nine-level inverter in this topology. In [15], a modified topology of MLI is presented. In this topology, a nine-level inverter requires 12 switches. In [16], a new nine-level cascaded MLI is designed, which consists of 12 switches. In [17],12 switches are required to design a modified nine-level symmetric MLI. In [18], the author presents a modified MLI topology. This topology consists of 12 switches for a nine-level output. In [19], a new single-phase cascaded MLI is designed. In this work, 11 switches are required to design a nine-level inverter. In [20], the author proposed a new topology of the nine-level symmetrical MLI. This topology needs 12 switches for the nine-level MLI. In this proposed work [21], a new topology of nine-level MLI of reduced devices is designed. This topology of nine-level MLI uses 14 switches. This topology has the disadvantage that it can withstand faults at least seven levels. In [22], the author studied an asymmetric UXE-single-source MLI. This topology proposed a nine-level inverter. This topology uses twelve switches for the nine-level inverter. In [23], a UXE-type inverter is proposed. This topology uses twelve switches for the MLI. This topology requires more switches with the increase in voltage levels. The author in [24], proposed a dependable five-level inverter topology. In this topology, nine switches are used for the five-level inverter. The drawback of this topology is that more switches are required with the voltage levels. In [25], the proposed MLI’s basic circuit produces eleven output voltage levels. This topology consists of 11 switches for nine-level inverters. The drawback of this topology is that more switches are required with the increase in voltage levels. In [26], the author proposed a nine-level inverter for a PV system which requires 12 switches.

In light of this, a new topology of MLI based on a reduced switch count, reduced components, low total standing voltage, and minimum system cost is proposed. The proposed topology consists of ten switches and four DC sources. Several parameters of the proposed topology, such as CC/L, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, and CF, have been calculated to analyze the performance of the new topology of MLI. The proposed topology is compared with other existing topologies regarding DC sources, switches, diodes, capacitors, gate driver circuits, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, CF, and CC/L. In this article, the proposed topology is integrated with the PV system. In this system, the PV arrays are connected to the proposed MLI’s input using DC-DC boost converters, and the PV array voltages are controlled using PI controllers. The performance of the new topology of MLI with has been analyzed at a step change in PV irradiance and is tested under different loads.

Furthermore, the modulation method is another crucial element of an inverter, closely related to THD. The commonly used PWM techniques are PD-PWM, POD-PWM and APOD multicarrier PWM techniques. Using PD-PWM, the carrier signals above and below zero have the same magnitude and phase angle. The carrier signals in the POD-PWM technique are 180 phases shifted between those above and below the reference voltage. The alternate carrier signals are 180 phases shifted in APOD-PWM. These produce low switching losses and low harmonic distortion [27]. In this research work, the PD-PWM technique is designed to reduce the harmonics in the output waveform of the new topology of MLI. This technique is also compared with the POD-PWM and APOD-PWM techniques.

This paper is prepared as the proposed topology of the new symmetric MLI is described in Section 2. This section describes the generalized arrangement, design equations, switching states, and modes of operation of the new topology of the MLI. This section proposed the complete diagram of the proposed topology and the diagram of the DC-DC boost converter with PV system with PI controllers. The control circuit of the new topology of MLI is described in Section 3. A comparative analysis of the proposed topology with existing topologies of the MLI is described in Section 4. Section 5 presents the simulation results of the proposed topology. Section 6 interprets the simulation results. Section 7 summarizes the paper.

2. Materials and Methods

2.1. Proposed New Multilevel Inverter Topology

Figure 1 shows the new topology of symmetric nine-level MLI. For simplification, the PV stages are replaced with DC sources. It consists of 10 switches and 4 DC sources. Symmetric MLI consists of an equal magnitude of voltage sources. The magnitude of the four voltage sources is selected in the ratio of 1:1:1:1 with voltage magnitude ${\mathrm{V}}_1={\mathrm{V}}_2={\mathrm{V}}_3={\mathrm{V}}_4={\mathrm{V}}_{\mathrm{d}\mathrm{c}}$ of 24 V.

The overall voltage magnitude of a symmetric MLI is given in Equation (1):

$${\mathrm{V}}_{\mathrm{o}}={\mathrm{V}}_{1\mathrm{i}}+{\mathrm{V}}_{2\mathrm{i}}+{\mathrm{V}}_{3\mathrm{i}}+\dots {\mathrm{V}}_{\mathrm{n}\mathrm{i}}$$

(1)

Or ${\sum }_{\mathrm{i}=1}^{\mathrm{n}}{\mathrm{V}}_0={\mathrm{V}}_{1\mathrm{i}}+{\mathrm{V}}_{2\mathrm{i}}+{\mathrm{V}}_{3\mathrm{i}}\dots {\mathrm{V}}_{\mathrm{n}\mathrm{i}}$.

In symmetrical MLI, all voltage sources are equal in magnitude. Thus,

$${\mathrm{V}}_{1\mathrm{i}}={\mathrm{V}}_{2\mathrm{i}}={\mathrm{V}}_{3\mathrm{i}}=\dots {\mathrm{V}}_{\mathrm{n}\mathrm{i}}$$

The number of effective output voltage levels is given in Equation (2):

nlevel = 4n + 1

(2)

where n is the number of voltage sources in each leg. In this topology, two sources are connected in each leg. Therefore, nine levels of output voltage are generated.

In the proposed MLI, several DC voltage sources, no. of switches, and no. of gate driver circuits can be found using Equations (3)–(5).

$${\mathrm{N}}_{\mathrm{s}\mathrm{o}\mathrm{u}\mathrm{r}\mathrm{c}\mathrm{e}\mathrm{s}}=2\mathrm{n}$$

(3)

$${\mathrm{N}}_{\mathrm{s}\mathrm{w}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}\mathrm{e}\mathrm{s}}=2\mathrm{n}+6$$

(4)

$${\mathrm{N}}_{\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}\mathrm{r}\mathrm{i}\mathrm{v}\mathrm{e}\mathrm{r}\mathrm{c}\mathrm{i}\mathrm{r}\mathrm{c}\mathrm{u}\mathrm{i}\mathrm{t}\mathrm{s}}=2\mathrm{n}+3$$

(5)

2.1.1. Switching States of New Multilevel Inverter

The switching states of the proposed nine-level MLI are presented in

Table 1. Switching states of 9-Level Symmetric New MLI.

$\mathbf{States}{\mathbf{S}}_1{\mathbf{S}}_2{\mathbf{S}}_3{\mathbf{S}}_4{\mathbf{S}}_5{\mathbf{S}}_6{\mathbf{S}}_7{\mathbf{S}}_8{\mathbf{S}}_9{\mathbf{S}}_{10}{\mathbf{V}}_{\mathbf{O}}$
1 0 1 1 0 1 1 0 0 0 0 +${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
2 1 0 1 0 1 1 0 0 0 0 +$2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
3 1 0 1 0 1 0 1 1 0 0 +3${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
4 1 0 1 0 1 0 1 0 1 0 +4${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
5 0 0 0 0 1 0 1 0 0 1 0
6 0 0 0 0 1 1 0 1 0 1 −${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
7 0 0 0 0 1 1 0 0 1 1 −${2\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
8 0 1 0 1 0 1 0 0 1 1 −${3\mathrm{V}}_{\mathrm{d}\mathrm{c}}$
9 1 0 0 1 0 1 0 0 1 1 −$4{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$

. This topology generates nine voltage levels which consist of 0${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$, ±1${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$, ±2${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$, ±3${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$, ±4${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$. This switching scheme generates four positive voltage steps from +V to +4V, zero output voltage steps, and four negative voltage steps from −V to −4V.

2.1.2. Modes of Operation of Proposed Topology

Figure 2 shows the operating modes of the new topology of MLI. To produce +${\mathrm{V}}_{\mathrm{d}\mathrm{c}},$ mode 1 activates switches ${\mathrm{S}}_2,{\mathrm{S}}_3,{\mathrm{S}}_5\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{S}}_6$ are shown in Figure 2a. Mode 2 activates switches ${\mathrm{S}}_1,{\mathrm{S}}_3,{\mathrm{S}}_5\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{S}}_6$ to produce +2${\mathrm{V}}_{\mathrm{d}\mathrm{c}}$ are shown in Figure 2b. Figure 2c shows that mode three is activated to produce $+3{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$ by turning on ${\mathrm{S}}_1,{\mathrm{S}}_3,{\mathrm{S}}_5,{\mathrm{S}}_7,\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{S}}_8$. Mode 4 activates switches ${\mathrm{S}}_1,{\mathrm{S}}_3,{\mathrm{S}}_5\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{S}}_7,{\mathrm{S}}_9$ to generate $+4{\mathrm{V}}_{\mathrm{d}\mathrm{c}}$ are shown in Figure 2d. Mode 5 is activated by turning on switches ${\mathrm{S}}_5,{\mathrm{S}}_7,\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{S}}_{10},$ but cannot generate output voltage as shown in Figure 2e. In this manner, modes 6, 7, 8, and 9 generate negative polarity outputs according to the same operation phase as Modes 1 to 5, shown in Figure 2f–i.

2.2. Total Standing Voltage (TSV)

In MLI, the TSV of the switch is one of the significant parameters determining the MLI’s cost-effectiveness. The cost of the inverter decreases with the decrease in stress across the semiconductor switches. Standing voltage is the highest voltage stress a power device can withstand while turning off. The sum of all maximum blocking voltages across the switches is the TSV [28]. The maximum blocking voltage (MBV) across each switch is given as follows:

$$\begin{array}{c}\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_1=\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_2=1{\mathrm{V}}_{\mathrm{d}\mathrm{c}}\hfill \\ \mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_3=\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_{10}=4{\mathrm{V}}_{\mathrm{d}\mathrm{c}}\hfill \\ \mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_4=\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_5=2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}\hfill \\ \mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_6=\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_7=2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}\hfill \\ \mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_8=\mathrm{M}\mathrm{B}\mathrm{V}{\mathrm{s}}_9=1{\mathrm{V}}_{\mathrm{d}\mathrm{c}}\hfill \end{array}$$

The formula of total standing voltage is given in Equations (6) and (7):

$$\mathrm{TSV}={\sum }_{\mathrm{i}=1}^{\mathrm{n}}\mathrm{M}\mathrm{B}{\mathrm{V}}_{\mathrm{S}\mathrm{i}}$$

(6)

$$\begin{array}{c}\mathrm{TSV}=\mathrm{M}\mathrm{B}{\mathrm{V}}_{\mathrm{S}1}+\mathrm{M}\mathrm{B}{\mathrm{V}}_{\mathrm{S}2}+\mathrm{M}\mathrm{B}{\mathrm{V}}_{\mathrm{S}10}\\ \mathrm{TSV}={1\mathrm{V}}_{\mathrm{d}\mathrm{c}}+1{\mathrm{V}}_{\mathrm{d}\mathrm{c}}{+4\mathrm{V}}_{\mathrm{d}\mathrm{c}}+2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}+2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}+2{\mathrm{V}}_{\mathrm{d}\mathrm{c}}{+2\mathrm{V}}_{\mathrm{d}\mathrm{c}}{+1\mathrm{V}}_{\mathrm{d}\mathrm{c}}+{1\mathrm{V}}_{\mathrm{d}\mathrm{c}}+{4\mathrm{V}}_{\mathrm{d}\mathrm{c}}\\ \mathrm{TSV}={20\mathrm{V}}_{\mathrm{d}\mathrm{c}}\end{array}$$

(7)

TSV per unit can be calculated by using Equation (8):

$$\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}=\frac{{\mathrm{V}}_{\mathrm{T}\mathrm{S}\mathrm{V}}}{{\mathrm{V}}_{0\mathrm{M}\mathrm{A}\mathrm{X}}}$$

(8)

where, ${\mathrm{V}}_{\mathrm{T}\mathrm{S}\mathrm{V}}$ is the total standing voltage, and ${\mathrm{V}}_{0\mathrm{M}\mathrm{A}\mathrm{X}}$ is the maximum output voltage.

For the proposed nine-level MLI, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$ is calculated as:

$$\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}=5$$

2.3. Cost Function (CF)

Another important parameter of MLI is the cost function (CF). The CF is crucial for selecting the MLI that is most appropriate for the application.CF can be calculated by considering the switches count $({\mathrm{N}}_{\mathrm{s}})$, DC sources count $({\mathrm{N}}_{\mathrm{D}\mathrm{C}})$, capacitors $({\mathrm{N}}_{\mathrm{C}})$, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, diodes count ${(\mathrm{N}}_{\mathrm{D}})$, and gate drivers count ${(\mathrm{N}}_{\mathrm{g}\mathrm{d}})$ [29]. The cost function is given in Equation (9):

$$\mathrm{C}\mathrm{F}=\left({\mathrm{N}}_{\mathrm{s}}+{\mathrm{N}}_{\mathrm{g}\mathrm{d}}+{\mathrm{N}}_{\mathrm{D}}+{\mathrm{N}}_{\mathrm{C}}+\mathsf{\alpha }\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}\right)\times {\mathrm{N}}_{\mathrm{D}\mathrm{C}}$$

(9)

where, $\mathsf{\alpha }$ is the cost coefficient.

The $\mathsf{\alpha }$ is 0.5 (<1) and 1.5 (>1) for the usual operating state. For the nine-level MLI, the CF/level is calculated as:

For, $\mathsf{\alpha }=0.5,$ the cost function is given as

$$\mathrm{CF}/\mathrm{Level}=\frac{19.5\times 4}{9}=8.66$$

For α = 1.5, the cost function per level is given as

$$\mathrm{CF}/\mathrm{Level}=\frac{24.5\times 4}{9}=10.88$$

2.4. Components Count per Level (CC/L)

Components count per level is a method used to calculate the number of components per level. The MLI needs more components for the desired voltage levels if the CC/L is high. Thus, the factor needs to be decreased. The CC/L is computed by using Equation (10) [30].

$$\mathrm{C}\mathrm{C}/\mathrm{L}=\left({\mathrm{N}}_{\mathrm{s}}+{\mathrm{N}}_{\mathrm{g}\mathrm{d}}+{{\mathrm{N}}_{\mathrm{D}\mathrm{C}}+\mathrm{N}}_{\mathrm{D}}+{\mathrm{N}}_{\mathrm{C}}+{\mathrm{N}}_{\mathrm{X}}\right)$$

(10)

For the proposed nine-level MLI, $\mathrm{C}\mathrm{C}/\mathrm{L}$ is calculated as:

$$\mathrm{C}\mathrm{C}/\mathrm{L}=(10+7+4+0+0+0)=\frac{21}{9}=2.33$$

2.5. Boost Converter with PV System with PI Controller

The PV Panel is coupled with a DC/DC converter with PI controllers to enhance the performance of the PV system and obtain consistent output voltage at varying irradiance. Implementing PI controllers is the main advantage of irradiance change in the DC-DC converter. Therefore, this work uses a DC-DC boost converter with a PI controller to provide the optimum voltage for the proposed [31]. Figure 3 shows the complete proposed system for the new topology of a nine-level inverter with ten switches and four PV panels. Figure 4 shows the PV system, which includes a PV system and a boost converter with PI controllers.

The output voltage of the boost converter is given in Equation (11):

$${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{1-\mathrm{D}}$$

(11)

here, D is the duty ratio, ${\mathrm{V}}_{\mathrm{i}\mathrm{n}}$ is the input voltage, and ${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}$ is the output voltage.

The duty ratio is given in Equation (12):

$$\mathrm{D}\mathrm{u}\mathrm{t}\mathrm{y}\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{i}\mathrm{o}=\frac{{\mathrm{T}}_{\mathrm{o}\mathrm{n}}}{{\mathrm{T}}_{\mathrm{s}}}$$

(12)

here, ${\mathrm{T}}_{\mathrm{o}\mathrm{n}}$ is the turn-on time, ${\mathrm{T}}_{\mathrm{s}}$ is the switching time of the semiconductor Switch.

Inductance can be found by using Equation (13):

$$\mathrm{L}=\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\times \mathrm{D}}{{\mathrm{f}}_{\mathrm{s}}\times ∆{\mathrm{I}}_{\mathrm{L}}}$$

(13)

here, L is the inductance, and ${\mathrm{f}}_{\mathrm{s}}$ is the Switching frequency.

Capacitance can be found by using Equation (14):

$$\mathrm{C}=\frac{{\mathrm{I}}_{\mathrm{o}}\times \mathrm{D}}{{\mathrm{f}}_{\mathrm{s}}\times ∆{\mathrm{V}}_{\mathrm{c}}}$$

(14)

here, C is the capacitance, Io is the output current, $∆{\mathrm{V}}_{\mathrm{c}}$ is a change in voltage i–e (1 to 5% of ${\mathrm{V}}_{\mathrm{o}}$).

3. Control Circuit of New Topology of MLI

For the nine-level output, PWM pulse generation is required. It is always necessary to determine which PWM best matches the new topology. Using phase disposition, the THD value of MLIs can be drastically decreased to the lowest possible percentage. By comparing the pulses produced by carrier-shifted signals to a sinusoidal wave, power switches can be turned on [27]. A control circuit for the voltage waveform associated with the carrier signals produced by the PD-PWM approach is shown in Figure 5a. The eight carrier signals required to modulate the reference signal using the PD-PWM approach are shown in Figure 5b. Figure 5c shows the control signals for each switch (${\mathrm{S}}_1-{\mathrm{S}}_{10})$.

The triangular carrier for the m level is given in Equation (15): [32].

Triangular carriers = m − 1

(15)

Upper triangular signals are given in Equation (16):

$${\mathrm{T}}_{\mathrm{u}}={\mathrm{T}}_{\mathrm{u}1},{\mathrm{T}}_{\mathrm{u}2},{\mathrm{T}}_{\mathrm{u}3}\dots {\mathrm{T}}_{\mathrm{u}\mathrm{n}}$$

(16)

Lower triangular signals are given in Equation (17):

$${\mathrm{T}}_{\mathrm{l}}={\mathrm{T}}_{\mathrm{l}1}+{\mathrm{T}}_{\mathrm{l}2}+{\mathrm{T}}_{\mathrm{l}3}\dots {\mathrm{T}}_{\mathrm{l}\mathrm{n}}$$

(17)

If the upper triangular signal is less than the reference signal, then the comparator generates.

$${(\mathrm{u}}_{\mathrm{n}}-1)$$

If the lower triangular signal is less than the reference signal, then the comparator generates$-({\mathrm{l}}_{\mathrm{n}}-1)$.

Modulation index ${(\mathrm{M}}_{\mathrm{i}}$) is given in Equation (18): [33]

$${\mathrm{M}}_{\mathrm{i}}=\frac{{\mathrm{A}}_{\mathrm{m}}}{\left(\mathrm{m}-1\right){\mathrm{A}}_{\mathrm{c}}}$$

(18)

where, ${\mathrm{A}}_{\mathrm{c}}$ is the amplitude of the carrier signal, ${\mathrm{A}}_{\mathrm{m}}$ is the amplitude of the modulating signal, and m is the number of levels.

The frequency ratio ${(\mathrm{M}}_{\mathrm{f}})$ is given in Equation (19):

$${\mathrm{M}}_{\mathrm{f}}=\frac{{\mathrm{F}}_{\mathrm{m}}}{{\mathrm{F}}_{\mathrm{c}}}$$

(19)

where ${\mathrm{F}}_{\mathrm{m}}$ is modulating frequency, and ${\mathrm{F}}_{\mathrm{c}}$ is the carrier frequency.

4. Comparative Analysis

Table 2. Comparison of proposed topology with other topologies of MLI.

$\mathbf{Topologies}{\mathbf{N}}_{\mathbf{L}}{\mathbf{N}}_{\mathbf{d}\mathbf{c}}{\mathbf{N}}_{\mathbf{S}\mathbf{W}}{\mathbf{N}}_{\mathbf{C}}{\mathbf{N}}_{\mathbf{D}}{\mathbf{N}}_{\mathbf{g}\mathbf{d}}\mathbf{C}\mathbf{C}\mathbf{/}\mathbf{L}\mathbf{T}\mathbf{S}{\mathbf{V}}_{\mathbf{P}\mathbf{U}}\mathbf{C}\mathbf{.}\mathbf{F}$$(\mathsf{\alpha }=0.5)$$\mathbf{CF}(\mathsf{\alpha }=1.5)$
[11] 9 4 11 0 0 9 2.44 5.5 10.66 12.8
[12] 9 4 10 0 0 8 2.44 5.5 9.1 11.33
[19] 9 4 12 0 1 8 2.77 6 10.66 13.33
[28] 9 4 12 0 0 10 2.88 6 11.1 13.7
[34] 9 4 11 0 0 10 2.66 6 10.22 12.22
[35] 9 4 10 0 0 8 2.44 5.4 9.2 11.6
[36] 9 4 20 0 0 17 4.55 6 17.8 20.44
Proposed 9 4 10 0 0 7 2.33 5 8.66 10.88

${\mathrm{N}}_{\mathrm{L}}$ is the voltage levels, ${\mathrm{N}}_{\mathrm{d}\mathrm{c}}$ is the no. of sources, ${\mathrm{N}}_{\mathrm{S}\mathrm{W}}$ is the switches, ${\mathrm{N}}_{\mathrm{C}}$ is the capacitors, ${\mathrm{N}}_{\mathrm{D}}$ is the diodes, ${\mathrm{N}}_{\mathrm{g}\mathrm{d}}$ is the gate driver circuits, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$ is the total standing voltage per unit, and CF is the cost function. CC/L is the components count per level.

compares the proposed topology with conventional and other modified topologies of MLIs based on the number of DC sources, switches, gate diver circuits, diodes, no. of capacitors, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, CC/L, and CF. The DC sources in topology [11], the DC sources are 4, but the switches, gate driver circuits, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, CF, and components count per level are high. In [12], the DC sources and switches are the same as the proposed topology, but CC/L, $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, and CF are high compared to the proposed topology. In the other topologies mentioned below, all parameters have been calculated as high except DC sources.

Similarly,

Table 3. Comparison of proposed topology with other topologies of MLI.

Topologies No. of Switches No. of Voltage Levels
[13] m + 3 = 12, 16, 20, 24 2m + 1 = 9, 13, 17, 21
[14] 2m + 1 = 11, 13, 15, 17n + 4 = 9,13,17, 21
[15] 6n = 12, 18, 24, 30 4n + 1 = 9, 13, 17, 21
[16] 6n = 12, 18, 24, 30 4n + 1 = 9, 13, 17, 21
[17] $2\mathrm{n}+6=12,16,20,242{\mathrm{N}}_{\mathrm{D}\mathrm{C}}+1$ = 9, 13, 17, 21
[18] 4(p + 1) = 12, 16, 20, 24 4p + 1 = 9, 13, 17, 21
[19] 5n + 6 = 11, 16, 21, 26 6n + 3 = 9, 13, 17, 21
Proposed 2n + 6 = 10, 12, 14, 16 4n + 1 = 9, 13, 17, 21

m is the number of levels. n and p are the numbers of modules.

compares the number of switches concerning the voltage levels, which shows that switches in other existing topologies of MLI are greater than the proposed topology of MLI.

The graphical representation of respective comparisons is shown in Figure 6. Figure 6a compares the total standing voltage per unit ($\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}})$ of the proposed topology compared with other existing topologies. Figure 6b compares the number of gate driver circuits (${\mathrm{N}}_{\mathrm{g}\mathrm{d}})$ of the proposed topology with other existing topologies. Figure 6c shows the number of component counts per level (CC/L) in the proposed topology with other existing topologies. Figure 6d compares the cost function per level (CF/L) at 0.5 and 1.5 values of the cost coefficient of the proposed topology with other existing topologies. The comparison graph between no. of switches concerning voltage levels is shown in Figure 7. It shows that the proposed topology requires fewer switches with an increase in voltage levels compared to existing topologies of MLIs.

5. Results

The simulation was carried out using MATLAB/Simulink. The applied parameters and their values are given in

Table 4. Simulation parameters of the proposed system.

Parameters Values
PV voltage $({\mathrm{V}}_{\mathrm{p}\mathrm{v}}$), PV current (${\mathrm{I}}_{\mathrm{p}\mathrm{v}})$ 17.5 V, 2.86 A
Sinusoidal wave frequency 50 Hz
Switching frequency (${\mathrm{f}}_{\mathrm{s}}$) 1 kHz
Output voltage levels 9
No. of carrier signals 8
Resistive load $({\mathrm{R}}_{\mathrm{L}})$ 12 Ω
No. of DC voltage source (${\mathrm{N}}_{\mathrm{d}\mathrm{c}})$ 4
Voltage magnitude (${\mathrm{V}}_{\mathrm{s}}){\mathrm{V}}_1={\mathrm{V}}_2={\mathrm{V}}_3=V_4=$24 V
Inductance(L) 92 mH
Capacitance(C) 46 $\mathsf{\mu }$F

. The output PV groups (DC sources) are ${\mathrm{V}}_1={\mathrm{V}}_2={\mathrm{V}}_3={\mathrm{V}}_4=$24 V, functioned as symmetric sources to verify the nine-level output voltage inverter. Investigations were conducted on a new topology of MLI circuit having a maximum output voltage of approximately 96 V, four DC voltage sources, and ten switches.

In the first case, the resistive load is 12 Ω, and the PV irradiance varies from 1000 $\mathrm{W}/{\mathrm{m}}^2$ to 800 $\mathrm{W}/{\mathrm{m}}^2$ from 0.04 s to 0.14 s as shown in Figure 8a. The variation in PV voltage concerning irradiance is shown in Figure 8b. Figure 8c shows the variation in PV current. Since PI controllers are implemented with four PV arrays with boost converters to maintain the outputs of the proposed topology at variable irradiance. The constant DC voltage is shown in Figure 8d. Each produces a DC constant voltage of 24 V. The constant DC current is shown in Figure 8e. Figure 9 shows the load voltage and load current of the proposed topology nine-level MLI. Figure 10 shows the load current of the proposed topology. Fast Fourier Transform (FFT) spectrum of the load voltage and load current with PD-PWM are shown in Figure 11 and Figure 12.

In the second simulation scenario, resistive-inductive load of R = 12 Ω, L = 1 mH is used to test the topology. Figure 13 displays the load voltage and current waveforms. The load current waveform under a resistive-inductive load behaves differently than a purely resistive load and differs from the voltage waveform. According to the inductor value utilized, the current is smoothed due to inductive load. The load current waveform is shown in Figure 14. FFT analysis of both waveforms is shown in Figure 15 and Figure 16.

Furthermore, the harmonic profile of load voltages with the POD-PWM and with the APOD-PWM technique are shown in Figure 17 and Figure 18. THD with POD-PWM is calculated as 24.93% and 24.56% with APOD-PWM techniques. The Comparison graph of the harmonic spectrum is shown in Figure 19. The obtained results of three PWM techniques have been compared. It is observed that minimum harmonics are obtained with the PD-PWM technique as of 23.82%.

6. Discussion

It is evident from the simulation results contained in the precedent section that the proposed new topology of a symmetric nine-level inverter integrated with PV provides improved performance. In this study, PV irradiance varies from 1000 $\mathrm{W}/{\mathrm{m}}^2$ to 800 $\mathrm{W}/{\mathrm{m}}^2$ from 0.04 s to 0.14 s. It is observed that load voltage and load current remain constant with respect to irradiance. As such, PI controllers are implemented with boost converters to maintain the constant output, revealing the constant output of the MLI-fed PV. The THD under the proposed topology is 23.82% with PD-PWM. The THD under the proposed topology is 23.82% with PD-PWM. With a resistive-inductive load, the load current waveform differs from the voltage waveform. According to the inductor value utilized, the current is smoothed due to inductive load. The magnitude of the load current slightly decreases while the load voltage remains approximately constant. Since the current output waveform is closer to a purely sinusoidal, the THD has dropped to 17.60%. However, the THD for the voltage generally remains the same whether an inductive or resistive load is being powered. In addition, THD with POD-PWM is calculated as 24.93% and 24.56% with APOD-PWM techniques. The reduction of harmonics at the output of the new topology has been obtained with the PD-PWM technique. In addition, this new topology of MLI has also been compared with existing topologies. The comparison results reveal improved $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$ as of 5, CC/L as of 2.33, CF of 8.66 and 10.66, which are lesser than the existing topologies.

7. Conclusions

This study proposed a new topology of nine-level symmetric MLI for the PV system. The critical aspects addressed through this topology include high $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, high-cost function, and high components count per level, common problems associated with the existing MLI topologies. As such, this new topology of MLI with reduced device count, minimum $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$, and less cost function has been designed. The proposed topology reveals a $\mathrm{T}\mathrm{S}{\mathrm{V}}_{\mathrm{P}\mathrm{U}}$ of 5, component count per level of 2.33, and a cost function of 8.66 for a cost coefficient of 0.5 and 10.66 for a cost coefficient of 1.5. These results are sufficiently better than the existing topologies. The new topology of MLI has been integrated with the PV system with PI controllers to maintain the constant output of the proposed topology of the MLI under variations in irradiance. The simulation results revealed constant load voltage and load current with respect to variation in irradiance. Implementing the PD-PWM techniques in the proposed topology of MLI has also helped to reduce the harmonics, which are calculated to be 23.82% with PD-PWM. When tested with resistive-inductive load, the proposed topology works decently under resistive-inductive load. The magnitude of the load current slightly decreases while the load voltage remains constant. Since the waveform of the load current is closer to a purely sinusoidal, the THD has dropped to 17.60%. However, whether an inductive or a resistive load is being driven, the THD for the load voltage remains the same. In addition, THD with POD-PWM is calculated as 24.93% and 24.56% with APOD-PWM. Minimum harmonics have been obtained with the PD-PWM technique. Hence, the overall performance of the new topology of MLI is better and more appropriate for PV systems.