An Efficacious Modulation Gambit Using Fewer Switches in a Multilevel Inverter

Abstract

Since multicarrier based modulation techniques are simple to implement and can be used to control inverters at any level, they are frequently employed in modern multilevel inverters in high or medium power applications. When considering the many multi-carrier modulation techniques available, level-shifted pulse-width modulation (LSPWM) is often chosen for its superior harmonic performance. However, this traditional LSPWM method is not suitable for controlling newly proposed reduced switch count (RSC) MLI topologies. The research work in this paper seeks to elucidate the reasons why conventional LSPWM is ineffective in controlling RSC MLI topologies, and proposes a generalized LSPWM system based on logical expressions. The proposed method can be utilized with symmetrical and asymmetrical RSC MLIs, and can be extended to an arbitrary number of levels. The merit of the proposed method for controlling any RSC configuration with satisfactory line-voltage THD (≈1.8%) performance (identical to conventional LSPWM) was evaluated using multiple 13-level asymmetrical RSC-MLI topologies. A MATLAB model was developed and then subjected to simulation and real-world testing to prove the effectiveness of the proposed modulation strategy.

1. Introduction

Multilevel inverters (MLI) have many advantages over two-level inverters, including lower dv/dt, reduced electromagnetic interference (EMI), suppressed common mode voltages, improved total harmonic distortion (THD), and minimized filtering requirements. Several modulation schemes have been reported to control the widely used classical topologies, including the cascaded H-bridge (CHB), the diode-clamped (DCMLI), and the flying capacitor (FCMLI) [1,2,3,4]. According to studies [5,6,7], level shifted pulse-width modulation (LSPWM) provides the best harmonic performance of these modulation schemes.

Due to their higher switch count, MLIs present several challenges in terms of size, cost, and reliability that are not shared by their simpler two-level inverter counterparts. In response to this need, a new class of MLIs known as reduced switch count (RSC) MLIs has emerged [8,9,10,11,12]. Depending on the ratios of the DC sources, these RSC MLI topologies can be further categorized as symmetrical or asymmetrical [13,14]. To further reduce the number of switches required, asymmetrical DC source voltages can be utilized. Many different RSC MLI topologies have been proposed, including the multilevel DC link (MLDCL) [15], packed U-cell (PUC) [16], cascaded bi-polar switched cells (CBSC) [17], reverse voltage (RV) [18], switched DC sources (SDS) [19], the basic unit MLI [20], envelope-type (E-type) [21], T-type [22,23,24,25,26], hybrid T-type [27,28], series parallel switched sources (SPSS), series connected switched sources (SCSS), and reverse voltage (RV) [8,10,29,30,31]. Most of these RSC configurations operate with drastic reductions in switch or device count in comparison to those employed in traditional MLI designs. Switched capacitor configurations, extended hexagonal switched cell (HSC) configurations, X-structured, envelope-structured, and layered-type configurations with symmetric and asymmetric capabilities have also been reported for various grid-connected, energy-storage, and standalone applications [32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47].

However, a drastic reduction in the switch count affects the corresponding topological arrangement of RSC MLI, imposes multiple limitations on their switching operation, and thus effects the modulation scheme that is used to control them. These topologies include the T-type, E-type, hybrid T-type, CBSC, SSPS, SCSS, and basic unit MLI. In general, selective harmonic elimination (SHE) [21], low frequency switching (50 or 100 Hz) [15,17,20,25,27,28,33,41,46], and space vector pulse-width modulation (SVPWM) [16,32,39,41] are the most frequently used schemes for their control. Nevertheless, in order to calculate switching instants, these schemes must perform intricate mathematical transformations that become more difficult as levels increase.

To control RSC MLI in the context of RV, SSPS, T-type, and reduced cascaded topologies, various multi-carrier [31] and reduced carrier PWM schemes involving logical operators have been reported. The logical expressions, however, are not scalable and change depending on the topological arrangement. For further control of RSC MLI topologies such as T-type and reduced cascaded topologies, a novel multi-reference modulation scheme has been reported [24,26,36,38]. Although this scheme is easily generalized to higher levels, its line-voltage THD performance is subpar. A novel switching function scheme method, named switching function PWM, has been reported for RSC MLI using PUC, switched DC sources (SDS), and hybrid T-type topologies [19,29]. This scheme imposes a popular level-shifted carrier arrangement and uses multiple comparators to implement the control logic. Despite its incorporation of a generalized switching logic, this switching function scheme suffers from complexity at higher levels (due to numerous comparators).

Hybrid modulation, which has been well documented in the literature for use with asymmetrical CHB [48], is a common technique for implementing cascaded asymmetrical topologies. By including an additional H-bridge in each phase, this hybrid modulation can be implemented in non-cascaded RSC MLI topologies such as SSPS, in addition to cascaded RSC MLI topologies [33,35]. To obtain the reference signal for the lower voltage cells in this scheme, it is necessary to measure or estimate the output voltage of the higher voltage cells. The output voltage of cells with lower voltages will therefore be affected by any delays or errors in the estimation or measurement. The modified reduced carrier PWM scheme described in the literature [49,50] uses uniform switching logic and generates a good harmonic profile, but because of its synchronized carrier arrangement with the modulating signal, the carrier frequency must be a triple-n multiple of the modulating frequency [50].

Thus, deep investigation into the various reported topologies and modulation schemes of RSC MLIs concludes that reduction in the switch count of RSC MLIs has simplified their circuit configuration, such that each switch is involved in achieving more than one voltage level, which limits the switching redundances and complicates the switching operation. With asymmetrical topologies, a decrease in switch count further complicates the switching states and drastically reduces switching redundancies. Even the most basic LSPWM scheme for MLI is no longer able to realize these switching states, due to the diverse effects created by the nature of this switching. Additionally, modulation schemes reported for RSC MLI topologies suffer from multiple drawbacks, including difficult switching logic, subpar THD, and higher-level generalization.

Therefore, this paper aims to propose a generalized carrier-based modulation scheme to control any RSC MLI, regardless of its DC voltage ratio, the nature of the switching operation, and the topological arrangement. With the addition of straightforward Ex-OR logical expressions, the proposed modulation scheme can derive the desired non-overlapped switching pulses from the conventional level-shifted carrier arrangement. To put it another way, the switching logic described by previous researchers [49] is extended by this proposed scheme, imposing conventional level-shifted carrier arrangements, such that the proposed scheme is applicable to any set of carrier frequencies, including both synchronized and unsynchronized PWM. For any RSC MLI topology, the proposed scheme produces optimal generalized harmonic performance identical to LSPWM, which can be applicable for multiple applications such as PV/grid connections [12], custom power devices [51], flexible bi-directional power control [51], front end converters, and energy storage [51].

The format of this essay is as follows: The introduction is provided in the first section, then the subsequent sections summarize the PWM schemes that have been reported in the literature and discuss why the LSPWM technique cannot be directly applied to RSC MLI topologies. The methodology of the generalized LSPWM technique is presented in the third section. The fourth section discusses the application of the suggested scheme to various 13-level asymmetrical RSC MLI topologies in simulation studies, and the fifth section discusses the experimental outcomes of these topologies.

2. RSC MLI Topologies and Their Modulation Schemes

Some RSC MLI topologies, including SCSS and T-type, are symmetrical, while others such as E-type are entirely asymmetrical, and these differences have been reported in the literature. MLDCL, SSPS, PUC, switched DC sources, cascaded T-type, nested cell, basic unit MLI, hybrid T-type, RV, and reduced cascaded topologies are a few examples of configurations that can be either. Since asymmetrical topologies are more challenging to implement with traditional LSPWM techniques, they are the focus of this paper. Because there are no switching redundancies in asymmetrical topologies, the choice of switching states for the typical LSPWM method is severely constrained. Figure 1 depicts the circuit configurations of the various single-phase 13-level RSC MLI topologies, including the MLDCL, PUC, switched DC sources, cascaded T-type, CBSC, SSPS, RV, E-type, and hybrid T-type asymmetrical configurations.

Table 1. Summary of various RSC MLI configurations and their respective modulation schemes.

Topology	Topology Description	Symmetrical/ Asymmetrical	Modulation Schemes Reported in Literature		Demerits of the Modulation Scheme
			Symmetrical	Asymmetrical
MLDCL [13]	Separate level and polarity generators	Both	Low-frequency switching scheme		Complicated at higher levels and poor THD
PUC [14]	Can be extended with and without cascading	Both	SVPWM		Complicated at higher levels
CBSC [15]	Can be extended with and without cascading	Both	Low-frequency switching scheme		Complicated at higher levels and poor THD
RV [16]	Separate level and polarity generators	Symmetrical	Reduced carrier PWM		Poor THD in line voltage
Switched DC sources [17]	Involves separate DC link for all phases	Both	Switching function PWM		Increased comparisons at higher levels
SSPS [28,29]	Separate level and polarity generators	Both	LSPWM with maximum and minimum conditions [29]	Hybrid PWM [28]	Increased comparisons at higher levels [29]
SCSS [27]	Separate level and polarity generators	Symmetrical	Switching function PWM at low frequency		Complicated at higher levels
T-type [20,21,22,23,24]	T-type: Extended without cascading [21,22]	Symmetrical	Multi reference PWM [22] Reduced carrier with logic gates [20,21]		Poor THD in line voltages [20,21,22]
	T-Type	Both	Modified reduced carrier PWM [50,51]	Synchronized PWM: Produces degraded line THD, if (fcr) ≠ 3n*fs fcr: carrier frequency & fs = modulating frequency
	Cascaded T-type: Extended with and without cascading [23,24]	Both	Fundamental frequency switching [23] Phase shifted multi reference [24]		Complicated at higher levels [23] and poor THD [23,24]
Basic unit MLI [18]	Separate level and polarity generators	Both	An algorithm based PWM		Complicated at higher levels and poor THD
Nested cell [30]	Common DC link to all phases	Both	SVPWM		Complicated at higher levels
Hybrid T-type [25,26]	Can be extended with and without cascading	Both	Low-frequency carrier switching [25,26]	Low-frequency switching [26]	Complicated at higher levels and poor THD [25,26]
E-type [19]	Extended by cascading	Asymmetrical		SHE	Complicated at higher levels and slow dynamic response
Reduced cascaded [33,34,35,36]	Extended to higher level by cascading	Both [33,35]		Hybrid PWM [33]
		Symmetrical [34]	Multi-reference with logic gates [34]		Complicated at higher levels and poor THD
		Asymmetrical [36]		Multi reference with low-frequency carrier [36]	Complicated at higher levels and poor THD
Switched capacitor hybrid MLI [32]	Extended by cascading or series connection of capacitor units	Symmetrical	Fundamental switching scheme		Complicated at higher levels and poor THD
Basic capacitor unit MLI [31]	Extended by series connection of capacitor units	Both		Hybrid PWM
RSC MLI with three phases [37,38,39]	With common DC link to three phases [37,39]	Asymmetrical [37,39]	Low-frequency reduced carrier using logical operators [38]	SVPWM [37,39]	Complicated at higher levels [37,39] and poor THD [38]
	Separate DC link to three-phases [38]	Symmetrical [38]

provides a brief overview of the reported modulation schemes for several RSC MLI configurations. Many different RSC MLI topologies have been reported, and each has its own set of advantages and disadvantages due to the modulation scheme it uses. In this paper, we propose a generalized PWM scheme for controlling symmetrical and asymmetrical RSC configurations, based on LSPWM techniques, to alleviate this issue. The paper begins by exploring the restrictions of the standard LSPWM method for RSC MLI strategies, and then moves on to explain how the proposed scheme works in practice.

Limitation of Conventional LSPWM to RSC Configurations

As shown in Figure 2, an LSPWM technique can be used to obtain seven different levels of phase voltage, and this is considered as a means of examining the restrictions imposed by traditional LSPWM on RSC configurations. Figure 2 represents the carrier, the modulating signal configuration, and the resulting switching pulses. Figure 2a depicts the relationship between the instantaneous values of the reference and carrier signals and the corresponding switching pulse, Pi. Figure 2a shows that the arranged gating pulses P1 through to P6 have a waveform similar to the seven-level phase voltage ranging from +3 V to −3 V, where ‘V’ represents the step size between adjacent phase-voltage levels. The P1 pulse was found to be the cause of the 2–3 V range of voltage. When P1 fluctuated between zero and one, the remaining lower pulses, P2 to P6, were all at their maximum levels. The obtainable voltage range of 0 to 2 V was the result of the P2 pulse. When P2 fluctuated between zero and one, the remaining lower pulses, P3 to P6, were all at high levels. Figure 2 depicts the characteristics of the conduction intervals Qi between each switching pulse Pi. Qi is determined by referring to Figure 2b.

$$\begin{array}{l}{\mathit{Q}}_{\mathit{i}}=1\hspace{0.17em}\mathit{;}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\mathit{reference}\hspace{0.17em}\hspace{0.17em}>\hspace{0.17em}\hspace{0.17em}{\mathit{Carrier}}_{\hspace{0.17em}\hspace{0.17em}{\mathit{i}}_{\min }}\\ {\mathit{Q}}_{\mathit{i}}=0\mathit{;}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\mathit{else}\end{array}$$

(1)

Conduction intervals Q1 through to Q6 are shown to overlap in Figure 2. By extending Pi across Qi, we captured the overlapping structure of Qi in Pi. Therefore, the overlapping character of the switching pulses reflects the fact that the devices accountable for obtaining the lower levels also maintain conduction at the higher levels. A 13-level asymmetrical configuration was taken into account to examine the effect of LSPWM’s switching nature on the actualization of RSC MLI topologies.

For a visualization of how these topologies switch between phases at various voltages, see

Table 2. Switching states of 13-level asymmetrical RSC-MLI topologies in Figure 1.

Voltage Level	MLDCL	CBSC	PUC	Hybrid T-Type	E-Type	Switched DC Sources	Cascaded T-Type	SSPS	RV
0	S2-S4-S6-H1-H4 S2-S4-S6-H3-H2 H1-H3 H2-H4	S1-S2 S3-S4 S5-S6 S7-S8	S8-S6-S4-S2 S1-S3-S5-S7	S3-S6-S4 S1-S5-S2	S6-S4-S2 S5-S3-S1	S4-S3-S2-S1 S5-S6-S7-S8	H4-H2-H8-H6 H1-H7-H5-H3	H1-H3 H3-H2	S2-S3-S4-H1-H4 S2-S3-S4-H3-H2 H1-H3 H2-H4
V	S4-S6-H1-H4-S1	S7-S6	S5-S3-S1-S8	S7-S4-S6	S4-S3-S8	S3-S2-S1-S5	S1-H8-H6-H4	S3-S4-H1-H4	S3-S4-H1-H4-S1
2 V	S6-H1-H4-S2-S3	S3-S2	S3-S1-S7-S6	S1-S4-S6 S6-S3-S8	S1-S8-S7 S4-S2-S5	S1-S5-S6-S7	H1-H8-H6-H4 S2-H4-H2-H8	S4-H1-H4-S1	S5-H1-H4-S2-S3-S6
3 V	S6-H1-H4-S1-S3 H1-H4-S2-S4-S5	S5-S4	S3-S1-S8-S6	S7-S8-S6	S5-S7-S1	S7-S8-S4-S3	S1-H8-S2-H4	S4-H1-H4-S2	S6-S4-H1-H4-S2
4 V	H1-H4-S1-S4-S5	S7-S4	S1-S8-S5-S4	S1-S8-S6	S1-S6-S4	S7-S8-S5-S3	H1-H8-S2-H4 S5-H4-H2-H8	S5-H1-H4-S3	S6-S4-H1-H4-S1
5 V	H1-H4-S2-S3-S5	S5-S2	S1-S7-S6-S4	S7-S2-S6	S1-S8-S4	S1-S4-S3-S7	S1-H8-H5-H4	S5-H1-H4-S1	S5-H1-H4-S2
6 V	H1-H4-S1-S3-S5	S7-S2	S1-S8-S6-S4	S1-S2-S6	S1-S5-S4	S1-S5-S3-S7	H1-H8-H5-H4	S5-H1-H4-S2	S5-H1-H4-S1
−V	S4-S6-H2-H3-S1	S8-S5	S6-S4-S2-S7	S5-S2-S7	S3-S1-S8	S6-S7-S8-S4	H3-H5-H7-S1	S3-S4-H3-H2	S3-S4-H3-H2-S1
−2 V	S6-H3-H2-S2-S3	S4-S1	S4-S2-S8-S5	S5-S2-S3 S5-S1-S8	S2-S8-S7 S3-S1-S6	S8-S4-S3-S2	H3-H5-H7-H2 H7-H1-H3-S2	S4-H3-H2-S1	S5-H3-H2-S2-S3-S6
−3 V	S6-H3-H2-S1-S3 H3-H2-S2-S4-S5	S6-S3	S4-S2-S7-S5	S5-S8-S7	S2-S6-S7	S2-S1-S5-S6	H3-S2-H7-S1	S4-H3-H2-S2	S6-S4-H3-H2-S2
−4 V	H3-H2-S1-S4-S5	S8-S3	S2-S7-S6-S3	S4-S1-S5	S2-S5-S3	S2-S1-S4-S6	H7-H1-H3-H6 H3-S2-H7-H2	S5-H3-H2-S3	S6-S4-H3-H2-S1
−5 V	H3-H2-S2-S3-S5	S6-S1	S2-S8-S5-S3	S7-S5-S4	S2-S8-S3	S8-S5-S6-S2	H3-H6-H7-S1	S5-H3-H2-S1	S5-H3-H2-S2
−6 V	H3-H2-S1-S3-S5	S8-S1	S2-S7-S5-S3	S4-S3-S5	S2-S6-S3	S8-S4-S6-S2	H3-H6-H7-H2	S5-H3-H2-S2	S5-H3-H2-S1

. Devices that are responsible for achieving lower levels may lose conduction at higher levels, as shown in the table. When applied to these topologies, it was revealed that the LSPWM scheme was unable to realize fully the majority of the possible switching states. A consequence of this is that the typical LSPWM scheme used to regulate RSC MLI topologies is exposed as inadequate. Therefore, a more flexible LSPWM scheme is proposed as a means of overcoming this restriction. Figure 2 depicts the modified conduction intervals (Ci) that can be obtained once the overlapping nature of the conduction intervals (Qi) is removed.

3. Proposed Generalized LSPWM Scheme

The proposed modulation scheme uses (n1) carriers to generate n distinct phase-voltage states. Similar to the standard LSPWM technique depicted in Figure 2, its carrier arrangement is relatively simple. Here, the switching pulse Pi is applied across Ci, the non-overlapped conduction interval, rather than Qi, the overlapped conduction interval. When maximum and minimum carrier conditions are considered, non-overlapping conduction intervals (Ci) are obtained. In contrast, as complexity increases, the number of comparisons grows and with this the difficulty of putting it into practice increases. Logical operators are used in the proposed method to simplify the situation.

Figure 3 depicts Qi and Ci together (for seven-level phase voltage), indicating that the desired conduction interval Ci can be obtained by performing a logical operation on Qi with its adjacent bands. From Figure 3a, observing Q₁ and C₁ reveals the identical nature of their switching and hence:

$$C_1=Q_1$$

(2)

In Figure 3b, Q₂ and C₂ are different from each other such that the following relationships are obtained:

If Q₁ = 0 and Q₂ = 0, then C₂ = 0

If Q₁ = 1 and Q₂ = 1, then C₂ = 0

If Q₁ = 0 and Q₂ = 1, then C₂ = 1

It should be noted that the Q₁ = 1 and Q₂ = 0 condition does not appear, which is because the lower conduction interval Q₂ always remains high when the higher conduction interval Q₁ is high. To obtain a logical relation for C₂ in terms of Q₁ and Q₂, a two-variable Karnaugh map (K-map) is presented in Figure 4a. According to Figure 4a, the logical relation for C₂ is obtained as $C_2={\overline{Q}}_1\hspace{0.17em}\hspace{0.17em}{Q}_2$. To realize this logic in hardware, two logic gates NOT and AND are required. To reduce these logic gates, a don’t care variable is included in the K-map and the logical relation (3) is obtained, which requires an Ex-OR gate.

$$C_2=\hspace{0.17em}{\overline{Q}}_1\hspace{0.17em}{Q}_2+Q_1\hspace{0.17em}{\overline{Q}}_2=Q_2\oplus Q_1$$

(3)

To obtain the conduction interval C₃, Figure 4c is considered. From Figure 4c, the following relationships are obtained:

If Q₂ = 0 and Q₃ = 0, then C₃ = 0

If Q₂ = 1 and Q₃ = 1, then C₃ = 0

If Q₂ = 0 and Q₃ = 1, then C₃ = 1

With the help of the K-map shown in Figure 4b, logical relation Equation (4) is obtained for conduction interval C₃:

$$C_3=\hspace{0.17em}{Q}_3\oplus Q_2$$

(4)

Similarly, to obtain conduction intervals C₄, C₅, and C₆, Figure 3d–f is considered, respectively. The corresponding K-maps for these figures are given in Figure 4c–e, respectively. From these figures, the following relations are obtained for C₄, C₅, and C₆:

$$C_4=\hspace{0.17em}{Q}_4\oplus Q_3$$

(5)

$$C_5=\hspace{0.17em}{Q}_5\oplus Q_4$$

(6)

$$C_6=\hspace{0.17em}{Q}_6\oplus Q_5$$

(7)

Under Overmodulation: During overmodulation using Equation (1) for determining the last carrier’s conduction interval Q₆, it was observed that Q₆ remains low for references less than its Carrier_6-min. However, this is contradictory to the actual conduction interval of the switching pulse P₆ which remains high and generates pulses.

Under this condition, obtaining the desired conduction interval C₆ from Equation (7) results in C₆ = 0, which is contradictory to Figure 2c. Therefore, the switching logic to define this conduction interval (Q_i) should be altered as follows:

$$\begin{array}{l}for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}1\le i\le \hspace{0.17em}\hspace{0.17em}5\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_i=1\hspace{0.17em};\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}reference\hspace{0.17em}\hspace{0.17em}>\hspace{0.17em}\hspace{0.17em}Carrie{r}_{\hspace{0.17em}{i}_{\min }}\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_i=0;\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}else\\ for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}i=6\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_6=1\hspace{0.17em};\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}reference\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\le Carrie{r}_{\hspace{0.17em}{i}_{\max }}\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_6=0;\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}else\end{array}$$

(8)

The modified conduction interval Q₆ obtained from Equation (8) and the desired conduction interval C₆ shown in Figure 4c are shown together in Figure 5. From this figure, it can be observed that the modified Q₆ and C₆ are identical. Therefore, the logical relation to obtain C₆ in Equation (7) should be modified to Equation (9) and this is valid for both overmodulation and undermodulation.

$$C_6=Q_6$$

(9)

Summarizing Equations (2)–(6) and (9) as:

$$\begin{array}{l}for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}2\le i\le \hspace{0.17em}\hspace{0.17em}5\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_i=Q_i\oplus Q{\hspace{0.17em}}_{i-1}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\\ for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}i=1\hspace{0.17em}\hspace{0.17em}and\hspace{0.17em}\hspace{0.17em}6\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_i=Q_i\hspace{0.17em}\end{array}$$

(10)

The generalization of Equations (8) and (10) to obtain n levels in phase voltage is expressed as follows:

$$\begin{array}{l}for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}1\le i\le \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}(n-2)\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_i=1\hspace{0.17em};\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}reference\hspace{0.17em}\hspace{0.17em}>\hspace{0.17em}\hspace{0.17em}Carrie{r}_{\hspace{0.17em}{i}_{\min }}\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_i=0;\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}else\\ for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}i=(n-1)\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_{(n-1)}=1\hspace{0.17em};\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}reference\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\le Carrie{r}_{\hspace{0.17em}{i}_{\max }}\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{Q}_{(n-1)}=0;\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}else\end{array}$$

(11)

$$\begin{array}{l}for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}i=1\hspace{0.17em}\hspace{0.17em}and\hspace{0.17em}\hspace{0.17em}(n-1)\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_i=Q_i\hspace{0.17em}\\ for\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}2\hspace{0.17em}\hspace{0.17em}\le i\le \hspace{0.17em}\hspace{0.17em}(n-2)\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_i=Q_i\oplus Q{\hspace{0.17em}}_{i-1}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\end{array}$$

(12)

4. Implementation of Proposed Scheme to Various 13-Level RSC MLIs

By applying the proposed generalized LSPWM scheme to the 13-level RSC MLI topologies depicted in Figure 6 and Figure 7, we were able to confirm the scheme’s efficacy and discuss its application to a subset of these topologies. Five different topologies were chosen: MLDCL, CBSC, PUC, hybrid T-type, and E-type.

Table 3. Logical relationship to obtain desired conduction interval (C) of the proposed scheme for 13-level phase voltage.

Q1	Q2	Q3	Q4	Q5	Q6	Q7	Q8	Q9	Q10	Q11	Q12	C1	C2	C3	C4	C5	C6	C7	C8	C9	C10	C11	C12
1	1	1	1	1	1	1	1	1	1	1	0	1	0	0	0	0	0	0	0	0	0	0	0
0	1	1	1	1	1	1	1	1	1	1	0	0	1	0	0	0	0	0	0	0	0	0	0
0	0	1	1	1	1	1	1	1	1	1	0	0	0	1	0	0	0	0	0	0	0	0	0
0	0	0	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0	0	0	0	0	0	0
0	0	0	0	1	1	1	1	1	1	1	0	0	0	0	0	1	0	0	0	0	0	0	0
0	0	0	0	0	1	1	1	1	1	1	0	0	0	0	0	0	1	0	0	0	0	0	0
0	0	0	0	0	0	1	1	1	1	1	0	0	0	0	0	0	0	1	0	0	0	0	0
0	0	0	0	0	0	0	1	1	1	1	0	0	0	0	0	0	0	0	1	0	0	0	0
0	0	0	0	0	0	0	0	1	1	1	0	0	0	0	0	0	0	0	0	1	0	0	0
0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1	0
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	1

displays the ideal conduction times (Ci) required to achieve the desired output level in a 13-level inverter, making it possible to put this scheme into action. This table was calculated by changing n in Equations (11) to 13. Table 3 demonstrates that the preferred conduction intervals do not overlap with one another. For a 13-level inverter where a certain level is required,

Table 4. Selection of switching devices to control 13-level inverter with the proposed scheme.

Conduction Interval (Ci)	State of Switching Pulse (Pi)	Switching Devices to Be Selected to Obtain Required Voltage
		MLDCL	CBSC	PUC	Hybrid T-Type	E-Type
C1 = 1 (5 V to 6 V) band	P1 =1 (6 V state)	S3-S5-H1-H4-S1	S7-S2	S1-S8-S6-S4	S1-S2-S6	S1-S5-S4
	P1 =0 (5 V state)	S5-H1-H4-S2-S3	S5-S2	S1-S7-S6-S4	S7-S2-S6	S1-S8-S4
C2 = 1 (4 V to 5 V) band	P2 =1 (5 V state)	S5-H1-H4-S2-S3	S5-S2	S1-S7-S6-S4	S7-S2-S6	S1-S8-S4
	P2 = 0 (4 V state)	S4-S5-H1-H4-S1	S7-S4	S1-S8-S5-S4	S1-S8-S6	S1-S6-S4
C3 = 1 (3 V to 4 V) band	P3 = 1 (4 V state)	S4-S5-H1-H4-S1	S7-S4	S1-S8-S5-S4	S1-S8-S6	S1-S6-S4
	P3 = 0 (3 V state)	H1-H4-S2-S4-S5	S5-S4	S3-S1-S8-S6	S7-S8-S6	S5-S7-S1
C4 = 1 (2 V to 3 V) band	P4 = 1 (3 V state)	H1-H4-S2-S4-S5	S5-S4	S3-S1-S8-S6	S7-S8-S6	S5-S7-S1
	P4 = 0 (2 V state)	S6-H1-H4-S2-S3	S3-S2	S3-S1-S7-S6	S1-S4-S6	S1-S8-S7
C5 = 1 (V to 2 V) band	P5 = 1 (2 V state)	S6-H1-H4-S2-S3	S3-S2	S3-S1-S7-S6	S1-S4-S6	S1-S8-S7
	P5 = 0 (V state)	S4-S6-H1-H4-S1	S7-S6	S5-S3-S1-S8	S7-S4-S6	S4-S2-S8
C6 = 1 (0 to V) band	P6 = 1 (V state)	S4-S6-H1-H4-S1	S7-S6	S5-S3-S1-S8	S7-S4-S6	S4-S2-S8
	P6 = 0 (0 state)	S2-S4-S6-H1-H4	S7-S8	S1-S3-S5-S7	S4-S6-S3	S6-S4-S2
C7 = 1 (−V to 0) band	P7 = 1 (0 state)	S2-S4-S6-H3-H2	S5-S6	S1-S3-S5-S7	S2-S1-S5	S5-S3-S1
	P7 = 0 (−V state)	S4-S6-H3-H2-S1	S8-S5	S6-S4-S2-S7	S5-S2-S7	S3-S1-S8
C8 = 1 (−2 V to −V) band	P8 = 1 (−V state)	S4-S6-H3-H2-S1	S8-S5	S6-S4-S2-S7	S5-S2-S7	S3-S1-S8
	P8 = 0 (−2 V state)	S6-H3-H2-S2-S3	S4-S1	S4-S2-S8-S5	S5-S2-S3	S2-S8-S7
C9 = 1 (−3 V to −2 V) band	P9 = 1 (−2 V state)	S6-H3-H2-S2-S3	S4-S1	S4-S2-S8-S5	S5-S2-S3	S2-S8-S7
	P9 = 0 (−3 V state)	H3-H2-S2-S4-S5	S6-S3	S4-S2-S7-S5	S5-S8-S7	S2-S6-S7
C10 = 1 (−4 V to −3 V) band	P10 = 1 (−3 V state)	H3-H2-S2-S4-S5	S6-S3	S4-S2-S7-S5	S5-S8-S7	S2-S6-S7
	P10 = 0 (−4 V state)	S4-S5-H3-H2-S1	S8-S3	S2-S7-S6-S3	S4-S1-S5	S2-S5-S3
C11 = 1 (−5 V to −4 V) band	P11 = 1 (−4 V state)	S4-S5-H3-H2-S1	S8-S3	S2-S7-S6-S3	S4-S1-S5	S2-S5-S3
	P11 = 0 (−5 V state)	H3-H2-S2-S3-S5	S6-S1	S2-S8-S5-S3	S7-S5-S4	S2-S8-S3
C12 = 1 (−6 V to −5 V) band	P12 = 1 (−5 V state)	H3-H2-S2-S3-S5	S6-S1	S2-S8-S5-S3	S7-S5-S4	S2-S8-S3
	P12 = 0 (−6 V state)	H3-H2-S1-S3-S5	S8-S1	S2-S7-S5-S3	S4-S3-S5	S2-S6-S3

shows which switching devices can be used to obtain this. In order to construct this table, we first mapped the desired conduction interval to the switching pulse state.

Computer simulation studies conducted in a MATLAB/Simulink environment were used to probe the effectiveness of the proposed scheme. Considering the value of each DC source voltage as 100 V, Simulink investigations were conducted for 13-level MLDCL, CBSC, PUC, hybrid T-type, and E-type asymmetrical topologies. A 13-level symmetrical CHB MLI was also simulated to verify the proposed scheme’s compatibility with the standard LSPWM scheme. Conventional LSPWM was used to regulate this inverter. The harmonic spectra and phase-voltage simulation results are displayed in Figure 6. The results of the proposed method and its effects on the phase voltages of the 13-level MLDCL, CBSC, PUC, hybrid T-type, and E-type asymmetrical topologies are shown in Figure 6a–e. The phase-voltage performance of a standard LSPWM-controlled 13-level symmetrical CHB MLI is shown in Figure 6f.

There is a striking similarity between the waveforms and harmonic spectra depicted in Figure 6a–e, where the wave shapes and harmonic spectra of phase voltages recorded using the proposed scheme for MLDCL (2.03%), CBSC (2.13%), PUC (2.13%), hybrid T-type (2.03%), and E-type (2.03%) topologies were nearly identical to the THD recorded for CHB (2.13%) with LSPWM-IPD.

The line-voltage simulation results and harmonic spectra are displayed in Figure 7. The line-voltage performances of the proposed method for 13-level asymmetrical topologies are shown in Figure 7a–e. The line-voltage performance of 13-level symmetrical CHB MLI with conventional LSPWM is shown in Figure 7f. Figure 7 shows that the THD value was nearly 1.6% across the board, indicating that all the waveforms were equivalent. Specifically, Figure 7a–e shows that the wave shapes and harmonic spectra of the line voltages recorded using the proposed scheme for MLDCL (1.63%), CBSC (1.61%), PUC (1.61%), hybrid t-Type (1,61%), and E-type (1.63%) topologies were nearly identical to the THD recorded for CHB (1.61%) with LSPWM-IPD.

Thus, Figure 6 and Figure 7 show that the proposed scheme is able to yield the same performance across all possible topologies of RSC MLI. It was noted that the proposed scheme performs just as well as traditional LSPWM-IPD.

5. Experimental Results

The proposed modulation scheme was tested by observing the performance of a set of experiments involving three-phase thirteen-level asymmetrical RSC MLI topologies (MLDCL, CBSC, PUC, hybrid T-type, and E-type) built using the IGBT module. A 13-level symmetrical CHB MLI was also developed and controlled using a conventional LSPWM scheme, to verify the proposed scheme’s consistency with the standard method. Figure 8 and Figure 9 depict the experimental results for phase- and line-voltage performance, respectively. Loading the proposed modulation schemes onto the dSPACE-DS1104 R&D controller allowed the experiment to be conducted. The prototype 13-level inverter was constructed with three 24-switch IGBT-based inverter modules, where the 24 isolated IGBTs (with antiparallel diodes) can be freely interconnected according to the topological arrangement of any RSC-MLI. Single and dual-channel DC supplied power to the inverter, and the use of stabilized power maintained the supply in the 30 V/5 A range. We assumed a sampling rate of 50 nS for the controller. To stop the inverter leg from shooting through, a dead time circuit with a 2 µS dead time/delay time was developed.

Figure 10 depicts the full experimental setup. With an amplitude modulation index of 0.95, the carrier signal frequency was set to 3 kHz. To achieve a maximum phase-voltage amplitude of 180 V, a minimum DC input source voltage of 30 V was chosen.

The performance of RSC topologies and CHB in terms of phase voltage during the experiments is depicted in Figure 8. There is a striking similarity between the wave forms and harmonic spectra depicted in Figure 8a–e, where the wave shapes and harmonic spectra of experimental phase voltage recorded for the proposed scheme for MLDCL (2.3%), CBSC (2.3%), PUC (2.3%), hybrid T-Type (2.2%), and E-type (2.4%) topologies are nearly identical to the THD recorded for CHB (2.3%) with LSPWM-IPD. Thus, the wave shapes and harmonic spectra of all the recorded phase-voltage outputs had similar THD values of 2.3%, making them visually equivalent. In addition, it is important to note that the side-band harmonics of these spectra are identical and centered at m_f = 60 (this is not visible because the power-quality analyzer (Fluke 435 Series II) measures only up to the 49th order harmonic). After testing, it was clear that the hardware’s experimental performance matched the simulations.

The experimental line-voltage performance of the proposed scheme for the considered thirteen-level RSC MLI topologies and the traditional LSPWM for CHB is shown in Figure 9. The respective harmonic spectra and total harmonic distortion (THD) of these line-voltage wave forms were found to be identical. Note also that for m_f = 60, the side-band harmonics of these spectra were also identical. Specifically, Figure 9a–e shows that the wave shapes and harmonic spectra of the experimental line voltage recorded for the proposed scheme for MLDCL (1.9%), CBSC (1.8%), PUC (1.9%), hybrid T-Type (1.9%), and E-type (1.8%) topologies were nearly identical to the THD recorded for CHB (1.8%) with LSPWM-IPD. In addition, the identical nature of the line-voltage waveforms can be confirmed by referring to the Figure 7, lending credence to the simulation results presented earlier.

Finally, the comparative harmonic performance of the proposed scheme on the various thirteen-level asymmetrical configurations is tabulated in

Table 5. Comparative performance of simulation and experimental THD.

Comparative Harmonic Performance of Proposed Scheme on Various Thirteen Level RSC-MLI Configurations
RSC MLI Topology [37,38,39]	Line-Voltage THD		Phase-Voltage THD
	Experimental	Simulation	Experimental	Simulation
MLDCL [13]	1.9%	1.63%	2.3%	2.03%
CBSC [15]	1.8%	1.61%	2.3%	2.13%
PUC [14]	1.9%	1.61%	2.3%	2.13%
Hybrid T-type [25,26]	1.9%	1.61%	2.2%	2.13%
E-type [19]	1.8%	1.63%	2.4%	2.03%
CHB [48]	1.8%	1.61%	2.3%	2.13%

, with corresponding comprehensive summaries of the simulation and experimental environment. The data in Table 5 were retrieved from the simulation phase and line THD depicted in Figure 6 and Figure 7, and the experimental phase and line THD shown in Figure 8 and Figure 9, respectively. Therefore, it was also experimentally verified that the proposed modulation scheme can be applied to any RSC MLI topology, resulting in identical performance to the conventional LSPWM technique.

6. Conclusions

This research looked at why traditional LSPWM methods failed to manage RSC MLI topologies, and developed an extended LSPWM scheme that works with symmetric and asymmetric RSC MLI networks. The suggested switching technique makes use of a simple Ex-OR logical expression for its switching logic, and this logical connection can be simply extended to accommodate an arbitrary number of levels. Furthermore, the suggested methodology yielded good harmonic performance, which was consistent with the standard LSPWM method. Multiple three-phase 13-level asymmetrical RSC MLI topologies were simulated and tested experimentally to ensure the method worked as intended. The phase- and line-voltage findings obtained in both the simulation and the experiment are consistent with the results of the traditional LSPWM approach applied to symmetrical CHB MLI.