A Single Source Self-Balanced Boost MLI with Reduced Part Count for EV Applications

Abstract

As the use of inductor-based topologies demands a large amount of space, capacitor-based topologies have garnered attention. Electric Vehicles (EVs) are usually equipped with two-level inverters, which require separate control strategies for each level and synchronizing the strategies increases the complexity of operation and makes them unreliable. Therefore, a single-stage converter with boost and conversion abilities with better power quality at optimal component count and efficiency is needed. A novel capacitor-based boost multilevel inverter (CB-MLI) topology is proposed in this paper as it is found suitable for EV and HEV applications. It is capable of generating an eleven-level waveform with only eleven switches, three capacitors, and a single isolated source. The self-balancing property of the capacitors makes the topology one of a kind. A constant carrier PWM-based control strategy is utilized to switch the IGBTs. Testing results from hardware setup confirm the proposed capacitor-based CB-MLI topology operating modes and potentiality. Lastly, by highlighting the proposed and existing MLI circuits, the benefits of the recommended configuration are outlined by component count and total cost. Additionally, it is a simplified design that needs fewer footprint areas and space.

1. Introduction

Demand for EVs [1] has been increasing rapidly as a result of the environmental issues and fuel scarcity associated with combustion engine vehicles. First-generation EVs use DC motors [2] to produce the tractive effort required by the vehicle to advance [3]. It did not take many years for the DC motors to lose their significance in the EV domain when researchers found AC motors offer more desirable characteristics than DC motors with better efficiency. Almost all EVs are equipped with distributed AC motors for vehicle propulsion nowadays. It is a well-established fact that all EVs are powered by battery systems [4], a DC form of electricity [5]. The voltage level of the battery systems [6] is at a low level, thus forcing us to introduce a voltage boost and DC-to-AC conversion before feeding the battery unit power to AC MOTOR.

Power semiconductor devices were revolutionized in the early 1990s because of their efficient conversion [7] and control abilities [8]. The extensive power handling capability at compact sizes is a significant advantage. The major problem associated with the use of power semiconductor devices is harmonics. The harmonics are imposed over the fundamental cause wave shape to deviate from the sinusoidal. Smoothing the deviated waveform demands large inductance and capacitance values in order to filter out harmonics. The EV power source is a DC form of electricity, and EV motors demand AC supply at a high frequency. It incorporates a need for a DC–AC converter (essentially, an inverter [9]), along with the voltage boost [10] capability in EV [11]. The Inverter topologies are advancing in such a way as to nullify filter requirements completely in the converter. The first step towards achieving that was the invention of multilevel inverters (MLI).

The basic H-bridge inverter [12] produces a square waveform that contains all the odd harmonics with a total THD of 48.3%. In the same H-bridge converter, when operated with the three-level waveform (with a pulse width of 120), the THD value tumbles to 31.1%. With a single-step waveform, it even eliminated the triplen harmonics out of the waveform essentially without any use of filter, and the THD value further descreases as the number of levels in the waveform increases. We can say the THD value of a waveform is inversely proportional to the number of steps in the waveform. In addition to the output wave shape, MLIs offer additional advantages such as reduced dv/dt stress on switches, lower common mode voltage, lower input current distortion, and reduced filter ratings.

The problem with the conventional MLIs, such as cascaded H-bridge, are the multi-source requirements which are an unlikely case in the practical world. To avoid the isolated source requirement, we shifted to diode-clamped MLI, where we use a cascaded capacitor technique for voltage division, which also demands a large device count as the number of levels increases. Clamping of levels is achieved with the help of diodes. In flying capacitor MLI topology [12], capacitors are used to maintain levels instead of diodes. All the basic topologies [13,14] demand a large switch count, and a large number of capacitors is required in NPC. This forces us to look into new topologies with all the advantages of MLIs but with a reduced component count.

Boost and inversion of voltage with multiple stages [15] make the conversion circuit bulky and unreliable. Thus, a topology that boosts and inverts the DC supply in a single stage offers better results with compact and economic advantages. The boost MLIs [15] are finding recognition in the recent trend as the advantages offered are far superior to those of the conventional systems. The circuit compactness and lower THD with boosting capability are major among them.

High device count and voltage stress in the converter are the significant shortcomings of circuits as the boosting gain increases. These limitations influence the overall cost of the converter significantly. Therefore, the converter should not undergo a greater component count and total standing voltage (TSV) for a cost-effective solution. Hence, a topology of capacitor-based 2.5 times boost, 11-level inverter is proposed. The topology demands only 11 switches, out of which 2 are complimentary, and there are three capacitors with a single DC-voltage source. The maximum blocking voltage of the switch decides the ratings and economics of the circuit. The topology demands four switches with a blocking voltage of 1.5${\mathrm{V}}_{\mathrm{dc}}$ and the all remaining switches with the voltage of ${\mathrm{V}}_{\mathrm{dc}}$. The total standing voltage of the topology is 12.5${\mathrm{V}}_{\mathrm{dc}}$. The voltage boost is achieved by significant charging and discharging of capacitors. The capacitors with a rating of 0.5${\mathrm{V}}_{\mathrm{dc}}$ are required. As all the capacitors are used in aiding with the source, the circuit delivers a maximum boost, which is 2.5${\mathrm{V}}_{\mathrm{dc}}$.

One of the major advantages associated with the proposed topology is the capacitors’ self-balancing property. During the charging of capacitors, the source feeds supply to capacitors through switches, whose on-state resistances are very low, thus making the charging time of capacitors low in value, but when the capacitors start to feed load, the resistance seen by the capacitors is of a high value. This makes the capacitors’ charging time far faster than the discharging time. As the charging time is far lesser than the discharging time, even before it discharges, the capacitor becomes charged, thus causing the capacitor to maintain its voltage at around 0.5 Vdc with lower ripple. The essential aspects of the recommended topology are:

• Smaller part count;
• The eleven-level load voltage generation with 2.5-times boost capability;
• Inherent self-balance ability and being simple to control;
• There are no limitations on the power factor or modulation index;
• To generate bipolar levels, no extra H-bridge is required;
• Lower total standing voltage (TSV).

This work aims to develop a novel voltage boost inverter circuit with a smaller component count and low TSV by mitigating the shortcomings. A thorough analysis of the working principle is discussed in Section 2. Section 3 presents modulation, capacitor size, and power loss calculations. The corresponding simulation results for the proposed circuit are provided in Section 4. To support the claims of the proposed inverter, sufficient hardware verification is presented in Section 5. Additionally, quantitative and cost analyses are performed to distinguish the merits of the proposed converter in Section 6. Finally, the conclusions are presented in Section 7.

2. Proposed Topology

2.1. Description of Proposed Topology

The proposed boost-MLI structure based on the switched capacitors is shown in Figure 1. This design pattern has a leg on two ends to produce load voltages with both negative and positive waveforms. The suggested circuit contains 11 semiconductor-switching devices (${\mathrm{S}}_1$ and ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_9$ and ${\overline{\mathrm{S}}}_9$, ${\mathrm{S}}_2$, ${\mathrm{S}}_3$, ${\mathrm{S}}_4$, ${\mathrm{S}}_5$, ${\mathrm{S}}_6$, ${\mathrm{S}}_7$, and ${\mathrm{S}}_8$), and an isolated DC-voltage source (${\mathrm{V}}_{\mathrm{dc}}$). Additionally, the suggested structure includes three boosting capacitors (${\mathrm{C}}_1$, ${\mathrm{C}}_2$, and ${\mathrm{C}}_3$) to minimize the requirement of the number of sources. ${\mathrm{V}}_{{\mathrm{C}}_1}$, ${\mathrm{V}}_{{\mathrm{C}}_2}$, and ${\mathrm{V}}_{{\mathrm{C}}_3}$ are the voltages across the capacitors ${\mathrm{C}}_1$, ${\mathrm{C}}_2$, and ${\mathrm{C}}_3$, respectively. The recommended boost-MLI topology uses the fundamental frequency PWM (FF-PWM) control switching method to provide eleven voltage levels at the load end. The possible magnitude of voltage levels are +2.5${\mathrm{V}}_{\mathrm{dc}}$, +2${\mathrm{V}}_{\mathrm{dc}}$, +$1.5{\mathrm{V}}_{\mathrm{dc}}$, +${\mathrm{V}}_{\mathrm{dc}}$, +0.5${\mathrm{V}}_{\mathrm{dc}}$, zero (0${\mathrm{V}}_{\mathrm{dc}}$), and −0.5${\mathrm{V}}_{\mathrm{dc}}$, −${\mathrm{V}}_{\mathrm{dc}}$, −1.5${\mathrm{V}}_{\mathrm{dc}}$, −2${\mathrm{V}}_{\mathrm{dc}}$, −2.5${\mathrm{V}}_{\mathrm{dc}}$. The significant switching sequence needed to build the eleven levels of the proposed boost-MLI topology is shown in

Table 1. Switching states for Proposed CB-MLI.

${\mathbf{V}}_{\mathbf{o}}$	${\mathbf{S}}_1$	${\mathbf{S}}_2$	${\mathbf{S}}_3$	${\mathbf{S}}_4$	${\mathbf{S}}_5$	${\mathbf{S}}_6$	${\mathbf{S}}_7$	${\mathbf{S}}_8$	${\mathbf{S}}_9$	${\mathbf{V}}_{{\mathbf{C}}_1}$	${\mathbf{V}}_{{\mathbf{C}}_2}$	${\mathbf{V}}_{{\mathbf{C}}_3}$
$2.5{\mathrm{V}}_{\mathrm{dc}}$	1	0	0	0	1	1	1	0	0	D	D	D
$2{\mathrm{V}}_{\mathrm{dc}}$	1	0	1	0	1	0	1	0	0	D	D	-
$1.5{\mathrm{V}}_{\mathrm{dc}}$	1	1	0	0	0	1	1	1	0	D	C	C
$1{\mathrm{V}}_{\mathrm{dc}}$	1	0	1	1	0	0	1	1	0	C	C	-
$0.5{\mathrm{V}}_{\mathrm{dc}}$	1	1	0	0	0	0	1	0	1	D	-	-
0	1	0	0	1	0	0	1	0	1	-	-	-
0	0	0	0	0	0	1	0	1	0	-	-	-
−$0.5{\mathrm{V}}_{\mathrm{dc}}$	0	0	1	0	0	0	0	1	0	-	-	D
−$1{\mathrm{V}}_{\mathrm{dc}}$	0	0	1	0	0	0	0	1	0	-	C	C
−$1.5{\mathrm{V}}_{\mathrm{dc}}$	0	0	1	1	0	0	1	1	1	C	C	D
−$2{\mathrm{V}}_{\mathrm{dc}}$	0	1	0	0	1	0	0	1	1	-	D	D
−$2.5{\mathrm{V}}_{\mathrm{dc}}$	0	0	0	1	1	0	0	1	1	D	D	D

C: Charging; D: Discharging; -: No effect.

.

2.2. Modes of Operation

For the proposed CB-MLI topology, the different levels of output waveforms are developed by firing appropriate switches, as mentioned in Table 1. The conduction paths of the topology are illustrated graphically in Figure 2 and Figure 3. ${\mathrm{V}}_{{\mathrm{C}}_1}$, ${\mathrm{V}}_{{\mathrm{C}}_2}$, and ${\mathrm{V}}_{{\mathrm{C}}_3}$ are the voltages across the capacitors ${\mathrm{C}}_1$, ${\mathrm{C}}_2$, and ${\mathrm{C}}_3$, respectively. The operating modes of the proposed topology are as follows.

(1) +2.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 2A]: The switches ${\mathrm{S}}_1$, ${\mathrm{S}}_5$, ${\mathrm{S}}_6$, ${\mathrm{S}}_7$, and ${\overline{\mathrm{S}}}_9$ are triggered to achieve the output as 2.5${\mathrm{V}}_{\mathrm{dc}}$. During this state source, the capacitors ${\mathrm{C}}_1$ and ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ feed the load. The corresponding flow path is depicted in Figure 2A. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0={\mathrm{V}}_{{\mathrm{C}}_1}+{\mathrm{V}}_{{\mathrm{C}}_2}+{\mathrm{V}}_{{\mathrm{C}}_3}+{\mathrm{V}}_{\mathrm{dc}}=2.5{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(1)

(2) +2${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 2B]: The switches ${\mathrm{S}}_1$, ${\mathrm{S}}_3$, ${\mathrm{S}}_5$, ${\mathrm{S}}_7$, and ${\overline{\mathrm{S}}}_9$ are triggered to achieve the output as 2${\mathrm{V}}_{\mathrm{dc}}$. During this state source, the capacitors ${\mathrm{C}}_1$ and ${\mathrm{C}}_2$ feed the load. The corresponding flow path is depicted in Figure 2B. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0={\mathrm{V}}_{{\mathrm{C}}_1}+{\mathrm{V}}_{{\mathrm{C}}_2}+{\mathrm{V}}_{\mathrm{dc}}=2{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(2)

(3) +1.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 2C]: The switches ${\mathrm{S}}_1$, ${\mathrm{S}}_2$, ${\mathrm{S}}_7$, and ${\overline{\mathrm{S}}}_9$ are triggered to achieve the output as 1.5${\mathrm{V}}_{\mathrm{dc}}$. In this state, the capacitor ${\mathrm{C}}_1$ is made to support the source, feed the load, and thus achieve the desired 1.5${\mathrm{V}}_{\mathrm{dc}}$ as output. The capacitors ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ are charged through switches ${\mathrm{S}}_6$ and ${\mathrm{S}}_8$ to 0.5${\mathrm{V}}_{\mathrm{dc}}$ each during this level. The corresponding flow path is depicted in Figure 2C. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{\mathrm{C}1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0={\mathrm{V}}_{\mathrm{C}1}+{\mathrm{V}}_{\mathrm{dc}}=1.5{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(3)

(4) +${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 2D]: The switches ${\mathrm{S}}_1$, ${\mathrm{S}}_4$, ${\mathrm{S}}_7$, and ${\overline{\mathrm{S}}}_9$ are turned ON to achieve ${\mathrm{V}}_{\mathrm{dc}}$ output. Source, along with load feed, will charge the capacitors ${\mathrm{C}}_1$ and ${\mathrm{C}}_2$ through switches ${\mathrm{S}}_3$, and ${\mathrm{S}}_8$. As the resistances of switches during on-state is low, the charging time constant of capacitors is very low. The corresponding flow path is depicted in Figure 2D. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{\mathrm{C}1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0={\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(4)

(5) +0.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 2E]: The output 0.5${\mathrm{V}}_{\mathrm{dc}}$ can be achieved by firing the gates of ${\mathrm{S}}_1$, ${\mathrm{S}}_2$, ${\mathrm{S}}_7$, and ${\mathrm{S}}_9$ switches, thus making the capacitor ${\mathrm{C}}_1$ to feed power demanded by the load during this mode. As the discharging time constant is a far greater value than the charging time, the voltage fall across the capacitor is small. The capacitors ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ remain idle during this mode. All remaining switches are in blocking state. The corresponding flow path is depicted in Figure 2E. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0={\mathrm{V}}_{{\mathrm{C}}_1}=0.5{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(5)

(6) ZERO Mode [Figure 2F and Figure 3A]: During the output, zero modes have two sets of switching combinations. One involves the switches ${\mathrm{S}}_1$, ${\mathrm{S}}_4$, ${\mathrm{S}}_7$, and ${\mathrm{S}}_9$ being triggered, and the other combination is the switches ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_6$, ${\mathrm{S}}_8$, and ${\overline{\mathrm{S}}}_9$ being triggered. This shortens the load through the path, as depicted in Figure 2F and Figure 3A. The rest of the switches are in blocking state, and three capacitors remain idle during this mode, i.e., neither charging, nor discharging.

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_1}=0\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0\hfill \\ {\mathrm{V}}_0=0.\hfill \end{array}\right.$$

(6)

(7) −0.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 3B]: The output −0.5${\mathrm{V}}_{\mathrm{dc}}$ can be achieved by firing the gates of ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_3$, ${\mathrm{S}}_8$, and ${\overline{\mathrm{S}}}_9$ switches, thus making the capacitor ${\mathrm{C}}_3$ feed power demanded by the load during this mode. As the discharging time constant has a far greater value than the charging time, the voltage fall across the capacitor is small. The capacitors ${\mathrm{C}}_1$ and ${\mathrm{C}}_2$ remains idle during this mode. All remaining switches will be in blocking state. The corresponding flow path is depicted in Figure 3B. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_{{}_3}}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0=-{\mathrm{V}}_{{\mathrm{C}}_3}=-{\mathrm{V}}_{\mathrm{dc}}/2.\hfill \end{array}\right.$$

(7)

(8) −${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 3C]: The switches ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_6$, ${\mathrm{S}}_8$, and ${\mathrm{S}}_9$ are turned ON to achieve −${\mathrm{V}}_{\mathrm{dc}}$ output. Source, along with load feed, will charge the capacitors ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ through switches ${\mathrm{S}}_2$, and ${\mathrm{S}}_7$. As the resistances of switches during on-state is low, the charging time constant of capacitors is very low. The corresponding flow path is depicted in Figure 3C. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0=-{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(8)

(9) −1.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 3D]: The switches ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_3$, ${\mathrm{S}}_8$, and ${\mathrm{S}}_9$ are triggered to achieve the output as −1.5${\mathrm{V}}_{\mathrm{dc}}$. During this state, the capacitor ${\mathrm{C}}_1$ is made to support the source, feed the load, and thus achieve the desired −1.5${\mathrm{V}}_{\mathrm{dc}}$ as output. The capacitors ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ are charged through the switches ${\mathrm{S}}_4$ and ${\mathrm{S}}_7$ at this level. The corresponding flow path is depicted in Figure 3D. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{\mathrm{C}1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0=-{\mathrm{V}}_{{\mathrm{C}}_1}-{\mathrm{V}}_{\mathrm{dc}}=-3{\mathrm{V}}_{\mathrm{dc}}/2.\hfill \end{array}\right.$$

(9)

(10) −2${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 3E]: The switches ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_2$, ${\mathrm{S}}_5$, ${\mathrm{S}}_8$, and ${\mathrm{S}}_9$ are triggered to achieve the output as −2${\mathrm{V}}_{\mathrm{dc}}$. During this state source, the capacitors ${\mathrm{C}}_2$ and ${\mathrm{C}}_3$ feed the load. The corresponding flow path is depicted in Figure 3E. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0=-{\mathrm{V}}_{{\mathrm{C}}_2}-{\mathrm{V}}_{{\mathrm{C}}_3}-{\mathrm{V}}_{\mathrm{dc}}=-2{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(10)

(11) −2.5${\mathrm{V}}_{\mathrm{dc}}$ Mode [Figure 3F]: The switches ${\overline{\mathrm{S}}}_1$, ${\mathrm{S}}_4$, ${\mathrm{S}}_5$, ${\mathrm{S}}_8$ and ${\mathrm{S}}_9$ are triggered to achieve the output as −2.5${\mathrm{V}}_{\mathrm{dc}}$. During this state source, the capacitors ${\mathrm{C}}_1$, ${\mathrm{C}}_2$, and ${\mathrm{C}}_3$ feed the load. The corresponding flow path is depicted in Figure 3F. Thus, the resulting load voltage is expressed as

$$\left\{\begin{array}{c}{\mathrm{V}}_{{\mathrm{C}}_1}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_2}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_{{\mathrm{C}}_3}=0.5{\mathrm{V}}_{\mathrm{dc}}\hfill \\ {\mathrm{V}}_0=-{\mathrm{V}}_{{\mathrm{C}}_1}--{\mathrm{V}}_{{\mathrm{C}}_2}-{\mathrm{V}}_{\mathrm{C}3}-{\mathrm{V}}_{\mathrm{dc}}=-2.5{\mathrm{V}}_{\mathrm{dc}}.\hfill \end{array}\right.$$

(11)

3. Modulation Technique

Space vector, sinusoidal, selective harmonic elimination pulse width modulation (SV-, S-, SHE-PWM), and basic fundamental frequency switching are a few of the controlled modulation techniques [16] employed by power converters to produce a multilevel output, which is in the sinusoidal shape of voltage waveforms. Numerous different control techniques are stated in [17]. Here, the fundamental frequency PWM (FF-PWM) control technique [18] is employed to provide gating signals for semiconductor switches. Level-shifted constant carrier signals with similar phases are coupled with an ideal reference sinusoidal pulse to produce gating signals to drive the semiconductor switching devices. This control technique requires $(N_l-1)/2$ constant carrier signals to obtain the required output voltage with $N_l$ levels. In Figure 4, the designing model of the output voltage waveform at any given load is illustrated. At the output terminals, eleven voltage levels are produced using four constant carrier pulses ($ca{r}_1-ca{r}_4$) with the same frequency but different offset values for the voltage parameter. These higher-frequency constant carrier signals are frequently compared with an absolute value of sinusoidal reference pulse $(V_{ref}=|V_{m}sin\left(\omega t\right)\left|\right)$ to generate gating signals for the semiconductor switches. Table 1 lists the different operating modes described by the recommended control switching strategy for semiconductor switches. The amplitude modulation index ($m_a$) for triangular carrier pulses is determined as

$$\begin{array}{c}\hfill m_a=\frac{V_m}{\left(\frac{N_l-1}{2}\right)\times {\widehat{V}}_{Car}}\end{array}$$

(12)

Here, ${\widehat{V}}_{Car}$, and $V_m$ are peak magnitudes of carrier and reference pulses, respectively.

The recommended capacitor-based CB-MLI structure uses one reference signal with 50 HZ frequency, a fundamental sinusoidal frequency, and four carrier pulses. Numerous carrier signal patterns, such as triangular, ramping, trapezoidal, sinusoidal, etc., can also be used. The root mean square (RMS) value of the resultant output for eleven-level voltage at different $m_a$ values is expressed as follows:

$$\begin{array}{c}\hfill V_{ab}\simeq m_a\frac{V_{dc}}{\sqrt{2}}\end{array}$$

(13)

The suggested structure has the feasibility that it can operate with all the control modulation techniques. There is no impact on capacitor voltage balancing when the circuit performs at the lower range of frequencies. However, the capacitor size negligibly depends on the switching frequency. When the switching frequency rises, the desired output waveform of the voltage chops more frequently. Consequently, it will only obtain limited time intervals to gain charge.

The final switching equations derived from the above Figure 5 are as given for all semiconductor switches as follows:

$$\begin{array}{cc}\hfill {\mathrm{S}}_1& =\begin{array}{cc}\hfill & \mathrm{P}\hfill \end{array}\hfill \end{array}$$

(14)

$$\begin{array}{cc}\hfill {\mathrm{S}}_2& =\begin{array}{cc}\hfill & ({\mathrm{A}}_1·\overline{{\mathrm{A}}_2}+{\mathrm{A}}_3·\overline{{\mathrm{A}}_4})·\mathrm{P}+[({\mathrm{A}}_2·\overline{{\mathrm{A}}_3}·+{\mathrm{A}}_4·\overline{{\mathrm{A}}_5}]·\overline{\mathrm{P}}\hfill \end{array}\hfill \end{array}$$

(15)

$$\begin{array}{cc}\hfill {\mathrm{S}}_3& =\begin{array}{cc}\hfill & ({\mathrm{A}}_1·\overline{{\mathrm{A}}_2}+{\mathrm{A}}_3·\overline{{\mathrm{A}}_4})·\overline{\mathrm{P}}+[({\mathrm{A}}_2·\overline{{\mathrm{A}}_3}·+{\mathrm{A}}_4·\overline{{\mathrm{A}}_5}]·\mathrm{P}\hfill \end{array}\hfill \end{array}$$

(16)

$$\begin{array}{cc}\hfill {\mathrm{S}}_4& =\begin{array}{cc}\hfill & ({\mathrm{A}}_1·\overline{{\mathrm{A}}_2}+{\mathrm{A}}_3·\overline{{\mathrm{A}}_4}+{\mathrm{A}}_5)·\overline{\mathrm{P}}+[({\mathrm{A}}_2·\overline{{\mathrm{A}}_3}·+\overline{{\mathrm{A}}_1}]·\mathrm{P}\hfill \end{array}\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill {\mathrm{S}}_5& =\begin{array}{cc}\hfill & {\mathrm{A}}_4+{\mathrm{A}}_5\hfill \end{array}\hfill \end{array}$$

(18)

$$\begin{array}{cc}\hfill {\mathrm{S}}_6& =\begin{array}{cc}\hfill & ({\mathrm{A}}_3·\overline{{\mathrm{A}}_4}+{\mathrm{A}}_5)·\mathrm{P}+[({\mathrm{A}}_2·\overline{{\mathrm{A}}_3}·+\overline{{\mathrm{A}}_1}]·\overline{\mathrm{P}}\hfill \end{array}\hfill \end{array}$$

(19)

$$\begin{array}{cc}\hfill {\mathrm{S}}_7& =\begin{array}{cc}\hfill & {\mathrm{A}}_1·\overline{{\mathrm{A}}_2}+{\mathrm{A}}_2·\overline{{\mathrm{A}}_3}+{\mathrm{A}}_3·\overline{{\mathrm{A}}_4}+(\overline{{\mathrm{A}}_1}+{\mathrm{A}}_4+{\mathrm{A}}_5)·\mathrm{P}\hfill \end{array}\hfill \end{array}$$

(20)

$$\begin{array}{cc}\hfill {\mathrm{S}}_8& =\begin{array}{cc}\hfill & {\mathrm{A}}_2·\overline{{\mathrm{A}}_3}+{\mathrm{A}}_3·\overline{{\mathrm{A}}_4}+(\overline{{\mathrm{A}}_1}+\overline{{\mathrm{A}}_2}+{\mathrm{A}}_4+{\mathrm{A}}_5)·\overline{\mathrm{P}}\hfill \end{array}\hfill \end{array}$$

(21)

$$\begin{array}{cc}\hfill {\mathrm{S}}_9& =\begin{array}{cc}\hfill & (\overline{{\mathrm{A}}_1}+\overline{{\mathrm{A}}_2})·\mathrm{P}+[({\mathrm{A}}_2+{\mathrm{A}}_3+{\mathrm{A}}_4+{\mathrm{A}}_5]·\overline{\mathrm{P}}\hfill \end{array}\hfill \end{array}$$

(22)

Logic gate-based (LGB) switching pulse decoder is a function block which contains the switching pattern of all semiconductors. Boolean Equations (3)–(11) are programmed in this decoder block to generate the required voltage level.

3.1. Determination of Capacitance

Estimating capacitance is essential in capacitor-based inverters, especially switched capacitor-based MLIs, to maintain the ripples below acceptable bounds. The smaller voltage ripple content in the capacitor causes fewer losses, leading to more inverter efficiency [19]. The large discharge period, allowable ripples, and maximum current of the capacitors are considered while calculating the capacitance value. Figure 6 indicates the time durations (${\mathrm{t}}_1$, ${\mathrm{t}}_2$, ${\mathrm{t}}_3$, etc.) on every step change. Whereas a loading is entirely resistive, output current and voltage are in perfect harmony. At this resistive load (unity power factor (UPF)), the peak current at the middle of the integration leads to maximum discharge in the capacitor. This means that if designed for UPF, the capacitor retains fewer ripples for other loads. Considering UPF ($m_a$ = 1), the longest discharging period of boosting capacitor (${\mathrm{C}}_1$) in Figure 4 occurs between [${\mathrm{t}}_3$, ${\mathrm{t}}_8$], and [${\mathrm{t}}_1$−${\mathrm{t}}_2$, ${\mathrm{t}}_9$−${\mathrm{t}}_{10}$, ${\mathrm{t}}_{15}$−${\mathrm{t}}_{16}$] respectively. As the load waveform adheres to the property of symmetry, positive and negative cycles have equal periods. Accordingly, the time interval between [${\mathrm{t}}_9$, ${\mathrm{t}}_{10}$] is similar to [${\mathrm{t}}_1$, ${\mathrm{t}}_2$] and duration between [${\mathrm{t}}_7$, ${\mathrm{t}}_8$] is similar to [${\mathrm{t}}_3$, ${\mathrm{t}}_4$] because of quarter wave symmetry. Additionally, each capacitor’s maximum discharge is computed [17] using the following equations:

$$\begin{array}{c}\hfill \Delta Q_{C_n}=\underset{t_3}{\overset{t_8}{\int }}{I}_{load}sin\left(\omega t\right)dt\end{array}$$

(23)

where $I_{load}$ is peak current of the capacitor, and $\omega$ is the fundamental frequency in rad/s.

The time duration (${\mathrm{t}}_1-{\mathrm{t}}_{10}$) is estimated as

$$\begin{array}{cc}\hfill t_1& =\begin{array}{cc}\hfill & \frac{{sin}^{-1}(Ca{r}_5/V_{ref})}{2\pi f_{ref}}=2.8944\times {10}^{-4}\sec \hfill \end{array}\hfill \end{array}$$

(24)

$$\begin{array}{cc}\hfill t_2& =\begin{array}{cc}\hfill & \frac{{sin}^{-1}(Ca{r}_4/V_{ref})}{2\pi f_{ref}}=8.788\times {10}^{-4}\sec \hfill \end{array}\hfill \end{array}$$

(25)

$$\begin{array}{cc}\hfill t_3& =\begin{array}{cc}\hfill & \frac{{sin}^{-1}(Ca{r}_3/V_{ref})}{2\pi f_{ref}}=1.499\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(26)

$$\begin{array}{cc}\hfill t_4& =\begin{array}{cc}\hfill & \frac{{sin}^{-1}(Ca{r}_2/V_{ref})}{2\pi f_{ref}}=2.19\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(27)

$$\begin{array}{cc}\hfill t_5& =\begin{array}{cc}\hfill & \frac{{sin}^{-1}(Ca{r}_1/V_{ref})}{2\pi f_{ref}}=3.05\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(28)

$$\begin{array}{cc}\hfill t_6& =\begin{array}{cc}\hfill & \frac{\pi -{sin}^{-1}(Ca{r}_1/V_{ref})}{2\pi f_{ref}}=6.9494\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(29)

$$\begin{array}{cc}\hfill t_7& =\begin{array}{cc}\hfill & \frac{\pi -{sin}^{-1}(Ca{r}_2/V_{ref})}{2\pi f_{ref}}=7.804\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(30)

$$\begin{array}{cc}\hfill t_8& =\begin{array}{cc}\hfill & \frac{\pi -{sin}^{-1}(Ca{r}_3/V_{ref})}{2\pi f_{ref}}=8.5\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(31)

$$\begin{array}{cc}\hfill t_9& =\begin{array}{cc}\hfill & \frac{\pi -{sin}^{-1}(Ca{r}_4/V_{ref})}{2\pi f_{ref}}=9.1211\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(32)

$$\begin{array}{cc}\hfill t_{10}& =\begin{array}{cc}\hfill & \frac{\pi -{sin}^{-1}(Ca{r}_5/V_{ref})}{2\pi f_{ref}}=9.7105\times {10}^{-3}\sec \hfill \end{array}\hfill \end{array}$$

(33)

Therefore, the minimum value of capacitance required for capacitor voltage with allowable ripples proportion (x%) is given as:

$$C_n=\frac{\Delta Q_{C_n}}{x\%\times V_{C_n}}$$

(34)

The desired capacitance value for a 50 V supply at UPF (R-load (30 $\Omega$)) with 3% of allowable voltage ripple content is determined as

$$\begin{array}{cc}\hfill C_1& =\begin{array}{cc}\hfill & \frac{1}{x\%\times V_{C_B}}\underset{t_3}{\overset{t_6}{\int }}{I}_{o}sin\left(\omega t\right)dt\hfill \end{array}\hfill \end{array}$$

(35)

$$\begin{array}{cc}\hfill C_1& =\begin{array}{cc}\hfill & \frac{1}{0.03\times 25}\underset{1.499\times {10}^{-3}}{\overset{8.5\times {10}^{-3}}{\int }}3sin\left(2\pi ft\right)dt\hfill \end{array}\hfill \end{array}$$

(36)

$$\begin{array}{cc}\hfill C_1& =\begin{array}{cc}\hfill & 2.132\mathrm{mF}\hfill \end{array}\hfill \end{array}$$

(37)

Similarly, the capacitance values of the capacitors (${\mathrm{C}}_2$ and ${\mathrm{C}}_3$) are calculated, and those are almost equal to ${\mathrm{C}}_1$.

3.2. Power Loss Calculation

The suggested methodology in [20] is used to determine approximated output total power losses. There are two types of electrical power losses caused by semiconductor switches: 1. conduction loss $\left({\mathrm{P}}_{\mathrm{cd}}\right)$ and 2. switch loss $\left({\mathrm{P}}_{\mathrm{sw}}\right)$. The mathematical formula for switching loss ($\left({\mathrm{P}}_{\mathrm{sw}}\right)$) of the proposed structure is defined as:

$$P_{sw}=f\left[\sum _{i=1}^{10}\left(\sum _{k=1}^{N_{ON,i}}{E}_{ON,ik}+\sum _{k=1}^{N_{OFF,i}}{E}_{OFF,ik}\right)\right]$$

(38)

where ${\mathrm{E}}_{\mathrm{ON}}$ = Power loss during ON-state, and ${\mathrm{E}}_{\mathrm{OFF}}$ = Power loss during OFF-state.

The total energy loss during the ON-state of a switch is expressed as

$${\mathrm{E}}_{\mathrm{ON}}={\int }_0^{{\mathrm{t}}_{\mathrm{ON}}}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)$$

(39)

The total energy loss during the OFF-state of a switch is expressed as

$${\mathrm{E}}_{\mathrm{OFF}}={\int }_0^{{\mathrm{t}}_{\mathrm{OFF}}}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)$$

(40)

The conduction losses for an IGBT (${\mathrm{P}}_{\mathrm{c},\mathrm{t}}\left(\mathrm{t}\right)$) and a diode (${\mathrm{P}}_{\mathrm{c},\mathrm{d}}\left(\mathrm{t}\right)$) within the ON-state are calculated as follows:

$${\mathrm{P}}_{\mathrm{c},\mathrm{t}}\left(\mathrm{t}\right)={\mathrm{V}}_{\mathrm{s}}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)$$

(41)

$${\mathrm{P}}_{\mathrm{c},\mathrm{d}}\left(\mathrm{t}\right)={\mathrm{V}}_{\mathrm{d}}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)$$

(42)

The following equation represents the extensive conductive switching losses $\left({\mathrm{P}}_{\mathrm{c}}\right)$:

$${\mathrm{P}}_{\mathrm{c}}\left(\mathrm{t}\right)={\mathrm{P}}_{\mathrm{c},\mathrm{t}}\left(\mathrm{t}\right)+{\mathrm{P}}_{\mathrm{c},\mathrm{d}}\left(\mathrm{t}\right)$$

(43)

The overall conduction losses of the suggested capacitor-based CB-MLI circuit are the sum of ${\mathrm{P}}_{\mathrm{c}}$ for all semiconductor switches in a given operating state, which includes $N_d\left(t\right)$ diodes, and $N_i\left(t\right)$ IGBTs.

$$P_c=\frac{1}{\pi }{\int }_0^{\pi }\left(N_i\left(t\right)V_s\left(t\right)+N_d\left(t\right)V_d\left(t\right)\right)i\left(t\right)dt$$

(44)

Additionally, losses are caused by ripple current in the voltage waveform and the capacitor’s intrinsic resistance. While in the charging state, the change between the voltage across capacitors and the reference input supply will create voltage ripple losses. The amount of ripple content across each capacitor is determined as follows:

$$\begin{array}{c}\hfill \Delta V_{C_n}=\frac{1}{C_n}\underset{t}{\overset{t^{\prime }}{\int }}{i}_{C_n}\left(t\right)dt.\end{array}$$

(45)

The current (${\mathrm{i}}_{{\mathrm{C}}_{\mathrm{n}}}$) flows through the $rmnth$ capacitor during the time interval, which is obtained in the suggested circuit. As a result, the capacitor ripple loss (${\mathrm{P}}_{{\mathrm{C}}_{\mathrm{rpl}}}$) can always be defined by including capacitance, fundamental frequency, and ripple content in the voltage waveform as parameters

$$\begin{array}{cc}\hfill P_{C_{rpl}}& =\frac{f_{ref}}{2}\sum _{n=1}^2(C_n\times \Delta V_{C_n}^2)\hfill \end{array}$$

(46)

$$\begin{array}{cc}\hfill P_{C_{rpl}}& =\frac{f_{ref}}{2}(C_{LD}\times \Delta V_{C_{LD}}^2+C_B\times \Delta V_{C_B}^2)\hfill \end{array}$$

(47)

The proposed CB-MLI circuit total losses are mathematically expressed as follows:

$${\mathrm{P}}_{\mathrm{T}}={\mathrm{P}}_{\mathrm{sw}}+{\mathrm{P}}_{\mathrm{c}}+{\mathrm{P}}_{{\mathrm{C}}_{\mathrm{rpl}}}$$

(48)

Hence, the proposed capacitor-based CB-MLI efficiency is calculated as

$$\eta =\frac{P_{out}}{P_{in}}=\frac{P_{out}}{P_{out}+P_T}$$

(49)

4. Simulations

Simulations were performed in MATLAB/SIMULINK to validate the proposed switched capacitor-based CB-MLI structure and FF-PWM-based switching pattern. In this case, the amplitude modulation index ($m_a$) is 1. The configuration presented in this study has three boosting capacitors ($C_1$, $C_2$, and $C_3$) with 2.2 mF each value, and an isolated 100 V dc source is used. In the present case, they provide a 30 $\Omega$ R-load and a 30 $\Omega$-50 mH RL-load, assuming that the converter’s parts will be nearly ideal. In Section 4, it is stated that the FF-PWM approach is used to generate gate pulses to create an eleven-level output voltage.

The proposed CB-MLI configuration generates the eleven-level output voltage waveform, shown in Figure 7 at different load conditions. Additionally, the corresponding output currents waveforms are depicted in Figure 7. Both output voltage and output current are achieved using the FF-PWM switching technique. The proposed topology is tested for an R-Load of 30 $\Omega$; the corresponding results, i.e., output voltage, current, and capacitor voltages, are shown in Figure 7a. Similarly, Figure 7b shows the output results at RL-Load of 30 $\Omega$-50 mH. To test the proposed inverter at transient conditions, here, we consider the load variations as R to RL-Load and No-Load to RL-Load. The corresponding outcomes are shown in Figure 7c,d, respectively.

In Figure 7, the waveform of voltage across capacitors (${\mathrm{C}}_1$, ${\mathrm{C}}_2$, and ${\mathrm{C}}_3$) are also shown, and it is observed that the voltage ripples are maintained at low value. Additionally, the output voltage, current, and voltage across the capacitors variations at different modulation index values ($m_a$ = 0.2, $m_a$ = 0.4, $m_a$ = 0.6, $m_a$ = 0.8, and $m_a$ = 1) are presented in Figure 8, and noticed that at $m_a$ = 0.2, $m_a$ = 0.4, $m_a$ = 0.6, $m_a$ = 0.8, and $m_a$ = 1, the proposed CB-MLI provides three-, five-, seven-, nine-, eleven-level output voltage waveforms, respectively. The individual switch stress for proposed CB-MLI topology is illustrated in Figure 9. As shown in Figure 7b, the recommended CB-MLI circuit converts a 100 V dc input supply voltage into a eleven-level output voltage of 176.78 Vrms and gives a 8.33A peak current. The proposed circuit’s estimated output power is 922.82 W at RL-Load (30 $\Omega$-50 mH), while the total loss of suggested CB-MLI is estimated to be 20.56 W. Using the FF-PWM control switching method for recommended CB-MLI circuit, the efficiency is calculated as 97.82%.

5. Laboratory Results

After extensive investigation and testing, the suggested capacitor-based CB-MLI topology was verified to be practical. An insulated-gate bipolar transistor (IGBT) with an anti-parallel diode is employed for each of the switching devices $S_1$ to $S_9$. Each module is rated at 1200 V/75 A and has two IGBTs/diodes. In a hardware implementation, HGTG11N120CND IGBT modules, pulse drivers (TLP250), and capacitors(electrolytic) were used to provide gating signals for the power switches, and for controlling the gating pulses, a real-time simulator (OPAL-RT4200) was used as a controller. A schematic diagram for the computer interface and additional controlling devices are also shown in Figure 10. A reference modulating signal (sine) and four triangular carrier signals with the same features described in the earlier section are utilized for CB-MLI modulation. The constant carrier pulses are sent as a digital pulse from the computer to the controller OPAL-RT unit, which transmits the digital signals as output to the gate driving circuit through the optocoupler.

The hardware prototype components and requirements are listed in

Table 2. Prototype implementing parameters.

Elements	Units	Specifications
Input DC-source	V	50
output frequency	Hz	50
Capacitors ($C_1$ = $C_2$ = $C_3$)	mF	2.2
Load resistance	$\Omega$	30
Load inductance	mH	50

. The suggested CB-MLI’s load voltage and current are shown in Figure 11A,B. The self-balanced voltage across each capacitor waveform is depicted in Figure 12A,B with different load changes, i.e., R-load (30 $\Omega$) and RL-load (30 $\Omega$-50 mH). Furthermore, the dynamic load variations, which are no-load to full load corresponding voltage and current, are illustrated in Figure 11D. For the load variation of R-load (30 $\Omega$) to RL-load (30 $\Omega$-50 mH), the corresponding load voltage and current waveforms are shown in Figure 11C, the capacitor voltages are shown in Figure 12C. The suggested CB-MLI has three capacitors, and the corresponding capacitor voltage waveforms with a dynamic change of R-load (30 $\Omega$-50 mH) to 2RL-load (60 $\Omega$-50 mH) are shown in Figure 12D.

Additionally, the proposed capacitor-based CB-MLI FFT spectrum analysis of the derived output voltage and current are illustrated in Figure 13a,b. Consequently, the CB-MLI circuit can identify when $ma=1$, the harmonic components of odd-order suppressing a comprehensive change in a THDs of 9.12% and 1.52% for eleven levels. The capacitor-based CB-MLI circuit provides medium-range power applications due to various attributes, including decreased voltage stress on switches, reduced component count, and electromagnetic interference (EMI).

6. Comparitive Analysis

Any practical voltage balancing approach must be evaluated by looking at the methodology processing time, which can be expressed in CPU clock pulses. To organize another method, the simplest approach to assess a method’s speed is to consider the number of CPU pulses required by a processor, such as a DSP, dSPACE, OPAL-RT, or the FPGA, which is used in the prototype implementation. Lower CPU clock periods make the algorithms run more quickly. Here, the proposed capacitor-based CB-MLI circuit is implemented using the OPAL-RT controller, which is the more accurate and advanced controller to give gating pulses to drive the circuit.

Additionally, quantitative and cost assessments of recently existing isolated DC-voltage source MLIs are presented. There are several issues with MLIs, such as having both passive and active component quantities and the rating of the devices. For a collated study, the blocking voltage, required capacitors, and switching devices for capacitor-based MLIs are all assessed in

Table 3. Collation of recommended CB-MLI topology with currently evolved structures.

Topology	[21]	[22]	[23]	[24]	[25]	[26]	[27]	[28]	[29]	Proposed
	(2018)	(2021)	(2020)	(2021)	(2021)	(2018)	(2018)	(2022)	(2018)
${\mathrm{N}}_{\mathrm{L}}$	11	11	11	9	7	11	11	9	9	11
${\mathrm{N}}_{\mathrm{sw}}$	14	21	20	10	12	20	24	10	12	11
${\mathrm{N}}_{\mathrm{Cap}}$	4	6	4	2	4	5	4	2	4	3
${\mathrm{N}}_{\mathrm{diode}}$	2	2	-	1	-	-	-	-	4	-
${\mathrm{N}}_{\mathrm{dc}}$	1	1	1	1	1	1	1	1	2	1
PIVx${\mathrm{V}}_{\mathrm{dc}}$	2.5	2.5	4	2	1	4	1	1	16	1.5
TSV	26	21	20	14	10	33	24	7	26	12.5

N_L, N_sw, N_Cap, N_diode, N_dc—No. of—levels, power switches, capacitors, power diodes, DC sources, respectively.

. Table 3 shows that the recommended CB-MLI circuit has the smallest part count. Existing structures required more semiconductor switching devices, diodes, and capacitors than the proposed design, and in the suggested configuration, no diodes are necessary. Since capacitors in the circuit are the most sensitive part of an inverter, their quantity should be reduced to a minimum. The number of capacitors is thus among the most widely used MLI measures of competent quality. In the suggested structure, merely three capacitors are required (throughout all inverter circuits, this circuit is the least expensive). Therefore, the recommended design is more compact and cheaper. Additionally, it must evaluate the H-bridge stress and blocking voltage of an inverter circuit since they represent the price of an inverter and the requirement for a heat sink. The proposed design shows that it has a lower TSV value when compared to existing architectures, and there is no H-bridge stress. Hence, the recommended capacitor-based CB-MLI structure has less components and reduced blocking voltage, and is cheaper than the MLIs mentioned in Table 3, making it best suited for a wider range of applications.

Finally, an economic benefit comparison is conducted to verify the recommended financial gains of the multilevel inverter.

Table 4. Cost estimation of the proposed CB-MLI circuit with recently developed capacitor-based topologies.

Component	Series	Rating	Unit Price	Topology
			($)	[25]	[26]	[27]	[28]	[29]	[22]	[23]	[24]	P
MOSFET	IRFP350PBF	400 V	2.98	-	-	4	-	-	-	-	-	-
	IRFP240PBF	200 V	2.31	-	9	-	4	4	-	-	-	-
	IRFP9140NPBF	100 V	1.89	-	8	15	6	8	2	2	4	2
	IRFZ20PBF	50 V	1.63	8	-	-	-	-	4	6	6	9
	IRF1404	25 V	1.16	4	-	-	-	-	5	8	-	-
Gate driver	IR2110SPBF	-	1.92	12	14	19	10	12	11	16	10	11
Capacitor	B41231A9128M	2.2 mF	1.51	4	4	3	2	4	4	3	2	3
Diode	SDT10A100P5	100 V	0.61	-	4	3	0	4	2	-	1	-
Total price ($)				47.84	71.27	83.11	45.22	55.88	44.48	58	45.5	44.1

Courtesy: www.element14.com, mouser.in, digikey.com.

displays the costs of the investigated configurations, and an illustration situation of 250 W (100 V, 5 A peak) is assessed. The expense of the device’s standardized rating is considered. It is challenging to compare the capacitance of the capacitor in capacitor-based configurations because it is impacted by frequency, load, and ripple percentage. Consequently, the comparative study is founded on similar capacitance values but with different voltage amplitudes. According to Table 4, the recommended capacitor-based CB-MLI structure is indeed less expensive when collated with earlier configurations. In conclusion, the proposed design is economical and is executed impressively while collating with existing converter topologies.

7. Conclusions

A novel capacitor-based boost MLI circuit with fewer semiconductor switching devices and gate signals is developed. The maximum blocking voltage value of the individual switch lies within the limits of 1.5${\mathrm{V}}_{\mathrm{dc}}$. Moreover, the boost capacitors are equally charged and discharged in the positive and negative half of the cycle, resulting in the smallest amount of capacitance needed. As the devised PWM technique contains only logic gates and does not need any sensing devices to control the boosting capacitors, the proposed CB-MLI configuration is significantly cost-effective. In addition, an explanation of the proposed CB-MLI topology, operating states, FF-PWM scheme, and the capacitor designs are provided. Both the hardware and simulator findings achieved here have validated the principle of operation and assessed the proposed structure’s ability to withstand various load conditions. Furthermore, a comprehensive commensurate study indicates the suggested CB-MLI circuit benefits compared to quondam study results, proving its suitability for a wide range of applications, especially in electric vehicles.