High-Performance N-Polar GaN/AlGaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors with Low Surface Roughness Enabled by Chemical–Mechanical-Polishing-Incorporated Layer Transfer Technology

Abstract

This article presents the utilization of the chemical–mechanical polishing (CMP) method to fabricate high-performance N-polar GaN/AlGaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) through layer transfer technology. The nucleation and buffer layers were removed via CMP to attain a pristine N-polar GaN surface with elevated smoothness, featuring a low root-mean-square (RMS) roughness of 0.216 nm. Oxygen, carbon, and chlorine impurity elements content were low after the CMP process, as detected via X-ray photoelectron spectroscopy (XPS). The electrical properties of N-polar HEMTs fabricated via CMP exhibited a sheet resistance (R_sh) of 244.7 Ω/sq, a mobility of 1230 cm²/V·s, and an n_s of 2.24 × 10¹³ cm⁻². Compared with a counter device fabricated via inductively coupled plasma (ICP) dry etching, the CMP devices showed an improved output current of 756.1 mA/mm, reduced on-resistance of 6.51 Ω·mm, and a significantly reduced subthreshold slope mainly attributed to the improved surface conditions. Meanwhile, owing to the MIS configuration, the reverse gate leakage current could be reduced to as low as 15 μA/mm. These results highlight the feasibility of the CMP-involved epitaxial layer transfer (ELT) technique to deliver superior N-polar GaN MIS-HEMTs for power electronic applications.

1. Introduction

Gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs) exhibit notable device characteristics such as high current density, low on-resistance, and large breakdown voltages, etc. [1,2,3]. Currently, GaN HEMTs are mostly based on Ga-polar epilayers along the c-axis. As a counterpart, the N-polar GaN-based HEMT is recently emerging and shows immense potential to further enhance device performance [4,5]. Such devices are normally based on the N-polar GaN/AlGaN heterojunction, where the GaN channel layer on the surface has a narrower bandgap and lower electron barrier, as well as AlGaN as an inherent back barrier. As a result, N-polar GaN HEMTs exhibit enhanced electron confinement, mobility, and reduced ohmic resistance [6,7], showing distinct advantages in power and high-frequency applications [8].

To prepare high-quality N-polar GaN epilayers, epitaxial growth via metal–organic chemical vapor deposition (MOCVD) methods has been intensively investigated. However, there still exist severe challenges in front of this technique. For example, the constrained atomic surface mobility of MO sources during the growth of N-polar GaN can result in pyramidal hexagonal surface morphology [9,10]. Additionally, the polarization field during epitaxial growth significantly affects the incorporation of oxygen and carbon impurities into GaN epilayers [11,12], degrading the crystal quality and electrical characteristics of the device. Overall speaking, the optimizations of the growth technique and epilayer quliaties of N-polar GaN are still complicated and difficult.

Alternatively, the N-polar GaN can be directly obtained by turning the Ga-polar GaN epi-structures upside-down via the epitaixial layer transfer (ELT) method [13,14]. With the advancements of Ga-polar GaN epitaxy technology, high-quality Ga-polar GaN epilayers can be grown on a Si (111) substrate at first, and then the whole structure can be bonded to the Si (100) substrate. Thereafter, the Si (111) substrate and buffer layer are removed to expose the N-polar GaN surface. Palacios et al. reported a layer removal and exposure process based on selective dry etching to precisely control the GaN channel thickness to 100 nm. Based on this method, an N-polar HEMT with the maximum drain current (I_D) of ~600 mA/mm was realized [13]. Our group also reported a high-selectivity etching process of N-polar AlGaN to GaN using chemical–material polishing (CMP), delivering a N-polar GaN surface with a roughness as low as 0.307 nm, and photoluminescence spectroscopy results indicated reduced deep level states in the CMP-fabricated sample, probably owing to the absent of ion bombardment [15], providing an approach to preparing N-polar GaN structrues through the ELT method.

Herein, we further implemented this CMP-involved ELT technique to fabricate an N-polar GaN/AlGaN-based HEMT from Ga-polar device structures. To highlight the advantages of the low-damage CMP process in the fabrication of N-polar HEMTs, a counter device whose GaN channel was exposed by an ICP dry etching process was perpared. Less impurity element content, like Cl, C, and O in the CMP sample than the ICP sample, were detected via XPS spectrum; then, both samples were fabricated into a metal–insulator–semiconductor (MIS) HEMT configuration, with the Si₃N₄ as the dielectric layers. It was found that the CMP MIS-HEMT exhibited overall boosted device performance, featuring higher maximum drain current, lower on-resistance, reduced subthreshold slope, decreased gate leakage current, and gate breakdown votlage, owing to improved N-polar GaN surface conditions and optimized gate dielectrics. These results verify the feasibility of the CMP-involved ELT to deliver high-performance N-polar MIS HEMTs for power electronic applications.

2. Experimental Methods

Figure 1 exhibits the main process flow of the proposed CMP-involved ELT technology for N-polar HEMT fabrication. The N-polar GaN structure was manufactured through the ELT method based on a high-quality Ga-polar AlGaN/GaN structure, which was epitaxially grown on a 6-inch Si (111) substrate using MOCVD. The Ga-polar device structure comprises a 23 nm Al_0.23Ga_0.77N barrier, a 300 nm GaN channel, a 1.5 µm GaN buffer, a 3.3 µm AlGaN buffer, and a 200 nm AlN nucleation layer, as shown in Figure 1a. The as-grown wafer exhibits a sheet resistance (R_sh) of 420.8 Ω/sq, a carrier density (n_s) of 1.05 × 10¹³/cm², and an electron mobility (µ_e) of 1420 cm²/V·s.

To be specific, the fabrication of the device commenced with the deposition of an Si₃N₄ diffusion buffer layer onto both the 6-inch Ga-polar AlGaN/GaN structure and the Si (100) substrate (Figure 1b), using low-pressure chemical vapor deposition (LPCVD). A Ti/Cu/Au (50 nm/800 nm/20 nm) stack was subsequently deposited onto both wafers by magnetron sputtering. Thereafter, Au–Au thermo-compressive wafer bonding was employed to bond the Ga-polar GaN wafer onto the Si (100) substrate (Figure 1c). Figure 1d shows the wafer bonding procedure for the Au–Au thermo-compressive wafer bonding of the Ga-polar GaN epiwafer onto the Si(100) carrier wafer. Following the removal of the Si (111) substrate by mechanical lapping and SF₆-based dry etching, the N-polar AlN nucleation and Al_xGa_1−xN barrier were removed by CMP, as illustrated in Figure 1e,f. The specifics are covered in the following text. The schematic and process flow in Figure 2a depict the main manufacturing process of the N-Polar HEMT device, comprising dielectric deposition, F ion implantation for device isolation, ohmic contact fabrication, and gate fabrication, which will be discussed later. Figure 2b shows the FIB-SEM image of the fabricated N-polar HEMT; a clear Si₃N₄/metal bonding interlayer beneath the GaN/AlGaN heterojunction can be observed. Figure 2c demonstrates the successful bonding of the 6-inch epitaxial wafers with minor defects generated by particles affecting the subsequent substrate thinning process. After the wafer bonding, the original Si (111) substrate of the HEMT structure was thoroughly removed using mechanical lapping and SF₆ plasma dry etching (Figure 1d). The wafer was then cut into 1.2 cm × 1.3 cm pieces and cleaned with an organic solvent.

After removal of the Si substrate, the exposed N-polar AlN nucleation layer was characterized using an atomic force microscope (AFM), showing a root-mean-square (RMS) surface roughness of 0.569 nm, as shown in Figure 3a. To expose the N-polar GaN surface, the AlN nucleation layer and AlGaN buffer layer needed to be removed via the CMP process conducted on a Single-Side Lapping Machine (AP-380, AM Technology Co., Ltd.). SiO₂-KOH-based slurry with a pH of 9.7 was used to assist mechanical stress in polishing wafer surfaces. The stronger surface activity of N-polar GaN, due to its smaller Ga-N bond angle compared to Ga-polar GaN, renders it susceptible to an OH-ion attack [16]. The CMP process was divided into different steps, carried out continuously with varying carrier speeds to remove the AlN nucleation layer and Al_xGa_1−xN and GaN buffer layer due to the average etching rate of 600/400/50 nm/min in the weak alkaline solution.

The FIB-SEM results showed that the GaN channel thickness of the CMP sample was controlled to be 100 nm. A smooth N-polar GaN surface with a roughness as low as 0.216 nm was achieved, thanks to combined physical polishing with the chemical etching of CMP. As a comparison, another sample fabricated by ICP etching with Cl₂/BCl₃-based gas obtained an average etch rate of 320 nm/min was prepared in the meantime with a 100 nm thick N-polar GaN channel, referred to as the ICP sample. Due to the physical ion bombardment during dry etching [17], the GaN surface featured an increased roughness of 1.75 nm, as depicted in Figure 3c.

To assess the electrical properties of N-polar samples, MIS-HEMTs devices were fabricated on the CMP and ICP samples. Initially, a 20 nm PECVD-Si₃N₄ gate dielectric was deposited, and then the active regions of the devices were defined by F ion implantation, annealing for 5 min at 450 °C in an N₂ ambient. After the Si₃N₄ window was opened for ohmic contact, the GaN channel was slightly etched down with Cl-based etching, and e-beam evaporation was used to form non-alloy ohmic contacts consisting of Ti/Au (25/200 nm); the Ni/Au (50/150 nm) stack was then evaporated as a gate metal. The MIS-HEMT featured a gate length of 3 µm, a gate-to-drain distance (L_GD) of 15 µm, a gate-to-source distance (L_GS) of 2.7 µm, and a width of 100 µm.

3. Results and Discussion

Different treatment methods for removing nucleation and buffer layers induced various impurity elements on the surface, and XPS was employed to investigate any stoichiometry modification on the N-polar GaN surface. With Gaussian fitting, the Ga 3d peak can be generally deconvoluted into two peaks contributing to Ga in GaN (Ga-(GaN) and Ga-(Ga₂O₃)), as shown in Figure 4a. Figure 4b,c shows the XPS energy spectrum of Cl 2p and O 1s core levels for CMP and ICP samples. As counted in

Table 1. Surface elemental composition of the ICP and CMP samples extracted via XPS.

Sample	Surface Elemental Composition (at. %)
	Ga	N	O	C	Cl
ICP	36.46	42.92	4.51	15.6	0.51
CMP	39.72	50.92	1.27	8.09	-

, a significant Ga deficiency was evident after ICP treatment compared to the CMP sample, and the ICP sample had higher oxygen content (4.51%) and carbon content (15.6%) than those (1.27% and 8.09%) of the CMP sample, along with chlorine content (0.51%) on its surface. Byproducts like Al(Ga)Cl_x cannot be easily removed from the N-polar surface during ICP etching [18]. The presence of ion bombardment appears to degrade the electrical characteristics through ion-related chemical changes [19]. It should be noted that the results of XPS was element distribution at 1~2 nm beneath the GaN surface. However, this can be strong evidence to characterize the surface conditions of the N-polar GaN channel, considering its large thickness of 100 nm.

The electrical properties of the as-obtained N-polar HEMT after CMP are determined from Hall effect measurements using Van der Pauw structures, showing a sheet resistance (R_sh) of 244.7 Ω/sq, a mobility of 1230 cm²/V·s, and an n_s of 2.24 × 10¹³ cm⁻². After device fabrication, the CMP/ICP samples showed non-alloy contact resistances of 0.6/0.9 Ω mm, the R_sh of 192.1/184.7 Ω/sq, and the specific contact resistivity (ρ_c) of 2.14 × 10⁻⁵/4.86 × 10⁻⁵ Ω·cm², as concluded in Figure 5a.

Figure 5b shows the output characteristics of the N-polar MIS-HEMTs fabricated via both CMP and ICP methods. The maximum current in the CMP sample is 756.1 mA/mm at V_GS = 4 V, ~11% higher than that of the ICP sample (677.9 mA/mm). The on-resistance (R_ON) values of CMP and ICP sample are 6.51 Ω·mm and 8.87 Ω·mm, respectively. The improved output characteristics of the CMP sample are mainly due to the reduced deep-level states defects induced by energetic ion bombardment [15]. Notably, it was found that the output curves shown in Figure 5b show negligible self-heating effects, i.e., current drop at the operating conditions of high I_DS = 756.1 mA/mm and high V_DS = 15 V. The improved thermal dissipation abilities of our device can be attributed to the layers having the worst thermal conductivity, i.e., high-Al-content AlGaN buffers having been totally removed by the CMP/ICP etching process [20]. The remaining structures, i.e., GaN/AlGaN heterojunction, have relatively good thermal conductivity and stability. Figure 6a,b shows the capacitance–voltage (C-V) test structure and measurements of the CMP and ICP samples at 1 MHz. The total 2DEG sheet density, n_s, can be obtained with the folowing formula [21]:

$$N_{CV}=-\frac{2}{q\epsilon A^2}\times \frac{\mathrm{d}V}{\mathrm{d}{C}^{-2}}$$

(1)

$$x=\frac{\epsilon A}{C}$$

(2)

$$A=\pi R^2$$

(3)

$$n_s={\int }_{-\mathrm{\infty }}^{+\mathrm{\infty }}{N}_{CV}\left(x\right)\mathrm{d}x$$

(4)

where $N_{CV}$ is the concentration of electrons, $q$ is the elementary charge, $\epsilon$ is the dielectric constant of the barrier layer, $A$ is the Schottky junction area, $C$ is the barrier capacitance under the anode bias V of Schottky barrier diode, $x$ is the distance of the electrons from the GaN surface, and R is the radius of the anode. The results show that the total 2DEG sheet density of the CMP and ICP samples are 1.29 × 10¹³ cm⁻² and 8.94 × 10¹² cm⁻² using Equations (1)–(4), which is the main reason for the higher maximum current of the CMP sample. A steeper rising slope at the first step shows better mutation and electron confinement in the CMP sample, and the slope at the second step is also observed to be steeper in the CMP sample, indicating that the Si₃N₄/GaN interface has a lower interface state density [22].

Figure 7a,b compares the transfer characteristics of the device on the CMP and ICP samples. Specifically, at V_DS = 5 V and the same pinch-off voltage of −18 V, the CMP sample exhibited a transconductance of 61.1 mS/mm, surpassing that of the ICP sample (57.9 mS/mm). The CMP sample demonstrated an I_ON/I_OFF ratio of 7.8 × 10⁴, with a subthreshold slope (SS) of 155 mV/dec, while the ICP sample exhibited an I_ON/I_OFF ratio of 5.3 × 10⁴, with a SS of 233 mV/dec. This largely reduced SS value of the CMP sample further confirms the improved surface conditions of the N-polar GaN surface prepared via CMP methods [20].

Due to the Si₃N₄ gate dielectric, the gate leakage in both N-polar MIS-HEMTs was ~0.015 mA/mm at the pinch-off voltage, much lower than that in the previously reported Schottky N-polar HEMT (2–3 mA/mm) [14]. Further reduction in leakage could be achieved by optimizing the gate leakage through LPCVD growth of the Si₃N₄ gate dielectric [23]. In addition, the CMP sample in Figure 7c shows a large gate breakdown voltage of 23 V, corresponding to an ultra-high gate swing of ~40 V. In comparison, the gate breakdown of the ICP sample was premature at 18 V, mainly due to the inferior surface conditions caused by dry etching. These results verify the compatibility between the N-polar GaN surface obtained from CMP-incorporated layer transfering technology and PECVD Si₃N₄ for high-performance N-polar GaN HEMT application. It should be noted that the AlGaN back barrier employed in this work is based on a well-developed Ga-polar GaN-on-Si epitaxial structure. It is of great interest and significance to further investigate the influences of Al% of the AlGaN back barrier on the electrical characteristics of N-polar GaN MIS-HEMTs to further propel the development of such device technologies towards high-efficiency power electronic devices.

4. Conclusions

A method to obtain an N-polar GaN surface via CMP-involved ELT achieving low surface roughness (RMS = 0.216 nm) and low-induced impurity-like elements like Cl, C, and O has ben presented in this article. The electronic properties show a sheet resistance (R_sh) of 244.7 Ω/sq, a mobility of 1230 cm²/V·s, and an n_s of 2.24 × 10¹³ cm⁻². Compared to the ICP approach, CMP can avoid damage from ion bombardment and provide improved surface conditions, resulting in a better performance of the fabricated N-polar GaN/AlGaN MIS-HEMTs, with 756.1 mA/mm maximum current, 0.015 mA/mm (@V_GS = −30 V) gate leakage, and reduced subthreshold slope. This approach highlights the feasibility of CMP-involved ELT and offers a viable route of fabricating high-performance N-polar devices.