In-Memory Caching for Enhancing Subgraph Accessibility

Round 1

Reviewer 1 Report

In this paper, authors use subgraph structure to study the in-memory caching accessibility. It can help reduce sources for input and output. They proposed "first-in subgraphs are targeted for replacement as a priority." Also, performance evaluation is provided.

1. Authors should provide additional motivations.
2. Explain details on related work.
3. Explain Figure 4.
4. Explain Figure 5 and Table 1.
5. Refs should be in alphabetical order.

This paper is in a nice topic, and it has a good realization. The results on performance evaluation is good. But it needs some updates. So I give it as a minor revision.

 

Author Response

We would like to sincerely thank you for your attentive indications and good comments. Our paper is partially rewritten in order to revise and complement your comments. Please refer to the attached file about the detailed revisions.

Author Response File: Author Response.docx

Reviewer 2 Report

Minor issues:

• Authors should introduce TTL in the same way they introduce other acronyms;
• Line 160 should begin as follows: "Frequently used subgraphs...".

In line 161, authors use the word "likely". Please elaborate what this means in terms of datasets that were used for the evaluation.

In line 166, "of queries" is redundant.

Table in Figure 4(a) is not well elaborated. What is QID and Edge Information? Please consider revising your table.

Equation (1) is not elaborated at all. Why this equation is used? What is the rationale behind this equation? Did you consider other models for TTL?

What is the \alpha parameter? What are the ranges for it? Please give detailed discussion about the impact of this parameter on the overall TTL and why you choose this model.

In line 215, authors mention "data characteristics". What are they and how they impact this "likelihood" paradigm.

In line 218, authors say they cache neighbouring vertices. Why not caching whole neighbouring subgraph? What would be the impact of that approach?

In figure 7, authors should rename ttl_{low} to something more consistent. 

In line 306, authors state percentages but they are not referring to where these percentages are to be observed. I guess figure 13? Should be stated.

Why the approach is slower for smaller caches? Please give detailed discussion.

Author Response

We would like to sincerely thank you for your attentive indications and good comments. Our paper is partially rewritten in order to revise and complement your comments. Please refer to the attached file about the detailed revisions.

Author Response File: Author Response.docx

Reviewer 3 Report

The article is written in an interesting way and the solution presented is supported by the experimental results that show its great potential. However, minor adjustments should be made - the details are listed below:

1. In the abstract, too much attention was devoted to the descriptions of the methods used at the expense of not referring to the results obtained and their importance for the development of science.
2. The paper does not mention any practical applications of the presented methods, all studies were conducted on benchmark datasets.
3. Not too many technical and implementation details of the cache memory mechanism were given.
4. The alpha parameter appears repeatedly in the experimental results section, but it is not formally defined anywhere, nor its meaning is explicitly given, although it is an independent variable in the study presented in Figure 12.
5. Algorithmic descriptions have not been presented in a legible way - there is no description of input and output parameters, as well as explicit declaration of variables.
6. Acronyms used repeatedly in the text (e.g. TTL) have not been developed.
7. Chapter 2 is relatively short - merging it with the introduction may be considered.
8. Figure 2: the block diagram is non-deterministic - after reading the graph data from the disk, is the transition made to "Check UC" or "Check PC", or maybe to both of them at once? The block diagram should reflect an algorithm in which each step is defined strictly.
9. Graphs are often represented in the form of matrices - is the use of some methods and techniques, including parallel processing on the GPU, presented in the publication: https://link.springer.com/article/10.1007/s10766-017-0515-0 possible in authors' opinion to adapt in their research?

Author Response

We would like to sincerely thank you for your attentive indications and good comments. Our paper is partially rewritten in order to revise and complement your comments. Please refer to the attached file about the detailed revisions.

Author Response File: Author Response.docx