The switching process of the MOSFET will be studied stage by stage in this section. A double-pulse test circuit is adopted for the modeling of MOSFET switching transients, as shown in
Figure 3. The input is a constant voltage source
VDD and the load is a clamped-inductive load which can provide a constant current
IDD. The gate signal
Vpulse is assumed to flip between
VSS and
VGG with zero rise time and fall time in the analysis. In order to investigate the switching process better, two different external gate resistances
Rg_on and
Rg_off are used in the turn-on transients and turn-off transients, respectively. Similar to the MOSFET, the freewheeling diode is modeled by two parasitic inductances
Lc_1 and
La_1 and a parasitic resistance
Rf in series with an ideal diode
Df, and then in parallel with a nonlinear junction capacitance Cf. In addition to these power devices, there also are a lot of stray inductances result from the PCB traces of the power loop, which are represented by
Lbus1,
Lbus2,
Lc_2,
La_2,
Ld_2,
Lg_2 and
Ls_2. In order to simplify the model and the equations, some parameters are merged in the equivalent circuit.
Ld1 =
Ld_ext +
Ld_int,
Lg1 =
Lg_ext +
Lg_int and
Ls1 =
Ls_ext +
Ls_int are denoted as the total parasitic inductances at each terminal of the MOSFET, respectively. It should be noted that the stray inductance of the ground lead of a measuring loop is hard to quantitatively analyze and its influence on the loss assessment can be ignored. Therefore, it was not considered in this model.
3.1. Turn-On Switching Transients
Stage 1 [t0–t1] turn-on delay time: Before the gate source voltage
vgs reaches the threshold voltage
Vth, the SiC MOSFET power device is still in the cut-off region. At this stage, the value of the drain current id is assumed to be zero. According to
Figure 4a and Kirchhoff’s law, the following equations are obtained:
where
RGG =
Rg_on +
Rg_int,
Lg =
Lg1 +
Lg2.
There are three independent state variables: the drain current
ig, the gate-source voltage
vgs and the drain-source voltage
vds. The state equations derived from above equations are shown in
Appendix A Equation (A1). As the power device is not activated, there is no switching loss
Psw during this period.
Stage 2 [t1–t2] current rise time: When the gate source voltage
vgs goes beyond the threshold voltage
Vth, the conductive pass (channel) enabling the current flow begins to form. Due to the fast speed of the SiC MOSFET power device, the drain current
id surges, which generates the induced voltage across the parasitic inductances. This induced voltage deservers special attention, as it determines whether the drain current (id) will rise to its full value
IDD before or after the drain-source voltage
vds drops to
vgs −
Vth (the boundary condition between the saturation region and the ohmic region of MOSFET). If the power device works in the saturation region, the channel of the SiC MOSFET can be equivalent to a voltage-controlled current source (the relationship between the channel current
ich and gate-source voltage
vgs is governed by (6)), otherwise it can be equivalent to a nonlinear resistance which is related to the junction temperature
Tj and the drain current
id. Both of them are discussed as follows.
where
gf is trans-conductance of the SiC MOSFET, which is also nonlinear.
Case I: The MOSFET works in the saturation region. In this situation, as shown in
Figure 4b, the drain current
id consists of three parts: the channel current
ich and the current flowing through the junction capacitor
Cgd and
Cds. The circuit equations can be expressed as:
where
Lp =
Lbus1 +
Lbus2 +
Lc +
La +
Ld +
Ls,
Lc =
Lc1 +
Lc2,
La =
La1 +
La2,
Ld =
Ld1 +
Ld2,
Ls =
Ls1 +
Ls2.
Case II: The MOSFET works in ohmic region directly. As discussed above, the channel of MOSFET can be represented by a nonlinear resistance in this scenario. Therefore, (10) is changed to (12), and the rest remains unchanged.
A new independent state variable
id appears in this stage compared to the previous one, and the state equations derived from the above equations are shown in
Appendix A Equation (A3). This stage ends when the drain current id reaches the bus current
IDD. The switching loss
Esw expression in this period is as follows.
However, a more appropriate switching loss analysis is to replace (13) with (14), taking into account the assumption that the junction capacitances of MOSFET are only lossless energy buffers. The discrepancy between the two types of calculation methods will be further elucidated in
Section 5 with the experimental verification.
Stage 3 [t2–t3] voltage falling time I: As the current is transferred to the SiC MOSFET, the SiC Schottky Diode (SBD) becomes capable of blocking the voltage;
Figure 4c shows the equivalent circuit of this stage, and the drain-source voltage
vds drops dramatically at the same time, if the
case I occurs in the previous stage. The gate-source voltage
vgs is maintained at the Miller Plateau, because the gate current
ig is completely absorbed by the drain-source capacitance
Cds without flowing to the gate-source capacitance
Cgs. Although SBD features zero reverse recovery current, the drain current id continues to increase since the charging current of junction capacitance
Cf of the SiC SBD. Therefore, (11) is replaced by (15), and the rest remains unchanged. A resonant period begins in this moment, which induced by the oscillations between
Lp and C
f. This stage ends when drain-source voltage
vds decreases to
vgs −
Vth.
There are five independent state variables: the drain current
ig, the drain current
id, the gate-source voltage
vgs, the drain-source voltage
vds and the free freewheeling diode voltage
vf. The state equations at this stage are shown in
Appendix A Equation (A4).
During this period, the two type of switching loss calculation as following:
Stage 4 [t3–t4] voltage falling time II: When the drain-source voltage
vds decreases to
vgs −
Vth, the SiC MOSFET will come out of the saturation region and get into the ohmic region. As shown in
Figure 4d, the channel is equivalent to a nonlinear resistance (also called on-state resistance) in this stage. Therefore, (10) is replaced by (18). The gate-source voltage
vgs breaks out of the Miller Plateau and begins to increase again. The drain-source voltage
vds drops slightly in this period, and the drain current id drops back to
IDD simultaneously. The oscillations in the power loop will be damped by the stray resistance resulting from the PCB traces. In order to specify this point, a lumped resistance
Rstray is added in the equivalent circuit, as same as the stray inductances, to compensate for the active power consumption and (9) should be replaced by (19). Once the drain-source voltage
vds decreases to
id·
Ron, this stage ends and the channel can be seen as completely conductive.
The independent state variables at this stage remain unchanged and the state equations are shown in
Appendix A Equation (A5). The switching loss in this period can be calculated as:
Stage 5 [t4–t5] On-State Operation: The gate current
ig still continues to charge the gate-source capacitance
Cgs until the gate-source voltage
vgs reaches the positive drive voltage
VGG. The state equations and the equivalent circuit are the same as the previous stage, while the loss at this stage is considered as conduction loss
Econd and can be calculated as:
3.2. Turn-Off Switching Transients
It is known that the turn-off switching transients are a reversely symmetrical process of the turn-on switching transients, in which the channel can also be equivalent to a nonlinear resistance, voltage-controlled current source, or an open circuit. Therefore, some repeated equations are omitted in the derivation of the stage equations for the turn-off switching transients.
Stage 6 [t6–t7] Turn-Off Delay Time: Before the gate source voltage
vgs reduces to the Miller Voltage
Vmiller, which is governed by (23), the SiC MOSFET power device operates in the ohmic region. It is assumed that the drain current
id remains unchanged (
id =
IDD) at this stage. As shown in
Figure 5a, the gate-source capacitance and the gate-drain capacitance are being discharged through
Rg and
Ls. The circuit equations are shown from (24) to (26):
where
RSS =
Rg_off +
Rg_int.
As with the stage 1, there are three independent state variables: the drain current
ig, the gate-source voltage
vgs and the drain-source voltage
vds, and the state equations derived from the above equations are shown in
Appendix A Equation (A6). Since the device is still activated, the loss during this period is conduction loss
Econd, which can be calculated as:
Stage 7 [t7–t8] Voltage Rising Time I: During this stage, the power device still works in the ohmic region until the drain-source voltage
vds reaches
vgs −
Vth. Therefore, the drain current
id stays constant at
IDD and the gate-source voltage
vgs (almost) remains at the Miller voltage. The equivalent circuit and equations during this period are the same as the previous one, while the loss during this period is regarded as the switching loss
Esw and can be calculated as:
Stage 8 [t8–t9] Voltage Rising Time II: When the drain-source voltage
vds reaches
vgs −
Vth, the device begins to operate in saturation region. Therefore, the channel is equivalent to a voltage-controlled current source, as shown in
Figure 5b. The drain-source voltage
vds continues to increase until the forward voltage
vf of the SBD decreases to the forward voltage −
Vf. The voltage slew rate will be faster than in the previous stage, since the value of junction capacitance significantly decreases with the increase in drain-source voltage
vds. A part of
IDD will be flowing through the freewheeling diode to discharge the
Cf, which will be causing the drain current id drop. During this period, the channel current
ich is also governed by (6). Hence the drain current id expression is changed to (10) and the rest of the circuit equations are the same as the stage 4 and the state equations are shown in
Appendix A Equation (A8). During this period, the switching loss
Esw is given by (30) and (31).
Stage 9 [t9–t10] Current Falling Time: When the freewheeling diode ceases to block the voltage, the current begins to divert from the MOSFET to the freewheeling diode rapidly, which will induce a voltage drop across the parasitic inductances and simultaneously incur a voltage overshoot on the drain-source voltage
vds. Compare to the previous stage, the expression of the freewheeling diode voltage is replaced by (11) and the rest of circuit equations remain unchanged. This stage ends when the gate-source voltage
vgs decreases to
Vth. The equivalent circuit is shown in
Figure 5c.
Stage 10 [t10–t11] Off-State Operation: After the gate-source voltage
vgs decreases to
Vth, the device works in the cut-off region. For a similar reason, a lumped resistance is added in the circuit (shown in
Figure 5d). This stage ends, when the gate-source voltage
vgs decreases to the negative drive voltage
VSS. The state equations are shown in
Appendix A Equation (A9) Since the channel is inactive, there is no power loss during this period. As discussed above, the power loss during the switching transient can be categorized and summarized as (34) to (37).