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Volume 11
Issue 21
10.3390/app112110183
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Article

FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC

by
Miroslaw Chmiel
1,
Robert Czerwinski
1,* and
Andrzej Malcher
2
1
Department of Digital Systems, Silesian University of Technology, Adademicka Str. 16, 44-100 Gliwice, Poland
2
Department of Electronics, Electrical Engineering and Microelectronics, Silesian University of Technology, Adademicka Str. 16, 44-100 Gliwice, Poland
*
Author to whom correspondence should be addressed.
Appl. Sci. 2021, 11(21), 10183; https://doi.org/10.3390/app112110183
Submission received: 22 September 2021 / Revised: 25 October 2021 / Accepted: 26 October 2021 / Published: 30 October 2021
(This article belongs to the Special Issue Programmable Logic Controllers)
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Abstract

The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.
Keywords: programmable logic controllers (PLC); counters; IEC 61131-3; field programmable gate arrays (FPGA); function blocks; central processing units (CPU) programmable logic controllers (PLC); counters; IEC 61131-3; field programmable gate arrays (FPGA); function blocks; central processing units (CPU)

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MDPI and ACS Style

Chmiel, M.; Czerwinski, R.; Malcher, A. FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC. Appl. Sci. 2021, 11, 10183. https://doi.org/10.3390/app112110183

AMA Style

Chmiel M, Czerwinski R, Malcher A. FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC. Applied Sciences. 2021; 11(21):10183. https://doi.org/10.3390/app112110183

Chicago/Turabian Style

Chmiel, Miroslaw, Robert Czerwinski, and Andrzej Malcher. 2021. "FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC" Applied Sciences 11, no. 21: 10183. https://doi.org/10.3390/app112110183

APA Style

Chmiel, M., Czerwinski, R., & Malcher, A. (2021). FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC. Applied Sciences, 11(21), 10183. https://doi.org/10.3390/app112110183

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