Leakage Current Mitigation of Photovoltaic System Using Optimized Predictive Control for Improved Efficiency

Abstract

This paper proposes an optimized predictive control strategy to mitigate the potential leakage current of grid-tied photovoltaic (PV) systems to improve the lifespans of PV modules. In this work, the PV system is controlled with an optimized predictive control algorithm that selects the switching voltage vectors intelligently to reduce the number of computational burdens. Thus, it improves the dynamic performance of the overall system. This is achieved through a specific cost function that minimizes the change in common-mode voltage generated by the parasitic capacitance of PV modules. The proposed controller does not require any additional modulation schemes. Normalization techniques and weighting factors are incorporated to obtain improved results. The steady state and dynamic performance of the proposed control scheme is validated in this work through simulations and a 600 W experimental laboratory prototype.

1. Introduction

Increased consciousness about the significance of human activities has led to increased awareness of renewable energy sources in the 21st century. Solar energy has drawn incredible interest as a possible substitute for conventional energy sources because of its intrinsic advantages, such as its clean nature, lack of moving parts, and sustainability [1,2,3]. Photovoltaic cells convert solar radiation into electrical energy through the photovoltaic effect. The first-generation photovoltaic cell materials are based on monocrystalline, polycrystalline, and gallium arsenide (GaAs) technologies. The second generation includes amorphous silicon and thin microcrystalline silicon films, cadmium sulfide or telluride, and copper indium gallium selenide based solar cells. The third and fourth generations incorporate nanocrystalline films and stacked multilayers of inorganics based on III–V materials, such as GaAs/GaInP, organic-based (polymer) nanomaterials (e.g., carbon nanotubes), graphene, and their derivatives [4].

The monocrystalline Si cells are manufactured using the Czochralski process [5]. In this process Si ingots are grown from small monocrystalline silicon seeds and cut to yield Si wafers. This produces Si crystals with diameters ranging from 10 to 300 mm and lengths from 50 cm to 2 m. Polycrystalline Si is obtained using the Siemens process [6]. This process consists of gasification of metallurgical grade Si, distillation, and finally deposition to yield ultrapure silicon. The production of GaAs can be condensed into four stages: growth of ingots, wafer processing, epitaxy, and the manufacturing of devices [7]. The traditional production of second-generation photovoltaic cells follows the roll-to-roll process [8]. First, a cylindrical sheet is unfurled (as superficial deposition) and the sheet is washed and printed with an insulating layer. Si is subsequently deposited on the reflector, and the transparent conductive oxide is put on the silicon layer. The third generation (dye-sensitized solar cell) consists of low-cost solar cells in the form of thin films [9]. They are based on the formation of a semiconductor between a photo-sensitized anode and an electrolyte. Fourth-generation photovoltaic cells, such as organic photovoltaic cells, exploit conductive organic polymers or small organic molecules for light absorption. Perovskite solar cells are comprised of a light-harvesting active layer and a designed perovskite compound (hybrid organic-inorganic lead or tin halide). It is placed between the electron-transport (mesoporous material or TiO₂) and hole-transport layers [10,11].

The grid-tied photovoltaic (PV) converters need to be designed for high efficiency, small size, and low cost and weight [12]. These converters use line-frequency transformers to provide galvanic isolation, which makes the overall system bulky. However, few PV converters use high-frequency converters for galvanic isolation [12]. The high-frequency isolation transformers are smaller than line-frequency transformers, but high-frequency transformer-based power converters have many power stages, which increase the system’s complexity and reduce the system’s efficiency. Currently, the transformerless PV converters are extensively used in low-power distributed PV generation by imposing DIN VDE 0126-1-1 standards [13]. Due to the removal of transformers, the leakage current appears in the system because of changes in common-mode voltage (CMV) across the parasitic capacitance, which appears between the PV module and the ground [12]. Moreover, the leakage current leads to safety issues in the system, power losses, harmonic distortion in grid current, and electromagnetic interference issues. Therefore, they must be limited within a utilitarian boundary [13].

Solar modules are typically connected to PV converters, which convert variable DC output to AC (line frequency) for commercial grid applications. Several power converters reported in literature, such as two- and three-level inverters, H5, H6, and HERIC, have found commercial and academic research acceptance [14,15,16]. Traditional inverters are unable to provide high efficiency at higher power ratings; therefore, converter topologies are moving toward multilevel structures. Among the various multilevel inverters, cascaded H-bridge multilevel inverters (CHB-MLI) have several advantages as compared to other converters [17,18,19,20,21]. The use of CHB inverters also opens up the prospect for removal of transformers from PV systems. MLIs are more attractive because of their lower device stress and low dv/dt. A CHB made up of n full bridges (4n power switches) can synthesize 2n + 1 voltage levels when the supply voltage is the same for each full bridge. Reduction in switches per output voltage levels can be achieved in CHB structures easily, if different supply voltages are selected for each full H-bridge [20]. Due to the higher number of DC voltage sources used in CHB-MLIs, their application is restricted for higher voltage levels. In due course, asymmetrical CHBs will evolve, until DC voltage sources can be replaced by capacitors. The topology used in this paper consists of two asymmetrical H-bridges and is known as hybrid MLI (HMLI) for generating nine output voltage levels. The DC voltage source (in place of a PV panel) supplies one of the full H-bridges, whereas a capacitor supplies the other one. By appropriately controlling the ratio between the two voltages, different output levels can be generated. This facilitates the elimination of bulky transformers, which makes the overall system lighter and more efficient. However, the removal of the transformer gives rise to leakage current. Due to the change in CMV, leakage current flows though the PV panel, which depreciates the lifespans of the PV modules.

Leakage current can be mitigated using several methods, such as by changing converter topology, including filters [22], changing modulation schemes [23,24], and altering control schemes [25,26]. Few methods are employed for changing converter topology (e.g., the conventional H-bridge is modified by adding more switches to form the familiar H5 and H6 converters). The leakage current can be reduced by including an extra filter, as reported in Lai, R. et al. [22]. The switched CMV can be kept constant by using a precise modulation scheme. Modification in the modulation schemes of conventional converters is one of the solutions for reducing leakage current. Multicarrier pulse width modulation (MC-PWM) and space vector modulation (SVM) are two well-known modulation techniques used in MLIs [24,25]. The SVM technique is more productive due to better switching control. However, it requires regress efforts for implementation. In Kang, D.W. et al. [24], SVM is used to reduce the leakage current in transformerless PV inverter topology. However, switching state selection is not easy in terms of practical implementation. MC-PWM also increases the computational burden because of a higher number of carrier signals.

Among the reported control schemes, model predictive control (MPC) is one of the better control schemes because of its robust dynamic and static characteristics. In this work, an optimized finite control set (FCS) MPC is utilized for overall control and for reducing leakage current from PV panels [27,28,29,30,31,32]. This paper uses a transformerless HMLI PV system that synthesizes different multilevel output voltage levels. Capacitor voltage balancing and the elimination of leakage current is achieved through a modified FCS-MPC scheme. The number of computational burdens is minimized to attain optimum results by adjusting the selection of switching vectors. The control algorithm is also optimized for compilation in any microcontroller. Normalization and weighted techniques are also implemented to obtain improved results [32].

The proposed control structure and converter architecture are discussed in Section 2. The different voltage levels obtained from HMLI and their impacts on leakage current are also discussed, as are the salient features for the modelling of optimized FCS-MPC, which are particularly useful for PV systems. The modified control scheme also implements current control and capacitor voltage balancing, as discussed in Section 2. The optimization is explained with mathematical concepts. The simulation and experimental results are discussed in Section 3 and Section 4, respectively, and conclusions are drawn in Section 5.

2. Modified Topology and Control Scheme

The conventional multilevel cascaded H-Bridge (CHB-MLI) uses an isolated DC source for every H-bridge. The number of voltage levels generated can be generalized to (2k + 1), where k is the number of H-bridges. An inverter with two H-bridges uses two DC sources of equal magnitude for a five-level output voltage generation. However, it requires more DC sources for each H-bridge to generate higher voltage levels, which increases the cost of the system. A capacitor can be used instead of a DC voltage source. Furthermore, the same configuration with one DC source and one capacitor at their respective H-bridges can generate five, seven, or nine voltage levels, respectively. A trade-off has to be made as increasing the voltage levels decreases the magnitude of the maximum voltage generated. The use of a capacitor raises the issue of charging and discharging so that the capacitor voltage can be balanced at the desired value. The balancing of the capacitor can be attained by cascading another control loop in addition to a grid current control loop using conventional PI-based control schemes [15,16,17]. However, these control loops make the overall system complex. This issue of intricacy is further augmented when additional control schemes are introduced to reduce the leakage current in grid-tied PV converters. This can be smoothly achieved with the proposed proper control scheme.

The modified topology, a hybrid-MLI (HMLI), effectively solves the control challenges created by the incorporation of a capacitor in one of the H-bridges. The modified model predictive control (MPC) implemented in this work uses multivariate, multi-input, and multi-output optimisation problems. The proposed modified circuit is depicted in Figure 1. A block diagram for the overall control scheme is shown in Figure 2. The control loop takes the capacitor voltage (V_cap), grid voltage (V_g), current (I_g), reference current (I_ref), grid angle (θ), and weighting factor. The grid angle is generated through a phase-locked loop (PLL). All these control loops use modified MPC to generate the required switching signals fed to the HMLI.

The multilevel output generation property of the MLI is fully used in the proposed modified HMLI. The voltage across capacitors is maintained at a third of the input voltage (V_DC), which results in the maximum of different voltage levels possible obtained across two H-bridges (i.e., nine). The 16 combinations of voltage vectors are given in

Table 1. Generated nine voltage levels.

to generate these nine levels. However, only nine separate vectors are required out of only 16 voltage vectors to generate the required voltage level. The modified MPC only considers these nine states, thus reducing the computation time significantly. The number of distributed states is also further minimized using optimization, which will be discussed later in this paper. In addition, two extra switches, S₅ and S₆, are incorporated to minimize the leakage current problem, as shown in Figure 1.

The parasitic capacitance is formed between the PV module and the ground. The leakage current is generated by a change in the CMV across it. The CMV is the average value of voltage between the output and the reference point. The negative terminal of the DC voltage, (i.e., terminal N) is called the common reference point for the upper H-bridge. Similarly, for the lower H-bridge inverter, N’ is the common reference point. The parasitic capacitance is formed for the upper H-bridge. The CMV and leakage current in the two H-bridges are also the same. The CMV voltage (V_CM) for the upper full-bridge can be expressed in (1):

$$V_{\mathrm{CM}}=\frac{V_{\mathrm{AN}}+V_{\mathrm{BN}}}{2}$$

(1)

where V_AN and V_BN are voltages between the mid-point of the upper H-bridge legs to the negative terminal of the DC link. V_AB is the voltage between the mid points of the two legs of the upper H-bridge inverter. V_inv is the output voltage across the load. The leakage current primarily depends upon the magnitude of the CMV. The CMV can be derived in (2) and (3) as follows:

$$V_{\mathrm{CM}}+V_{\mathrm{AN}}-V_{\mathrm{Lg}}-V_{\mathrm{inv}}=0$$

(2)

$$V_{\mathrm{CM}}+V_{\mathrm{BN}}-V_{\mathrm{Lg}}-V_{A^{\prime }{B}^{\prime }}=0$$

(3)

V_inv has much less effect on parasitic capacitance. Hence, it can be neglected. The filter inductance, L_g, and the voltage drop caused by L_g are considered the same for the two H-bridges for ease of analysis. The mathematical expression of the CMV can be obtained by adding Equations (2) and (3) as follows:

$$2V_{\mathrm{CM}}+V_{\mathrm{BN}}+V_{\mathrm{AN}}-V_{A^{\prime }{B}^{\prime }}=0$$

(4)

From Equation (4), the CMV can be written as:

$$V_{\mathrm{CM}}=\frac{V_{A^{\prime }{B}^{\prime }}-V_{\mathrm{AN}}-V_{\mathrm{BN}}}{2}$$

(5)

Equation (5) is utilized for defining the CMV in several intervals of referenced time.

3. Modelling and Optimization

In this section, the mathematical modelling of current tracking, capacitor voltage balancing, and leakage current mitigation in HMLI is derived.

3.1. Current Tracking

The nine (highlighted) valid switching states of the HMLI defined in Table 1 are used for tracking load current. For grid-tied HMLI with inductive (R-L) loads, the analytical expression can be written as in (6):

$$V_{\mathrm{inv}}-R_g{I}_g-L_g\frac{d{I}_g}{dt}-V_g=0$$

(6)

where V_inv is output voltage, R_g is grid filter resistance, and L_g is filter inductance.

To predict the current for the next sampling instant, Equation (6) needs to be converted into discrete time. The variation of I_g at two sampling instances, k and k + 1, are alienated by a sampling time of T_S. This can be expressed in (7) as follows:

$$\frac{d{I}_g}{dt}=\frac{I_{g,k+1}-I_{g,k}}{T_S}$$

(7)

To derive an expression for current prediction, the relation between V_inv and the grid current I_g needs to be expressed in discrete time. The future value of the current can be predicted by using a first-order Taylor series [24]. Considering h as the prediction horizon, the grid current can be written as in (8):

$$I_g\left(k+h\right)=\left(1-\frac{R_g\times T_s}{L_g}\right)\times I_g\left(k+h-1\right)+\frac{T_s}{L_g}\left(V_{\mathrm{inv}}\left(k+h-1\right)-V_g\left(k+h-1\right)\right)$$

(8)

As there is more than one term each for different purposes, weighting components will be assigned with each term. However, for the V_inv,min calculation, only the term that regulates current is considered. The cost function (CF) is an essential factor in MPC. Here CF is defined as G₁, G₂, and so on for different parameters. G₁ is taken as a CF for current tracking and grid synchronisation as given in Equation (9). Weighting factors (W₁, W₂, etc.) are assigned to each term of CF, which regulates the robustness of the control parameter. The CF (G₁) for current tracking can be expressed as:

$$G_1=W_1{\left(I_g^{*}-I_{g,k+1}\right)}^2$$

(9)

where $I_g^{*}$ is the reference amplitude of the grid current.

Substituting Equation (8) in (9),

$$G_1={(I_g^{*}\left(k+1\right)-\left(1-\frac{R_g\times T_s}{L_g}\right)\times I_g\left(k\right)-\frac{T_s}{L_g}\left[V_{\mathrm{inv}}\left(k\right)-V_g\left(k\right)\right])}^2$$

(10)

The conventional MPC iterates over all of the voltage vectors. However, in this work, the voltage vectors are reduced to nine for each voltage level. The voltage vectors are further reduced to three by implementing the optimization discussed below. The optimum voltage can be obtained by differentiating G₁ by V_inv to zero, given in (11) as follows:

$$\frac{d{G}_1}{d{V}_{\mathrm{inv}}}=0$$

(11)

The derivative of $G_1$ w.r.t V_inv can be written as in (12):

$$\frac{d{G}_1}{d{V}_{\mathrm{inv}}}=\frac{-2T_s}{L_g}[I_g^{*}\left(k+1\right)-\left(1-\frac{R_g\times T_s}{L_g}\right)\times I_g\left(k\right)-\frac{T_s}{L_g}\left[V_{\mathrm{inv}}\left(k\right)-V_g\left(k\right)\right])$$

(12)

By solving Equation (12),

$$V_{\mathrm{inv}, \min }=\frac{-L_g}{T_s}A$$

(13)

$$\mathrm{where} A=\left(1-\frac{R_g\times T_s}{L_g}\right)\times I_g\left(k\right)+\frac{T_s}{L_g}\left(V_g\left(k\right)-I_g^{*}\left(k+1\right)\right)$$

(14)

The minimum voltage can be written in (15) as follows:

$$V_{\mathrm{inv},\min }=-\frac{L}{T_S}\left(\left(1-\frac{R·T_S}{L}\right).I_{g,k}-I_{ref}\right)+V_g$$

(15)

As the slope of Equation (15) is negative, it ascertains that minimum voltage is generated. V_inv is bound to V_(p-p). It needs to be cut to allow the choice of the correct voltage vectors. Out of the chosen voltage vectors, a maximum of three are hard-coded. When V_min is within the constrained voltage range, the modified MCP loop iterates through only three vectors to predict the vector that will provide the minimum-cost value. A detailed explanation is shown in Figure 3. The program iterates follow CF minimisation. These modifications lessen the running time per multiple iteration. The computational time is reduced because of the modifications, as outlined in

Table 2. Effect of modification in MPC control scheme.

Without Voltage Vector Selection	With Voltage Vector Selection
$1.0435\times {10}^{-5}$	$3.3102\times {10}^{-6}$
$1.0557\times {10}^{-5}$	$3.1408\times {10}^{-6}$
$1.0732\times {10}^{-5}$	$3.2107\times {10}^{-6}$
$1.0615\times {10}^{-5}$	$3.1326\times {10}^{-6}$
$2.0162\times {10}^{-5}$	$3.6402\times {10}^{-6}$
Average	Average
$\mathrm{time} \left(\mathrm{s}\right)=1.0775\times {10}^{-5}$	$\mathrm{time} \left(\mathrm{s}\right)=3.2435\times {10}^{-6}$

.

3.2. Capacitor Voltage Balancing

For capacitor voltage balance, the capacitor voltage is compared to the desired reference voltage. The charging and discharging occurs because of the switching action of S₃ and S₄, as depicted in Figure 4. Charging occurs when switches S₄ and S_3′ are turned on and charging occurs when S₃ and S_4′ are turned on, as shown in Figure 4a,b, respectively. It also depends on the current flowing through the capacitor and is taken to realise a mathematical model of capacitor voltage balance. The voltage of the capacitor (working as source in the H₂ bridge) is repesented by adding it as one more term to the CF. To predict capacitor voltage (V_c) for the next sampling instant, the relation between current and voltage variation can be written in Equations (16) and (17) as follows:

$${\displaystyle \int }\frac{i\left(S_4-S_3\right)}{C}dt={\displaystyle \int }d{V}_c$$

(16)

$$\frac{i\left(S_4-S_3\right)}{C}{T}_S=V_{k+1}-V_k$$

(17)

V_k+1 and V_k are the capacitor voltages at time instants (k + 1)T_S and kT_S, respectively.

By rearranging the predicted capacitor voltage, $V_{\mathrm{c}}\left(k+1\right)$ can be written in (18) as:

$$V_c\left(k+1\right)=V_c\left(k\right)+[\left(S_3-S_4\right)\times (\frac{i·T_S}{C})]$$

(18)

The predicted capacitor is compared with the reference value of the capacitor (33% of the DC voltage source) by adding the modelled term in the CF (G₂) in (19) as follows:

$$G_2=W_2.{\left(0.33\times V_{DC}-\left(V_k-\frac{i\left(S_3-S_4\right)}{C}\right)\right)}^2$$

(19)

An additional term in Equation (19) needs the switching vectors responsible for the charging and discharging of the capacitor. The adjacent voltage selection reduces the maximum iteration to only three vectors.

3.3. Leakage Current Minimization

To reduce the leakage current, two switches, S₅ and S₆, are included in the circuit. When there is commutation from ON to OFF, the voltage across the parasitic capacitor changes from V_DC to 0 and vice versa. This sudden change in voltage results in leakage current. S₅ and S₆ are additional switches and are turned ON for most of the duration of a cycle. When the state of a switch changes from 0 to 1, the adjacent switch (S₅) has same state, and is triggered to turn off to include resistance (R₁) in the leakage current path for reducing the rate of the charging and discharging of the parasitic capacitor. Hence, the leakage current is reduced. Similary, the resistance (R₂) is included when S₆ is triggered to turn off. The flows of leakage current are depicted in Figure 5a,b, respectively. At the instant when a DC source commutates from being disconnected to connected or vice versa, the surge in current is mitigated and the output waveforms are kept intact. The power loss cause by the addition of a resistor to the leakage current path is negligible, as the magnitude of the obtained leakage current is much less and a maximum of two switches are in conduction mode throughout the operation of HMLI. Also, the energy loss caused by the charging and discharging of a parasitic capacitor (C_p) for input voltage V_dc in a time period of T can be given as:

$$P=\frac{C_p{V}_{DC}^2}{T}$$

(20)

with C_p = 100 nF and V_dc = 100, power loss is less than 1 W.

3.4. Weighting Factor and Normalization

There are two ways to choose the weighting factors related to the control objective [28]. The first one is offline and the second one uses mathematical dependencies in the control objective to reach the selected result. Here, W₁ is taken as 0.8 and the W₂ is varied between 1.9 to 18, because of only two terms in Equations (9) and (19), respectively. This can be different for different working conditions. In this work, a normalization method that evaluates the maximum variations of every state variable is used as an extra optimization norm in CF, as given in Equation (20). The modified MPC minimizes the normalized and weighted CF for the switching-state selections.

$$\mathrm{CF}=\sqrt{{\left(\frac{G_1}{max(I_{g,i}\left(k+1\right))-min\left(I_{g,i}\left(k+1\right)\right)}\right)}^2+{\left(\frac{G_2}{max(V_{cap,i}\left(k+1\right))-min\left(V_{cap,i}\left(k+1\right)\right)}\right)}^2}$$

(21)

4. Simulation Model and Results

Simulation analysis was carried out to verify the working of the proposed system. In this work, the theoretical analysis of the proposed HMLI system for output current tracking and capacitor voltage balancing and leakage current minimization is discussed in detail. A computer program generated on the basis of the algorithm (shown in Figure 4) is used in the controller design. Simulation was carried out on a MATLAB R2017a with a 64-bit Intel(R) Core ™ i7-4770 CPU operating at 3.40 GHz. Simulations were done on the basis of the presented theoretical analysis and the results of the simulations were subsequently presented.

4.1. Model Description of the HMLI

The HMLI was designed in the MATLAB/Simulink. The various parameter values are listed in

Table 3. Simulation parameters of HMLI.

Parameters	Values
Inductive load	1.2 mH
Resistive load	20 Ω
DC-Link capacitor	1000 µF
Sampling frequency	10 KHz
DC voltage	150 V
Capacitor voltage	50 V
Reference load current (peak)	6 A

. The first module is supplied by a DC source, while a capacitor is used for the other. For getting a nine-level output of the HMLI, the capacitor voltage needs to be 33% of the input DC voltage.

4.2. Simulation Results

The simulation results are at first obtained with an R-L load. Figure 6a shows the output voltage waveform. It can be seen that output voltage consists of a nine-level and the peak value of the output voltage is 200 V, which is the sum of the DC-supplied voltage and the capacitor voltage of the other H-bridge.

All the voltage levels observed in the output are 200 V, 150 V, 100 V, 50 V, 0 V, −50 V, −100 V, −150 V, and −200 V, respectively, at 50 Hz. In Figure 6b, the output current and reference current are depicted. From this figure, it can be clearly observed that load current is precisely tracking the reference current. The peak-peak current is 12 A, where the blue line shows the reference current and the red line shows the output current. This demonstrates the quick adaptiveness of the modified MPC algorithm. From these above figures, we can conclude that the system-output voltage and current are perfect according to the theoretical analysis.

The capacitor voltage waveform is balanced at 50 V, as shown in Figure 6c. The capacitor voltage value has a maximum variation of less than 0.25 V (approximately). It is between 50 V and 52 V for a current range of 1 A to 6 A, which shows the effectiveness of capacitor voltage balancing. In Figure 6d, the magnified capacitor voltage is shown for a small interval. In this figure, the capacitor charging and discharging cycles are clearly visible. Whenever capacitor voltage is increased from the reference value, the controller applies the required voltage vector, which discharges the capacitor, and tries to bring it to the reference value. A similar control method is applied to increase capacitor voltage. This process is repeated and the controller balances the capacitor voltage at the desired value. Thus, we can conclude that the simulation is working properly and in accordance with the theoretical analysis.

To show the variation of leakage current in HMLI, the waveform for leakage current and CMV are shown for the transient circuit (TC) in disabled and enabled conditions. Figure 7a,b show CMV and leakage current in the disabled TC and leakage current occurs around 30 mA. Figure 8a,b show CMV and leakage current when the TC is enabled and leakage current occurs around 19 mA.

4.3. Dynamic Behaviour

For verifying the dynamic performance of the controller, some parameters are changed during the running condition. The simulation is tested when the current reference is changed from 4 A to 6 A and vice-versa. The effect of these transitions on the load current are shown in Figure 9a,b, respectively. From Figure 9a,b, it can be observed that when the reference current is changed at 5 s, the load current is changed to track the reference current. The output current is tracking the reference current accurately whether its amplitude is increased, decreased, or kept constant. Thus, the smooth closed loop control and fast dynamic response of the proposed control scheme is verified.

4.4. Model Description of Grid Connected HMLI

The PV system leakage current standards are provided according to grid safety and regulation. Hence, it is necessary to check leakage current minimization in grid-connected mode. The necessary parameter values are provided in

Table 4. Simulation parameters for grid-connected HMLI.

Parameters	Values
Inductive load	2 mH
Resistive load	15 Ω
DC-Link capacitor	1000 µF
Sampling frequency	20 kHz
DC voltage	100 V
Grid voltage	110 V (peak)
Capacitor voltage	33.33 V
Reference load current (peak)	7 A

. The dynamic simulation results are presented here, in which the current is increased at 5 s and decreased at 5.1 s to show the fast dynamic response of the system in grid-connected mode. The grid connection control is implemented using PLL, which provides a phase angle for the current. The provided phase is used with a sine function and a constant magnitude to generate the current reference. Figure 10a shows output voltage levels of grid-connected HMLI. For the current reference of 6 A, HMLI generates seven levels as there is no requirement for two levels (133 V, −133 V) for low current generation. For the current reference of 7 A, HMLI outputs nine voltage levels (−133.33 V, −100 V, −66.66 V, −33.33 V, 0 V, 33.33 V, 66.66 V, 100 V, and 133 V).

When the current reference is again decreased to 6 A, the HMLI output voltage generation decreases to seven levels. Similar charging and discharging instances in capacitor voltage can be observed in Figure 10b. The capacitor is provided with charging and discharging vectors in less time as the sampling frequency interval is increased. Figure 10c,d show grid current and grid voltage respectively. Grid current is in accordance with the reference provided and grid voltage does not change because of proper inverter operation.

Figure 11a depicts the CMV of the HMLI. Figure 11b shows the RMS value of the leakage current, measured around 19 mA, and peak to peak it is also less than 300 mA. Both the RMS value and peak-to-peak value are under the regulatory norms. Thus, the simulation results presented here are in accordance with the theoretical expectation.

5. Experimental Validation

For experimental validation, the system parameters are taken as the same as in the simulation. The components used for the experiment are given in

Table 5. Components used in experiment.

Parameters	Attributes
Voltage sensor	LEM-LV 55 P
Current sensor	LEM-LA 25 P
Microprocessor	TI-TMS320F28335
Switches	IRFPS40N60K
Drivers	FOD-3184

. The sensor circuits and signal conditioning circuits are designed. The photograph of the experimental setup of the HMLI is shown in Figure 12. In Bridge H1, DC voltage is taken as 100 V and the magnitude of the reference current is set at 6.5 A. To represent the parasitic capacitance of the PV panel, a 100 nF capacitor is inserted into the circuit. Sampling is done at 20 kHz and the setup is tested first for R-L loads of 15 Ω and 2 mH.

The experiment was carried for a 600 W laboratory prototype. The steady-state output voltage and load current waveform are shown in Figure 13. The nine-level voltage waveform has been generated at the output of the HMLI. It consists of 0, ±33.33 V, ±66.66 V, ±100 V, and ±133.33 V output voltage levels. The voltage of the capacitor is balanced at 33 V. The output voltage and current magnitude are approximately 84.8 V and 7.05 A (RMS), respectively. The leakage current and CMV waveform are shown in Figure 14. The obtained RMS current is around 20 mA and it can vary within 5% of the given value because of precision errors of the measuring instrument.

The output voltage of the high voltage (HV) bridge and low voltage (LV) bridge are shown in Figure 15. The important observation to make in Figure 15 is that the voltage switchings of the HV bridge happen only in limited time intervals during a period of grid voltage. Leakage current is also minimized as the legs of HV bridge have a DC supply as a PV panel. The HMLI has also been experimentally validated at grid voltage 110 V (RMS). The grid current is precisely regulated to synchronize with the grid voltage. The grid voltage and current are depicted in Figure 16. The control strategy effectively balances the capacitor voltage balancing and tracks the reference current.

Figure 17 and Figure 18 show the dynamics of the output voltage for increasing and decreasing currents, respectively. For the low-current value, the control algorithm does not choose high voltage levels as the resistance value is fixed. Hence, at 3 A (peak) current, HMLI generates only five levels. In Figure 17, the current reference is decreased from 7 A (peak) to 3 A (peak) and the opposite sequence is implemented for Figure 18. From both of the figures, it can be confirmed that the proposed MPC provides a fast dynamic response.

The load current dynamics of the proposed controller is also experimentally validated in Figure 19 and Figure 20, respectively, which show that the load current tracks quickly for increased and decreased reference currents, respectively. The system shows excellent dynamic results using the proposed control scheme.

6. Comparison Results

Generally, in FCS-MPC the number of operations are increased for more voltage vectors and objectives used in the cost function. A computational burden analysis is presented in

Table 6. Comparative results in terms of execution time.

Parameters	MPC Conventional Scheme	Proposed Control Scheme
DSP execution time (µs)	110.73	32.52
Reduction rate	-	71.5%

. As expected, restricting the required voltage vectors using optimized MPC reduces the burden time. This is also caused by the calculation of V_{inv, min} before iterating through the vectors. The average execution time in a conventional MPC method is around 110.73 µs and, with optimization, it is reduced to 32.52 µs. Thus, with the proposed MPC-optimization method, an approximate 71% reduction in execution time is achieved.

Comparison in Terms of Leakage Current

Comparative results in terms of leakage current and efficiency for various converters are given in

Table 7. Comparative results in terms of leakage current.

Control Technique/Topology	Leakage Current (RMS)	Efficiency %
H5	45 mA	97.59
HERIC	48.8 mA	98.16
Hybrid-bridge topology	80 mA	96.71
Full H- bridge Bipolar modulation	84.5 mA	95.73
PD-MCPWM	98 mA	95.12
Full H- bridge unipolar modulation	2.7 A	93.7
Hybrid topology	2.6 A	97
Proposed	20 mA	98.57

. It can be observed that the proposed controller provides better comparative results in terms of the magnitude of leakage current.

7. Conclusions

In this paper, we propose a modified MPC controller that controls the output current and voltage of the HMLI to a given reference value. It also effectively balances the capacitor voltage. This is achieved through a predictive model and the minimization of specific cost functions to generate switching patterns. The proposed control scheme is also used to reduce the leakage current in modified HMLI and is minimized to an extent of 20 mA experimentally. The steady state and dynamic performances are demonstrated through extensive simulation results. A 600 W laboratory prototype was developed to validate the proposed system through experimentation. The experimental results are in accordance with theoretical analysis. The transient behavior explains the smooth and fast dynamic responses of the controller. All control is achieved without using additional modulation techniques.