Novel Design Method in Wireless Charger for SS Topology with Current/Voltage Self-Limitation Function

Abstract

This study proposes a novel wireless power transfer (WPT) resonance compensation design method based on the SS topology with a self-limitation function that achieves fault tolerance without additional components when the secondary circuit is in a short and open state. Conventionally, WPT compensation topologies have constant current (CC) or constant voltage (CV) output characteristics. The CC and CV characteristics can lead to overvoltage and overcurrent, respectively. Several control systems have been proposed to counter this issue; however, they tend to increase the cost and weight of the system. The proposed topology has a self-limitation function that limits the voltage–ampere output. Here, the wireless charging system was designed after the parameters were obtained using the proposed analysis. The performance of the proposed design was verified by configuring a 400 W experimental prototype and comparing it with the conventional series–series (SS) topology. Experimental results indicated that the system could effectively limit the output voltage and current resulting from open-or short-circuit states.

1. Introduction

Wireless power transfer (WPT) systems are widely applied in various applications such as electric vehicles (EVs), mobile phones, unmanned aerial vehicles, and robots [1,2,3,4,5,6,7,8]. These systems overcome the technical limitations of battery capacities and offer an easier charging alternative to plug-in charging methods during unmanned and autonomous mobility, thereby eliminating the possibility of hazards such as electric shock and leakage from cracked and worn-out cables [9,10].

WPT systems employ inductive power transfer (IPT) and magnetic resonance methods. Most of the WPT devices adopt the IPT charging method owing to its high efficiency. Major studies related to WPT based on IPT have focused on the pad design and the compensation topology of the IPT converter.

In terms of pad design, the studies mainly focused on overcoming the low coupling coefficients of existing circular and rectangular pads. The pad designs with polarity proposed in recent studies offer a higher coupling coefficient k and better consistency in alignment than basic pads [11,12,13,14,15].

Compensation topologies have been proposed to resolve the phase shift caused by the coil inductance of the charging pad. The phase difference between the voltage and current increases the current flowing through the IPT system owing to the increase in circulating current and reactive power, which leads to additional system losses. Various compensation topologies have been presented and analyzed. These topologies are classified into four basic resonant topologies, i.e., the series–series (SS), series–parallel (SP), parallel–series (PS), and parallel–parallel (PP). Furthermore, certain high-order topologies have been proposed to improve the compensation characteristics [16,17,18,19,20]. Compensation topologies are significant parameters that can improve efficiency by minimizing the volt-ampere (VA) ratings. It further influences the constant output characteristics (current or voltage), which are determined by the constant current (CC) or constant voltage (CV) compensation topology structure.

Most IPT systems have either CV or CC output characteristics; thus, the output characteristics can cause overcurrent or overvoltage when charging the battery through the IPT system, which can damage the battery [21,22]. Moreover, when WPT is applied to an automated system, it is difficult to respond immediately to prevent secondary damage in the event of a battery accident. To prevent these problems, most batteries include a battery management system (BMS), which has an internal monitoring function and a control-charging mode. When the state of charge (SoC) is low, the BMS can be in CC mode to avoid overcurrent, and when SoC is high, the BMS changes the CC mode to CV mode to avoid overvoltage. However, applying BMS and telecommunication functions inevitably increases the system’s cost and weight. Thus, it is not suitable for low-cost and low-volume mobility systems such as drones, mobile phones, wireless earphones, and electric bikes. To reduce the cost of controllers in low-cost models, researchers have proposed various safety strategies. It was proposed in [23] that a slot current protection circuit, such as ZnO resistance, be included or a signal from the control sensor be sent to the metal–oxide semiconductor field-effect transistor (MOSFET) switch to protect against faults. However, this mechanism offers protection only in the case of a fault, and a BMS is still required, which increases the cost owing to specific components.

Meanwhile, in [24,25], a CC/CV solution via topological access was proposed; in [24], a circuit that adds a coil in the primary pad to achieve the CC/CV mode was proposed, while in [25], a topology based on a high-order compensation topology was proposed. In [26,27,28,29,30], a hybrid topology was proposed to achieve the CC/CV mode by using a switching capacitor. In [26,27], CC/CV control by switching a capacitor between the two topologies was proposed. Further, CC/CV control was proposed in [28] by switching capacitors on the secondary coil. In [29], switching capacitors were proposed for both primary and secondary coils. In [30], a single switching capacitor and a variable operating frequency were proposed. However, these methods are not economically viable. In [24], the addition of a coil was required, and [25,26,27,28,29] are based on high-order topology, which requires additional components. In [26,27,28,29], more switches were required to change the charging mode, while a more complex controller was required in [30]. As these systems invariably cause an increase in cost or weight, they are unsuitable for low-cost WPT battery chargers. Thus far, there has been no reported study on the application of control strategies without including additional components.

In this study, a novel low-cost IPT compensation design method based on SS topology has been proposed. The proposed design method has resonance elements similar to those of the conventional SS design, but the resonance requirements are designed differently. Unlike the CC or CV characteristics of most conventional topologies, the proposed resonance design has a nonlinear converging current and voltage curve. Further, the proposed design method does not need additional control functions and components to prevent current/voltage fluctuations when an open or short state occurs on the secondary side.

This paper is organized as follows: A fundamental circuit analysis is presented in Section 2. The output characteristics are explained according to the load variation in Section 3. A prototype of the proposed design method is experimentally validated on a 400 W prototype. A control method for compensating for changes in output characteristics due to misalignment or tolerance is presented in Section 4. The comparison results of the proposed and conventional SS design methods, and the battery output characteristic results are presented in Section 5. The conclusions of the study are presented in Section 5.

2. Basic Principle

2.1. Fundamentals

Figure 1 shows the diagram of the IPT system. To simplify the circuit diagram, line resistance, core resistance, and parasitic parameters are not shown in this figure. A full-bridge inverter comprising four MOSFETs (Q₁–Q₄) was utilized to convert a direct current (DC) link voltage into an alternating current (AC) square wave voltage. U_s is the equivalent AC input voltage of the compensation topology. According to [29], U_s can be calculated as follows:

$$U_s=\frac{4U_{\mathrm{DC}}}{\pi }\sum _{n=1,3,5\dots }\frac{\sin (n\varphi )}{n}$$

(1)

Generally, only the fundamental harmonic (n = 1) is considered in the IPT converter system because high-order harmonics are filtered in the IPT converter circuit, which appear in the high-order harmonics of a high-impedance circuit. M represents the mutual inductance between the two pads. C_r and C_s represent the resonance capacitors in the primary and secondary coils, respectively. As illustrated in Figure 1, a loosely coupled transformer (LCT) works as an ideal transformer model. The coupling coefficient k of the LCT and its effective turn ratio are defined in (2) and (3). A bridge rectifier consists of four diodes (D₁–D₄) to rectify the sinusoidal AC voltage flowing from the IPT converter to the DC battery-charging voltage. R_L and C_o represent the DC output load and the output filter capacitance, respectively. U_o and I_o are the output voltage and output current, respectively. The following equations can be derived from [31]:

$$k=\frac{M}{\sqrt{L_p{L}_s}}$$

(2)

$$n=k\sqrt{\frac{L_p}{L_s}}$$

(3)

$$\left\{\begin{array}{l}{U}_L=\frac{\pi }{2\sqrt{2}}{U}_o\hfill \\ I_L=\frac{2\sqrt{2}}{\pi }{I}_o\hfill \end{array}\right.$$

(4)

where U_L and I_L represent the root-mean-square (RMS) values of U_o and I_o, respectively. Based on (4), the relationship between R_L and R_o is given as follows:

$$R_o=\frac{8}{{\pi }^2}{R}_L$$

(5)

Figure 1. IPT system.

Figure 1. IPT system.

2.2. Basic Analysis of the SS Topology with Conventional Design

Figure 2 depicts the proposed compensation design method based on the conventional SS topology. The SS topology with conventional design is the most widely applied resonance compensation network. Both the primary and secondary resonant capacitors are completely resonated with primary and secondary inductances. The two compensation capacitors C_p and C_s are designed using the following resonant equations:

$$L_p=L_m+L_{lkp}$$

(6)

$${\omega }_0^2{L}_p{C}_p={\omega }_o^2{L}_s{C}_s=1$$

(7)

$$\left\{\begin{array}{l}{Z}_{{22}_{-}SS}=R_L+j{\omega }_0{L}_s+\frac{1}{j{\omega }_0{C}_s}\hfill \\ Z_{r_{-}SS}=\frac{{\left({\omega }_{0}M\right)}^2}{Z_{{22}_{-}SS}}\hfill \\ Z_{{11}_{-}SS}=j{\omega }_0{L}_p+\frac{1}{j{\omega }_0{C}_{r_{-}SS}}+Z_{r_{-}SS}\hfill \end{array}\right.$$

(8)

where ω₀ is the resonant angular frequency, L_m is the magnetization inductance, and L_lkp is the primary leakage inductance. The self-inductance L_p can be divided into L_m and L_lkp. In the conventional SS resonance design, a resonance capacitor is resonated with inductance to reduce VA rating and primary circular current. From the corresponding secondary, reflect, and primary parasitic resistances, the output current can be calculated as follows:

$$I_{o_{-}ss}=\frac{j{\omega }_0{M}_{i_{n\_SS}}}{Z_{{22}_{-}SS}}=\frac{j{U}_s}{{\omega }_{0}M}$$

(9)

Figure 2. Proposed IPT compensation design method.

Figure 2. Proposed IPT compensation design method.

Figure 3 shows the voltage gain and phase angle of the SS topology with a conventional design for different load resistances. The primary and secondary self-inductances are presented in

Table 1. Measured parameters of the proposed IPT system.

Symbols	Parameters	Values
Us	DC link voltage	96 V
f	Operation frequency	85 kHz
Po,max	Maximum-output power	400 W
UL	Load voltage range	0–35.1 V
IL,short	Load current under short-circuit	23.4 A
k	Coupling coefficient	0.324
Lp	Primary self-inductance	56.76 µH
Ls	Secondary self-inductance	6.628 µH
Llk	Primary leakage inductance	38.421 µH
Cr	Leakage resonance capacitor	91.1 nF
RL	Load resistance	0.46–2000 Ω
RLp	AC resistance of Lp	58.7 mΩ
RLs	AC resistance of Ls	19.2 mΩ

, and the resonance capacitor is calculated by (7). As shown in (9) and Figure 3a, the output current is constant, and the voltage is linear to the load resistance. Therefore, CC characteristics can protect short faults, open faults can cause load to overvoltage.

Figure 3b shows the phase angle graph of the SS topology with the conventional design method. Ideally, the SS topology with the conventional design method can be implemented with a zero-phase angle independent of load resistance; however, in practical application, there is a concern that a bifurcation phenomenon may occur wherein the phase is changed depending on the load resistance value due to parasitic components, inductance tolerance, and temperature. In the bifurcation phenomenon, the MOSFET of the inverter is operated in the zero-current switching state, which can lead to switch failure [32].

As illustrated in Figure 3, when the SS topology with the conventional design method is in an open-circuit state, the output voltage rapidly increases.

In order to prevent faults caused by overvoltage and overcurrent, protection and wireless communication devices with low latency are required, which lead to increased cost and volume.

2.3. Basic Analysis of the Proposed Design Method

The SS topology with the proposed design method has a similar configuration to the conventional compensation topology design [33] that resonated with primary and secondary self-inductances. However, the SS topology with the proposed design method divides the primary self-inductance into a magnetizing inductance L_m and a virtual leakage inductance L_lkp to compensate for partial resonance. The primary side capacitor resonates with the leakage inductance. The secondary side has the same resonant conditions as the SS topology with the conventional design method that resonated with L_s. The equivalent impedance expressions for the secondary side is provided in (10)–(15). C_r is the capacitance that resonates with L_lkp, and Z_in is the equivalent input impedance.

$$C_s=\frac{1}{{\omega }^2{L}_s}$$

(10)

$$\frac{1}{j\omega C_s}+j\omega L_s=0$$

(11)

$$L_m=k{L}_p$$

(12)

$$L_{lkp}=(1-k)L_p$$

(13)

$$C_r=\frac{1}{{\omega }^2{L}_{lkp}}$$

(14)

$$Z_{in}=j\omega L_m+\frac{{\left(\omega k\sqrt{L_p{L}_s}\right)}^2}{R_o}$$

(15)

In (15), the imaginary value of the equivalent circuit impedance is always positive, and the proposed topology has inductive loads regardless of the load resistance. Thus, the proposed topology can be operated with zero-voltage switching (ZVS) over the entire load range. ZVS has the advantage of a reduced turn-on loss under MOSFET switching.

The primary current I_p, output current I_o, and output voltage U_o, respectively, are given in (16)–(18). As indicated by (17) and (18), the output current and voltage have complex components that show nonlinear output characteristics.

$$I_p=\frac{U_s}{Z_{in}}=\frac{U_s}{j\omega L_m+\frac{{(\omega M)}^2}{R_o}}$$

(16)

$$I_o=\frac{j\omega M{U}_s}{Z_{in }{R}_o}=\frac{\omega M^3{U}_s}{{\omega }^2{M}^4+{\left(L_m{R}_o\right)}^2}-j\frac{M{U}_s{L}_m{R}_o}{{\omega }^2{M}^4+{\left(L_m{R}_o\right)}^2}$$

(17)

$$U_o=I_o{R}_o=\frac{\omega M^3{U}_s{R}_o}{{\omega }^2{M}^4+{\left(L_m{R}_o\right)}^2}-j\frac{M{U}_s{L}_m{R}_o{}^2}{{\omega }^2{M}^4+{\left(L_m{R}_o\right)}^2}$$

(18)

In (17), the smaller the load resistance becomes, the more the real part converges and the imaginary part becomes zero. In (18), the larger the load resistance becomes, the more the imaginary part converges and the real part becomes zero.

Table 1 shows the practical parameters of the proposed design method used in Figure 2 and Figure 4, which were measured using an IM 3536 LCR Meter from HIOKI. Figure 4a,b show the graphs of the voltage gains and phase, respectively, from short to open state in the proposed design method. The operation frequency is equal to the resonance frequency, i.e., 85 kHz. As shown in Figure 4a, the voltage gains converge to a constant value under open load.

As shown in Figure 4b, there is a phase difference in the charging area. A small phase difference is required for ZVS but owing to the nature of the proposed design method, the phase increases with the increase in load resistance.

2.4. Analysis of High Order Harmonic Suppression

A prominent function of the compensation topology is that it can be utilized to compensate for the large leakage inductances of the LCT. The compensation topology can work as a passive bandpass filter that only allows the specified resonant frequency component to pass because the resonant networks comprise inductors and capacitors. Therefore, the harmonic components can be attenuated [34]. The proposed design method in this study uses partial resonance with leakage inductance, which may lead to concerns that harmonics cannot be completely eliminated. However, as the proposed design method has the structure of an inductive load whose impedance values increase proportionally with frequency, high-order harmonic components can be sufficiently attenuated. The impedance for filtering the harmonic component current can be explained as follows:

$$Z_s=j\omega L_s+\frac{1}{j\omega C_s}+R_o$$

(19)

$$Z_r=\frac{{(\omega M)}^2}{Z_s}$$

(20)

$$Z_{in}=j\omega L_p+\frac{1}{j\omega C_r}+\frac{{(\omega M)}^2}{j\omega L_s+\frac{1}{j\omega C_s}+R_o}$$

(21)

The secondary impedance Z_s, reflected impedance Z_r, and input equivalent impedance Z_in, respectively, are provided in (19)–(21). In addition, to verify the high-order harmonics suppression, Figure 5 shows the result of comparative simulations. By using the fast Fourier transform (FFT) tool to analyze the input current I_p, simulation results confirm that there are few high-order harmonic amplitudes of I_p. Therefore, the proposed topology can be approximated and computed using the fundamental harmonic approximation (FHA) method.

3. Analysis of Output Characteristics Variation

The SS topology with the proposed design method has a self-limitation characteristic. As indicated by (17) and (18), unlike conventional compensation topologies in which the output voltage and current are constant, the output equation consists of complex structures, and the values of the output current and voltage depend on the load. As the load resistance value fluctuates, the ratio between the reactance and resistance components included in the denominator of the output equation varies. Accordingly, the output characteristic equation is divided into three modes.

3.1. Mode 1: Current Limitation in Case of Short-Circuit

The output load current when the load resistance value is low is provided by (22). Based on (17), when short-circuit R_L is zero, the output load current equation becomes similar to that of the conventional SS topology [17]. The output equation is identical to the CC characteristics during short-circuit, and the phase angle is close to zero. Therefore, the proposed design method has the advantages of preventing transient current fluctuation when a short-circuit accident occurs under a load and protecting devices from damage caused by overcurrent.

$${\omega }^2{M}^4\gg {\left(L_m{R}_o\right)}^2\to I_L=\frac{2\sqrt{2}}{\pi }{I}_o\cong j\frac{2\sqrt{2}{U}_s}{\pi \omega M}$$

(22)

3.2. Mode 2: Voltage Limitation in Case of an Open-Circuit

The output load voltage is given in (23), which is based on (18) when the load resistance is infinity. When the load impedance is high, it can be approximated, and the output load voltage has a constant value regardless of the load. In (23) it is implied that, regardless of the coupling coefficient, the proposed topology can apply the desired output voltage according to the inductance design. The proposed topology prevents damage to the insulation and accident due to overvoltage, as no voltage is sustained for more than a fixed period even in the event of an open-circuit accidents without additional components.

$$U_{L,\max }=I_L{R}_L=\frac{{\pi }^2}{8}\cdot \frac{j\omega M{U}_s{R}_o}{j\omega L_m{R}_o+{(\omega M)}^2}\cong \frac{{\pi }^2{U}_s}{8}\sqrt{\frac{L_s}{L_p}}$$

(23)

3.3. Mode 3: Charging Region

The imaginary part of the output-voltage expression cannot be ignored in the charging region. The output voltage and output current exhibit non-linear changes, reaching the maximum-output power state in this interval. The resistance value when the output power reaches its maximum value is shown (24). Once the output power reaches the maximum value with the increase in the load resistance, it starts decreasing. It is necessary to consider the major charging regions of the battery.

$$R_{L,P_L=P_{\max }}=\frac{\omega M^2}{L_m}$$

(24)

Figure 6 presents a graph of the output current, output voltage, and output power of the proposed topology for different loads based on Table 1. Figure 6 shows that the proposed design method has a self-current/voltage limitation function depending on the load fluctuations. The maximum voltage and maximum current are fixed, which prevents the expansion of accidents during short-circuit and open-circuit states.

Thus, the proposed design method does not require additional components, which makes it suitable for low-cost WPT charging systems. In addition to the parameters proposed in Table 1, the short-circuit current and open-circuit voltage can be calculated and designed by modifying inductance, operating frequency, input voltage, and coupling coefficient. Battery management (BM) converter attachment is required to satisfy the output characteristics that vary depending on the battery SoC and the parameter tolerance [35].

4. Experimental Verification

4.1. The Proposed Hybrid IPT Charger’s Parameter Design for CC/CV Modes

After the load-specific characteristics of the proposed design method were verified (as described in Section 3), a design of the primary and secondary pads that satisfied the desired P_L, V_L, and I_L was crafted. The maximum voltage and maximum current are given in (17) and (18), and accordingly, the pad parameters were considered. As indicated by (22), (23), and (24), this had an impact on the ratio of the pad’s mutual and magnetization inductances. Figure 7 shows the 3D geometry design of the LCT, and its detailed design parameters are listed in

Table 2. Designed dimensional parameters of LCT.

Parameters	Values
Air gap distance	10 mm
Turns per coil	Np: 17, Ns: 5
Primary coil dimension	180 mm × 92 mm × 3.1 mm (0.12 mm/500)
Primary ferrite plate dimension	200 mm × 50 mm × 5 mm
Primary shield dimension	244 mm × 136 mm × 2 mm
Secondary coil dimension	180 mm × 92 mm × 3.1 mm (0.12 mm/500)

.

Considering the voltage and current on the primary and secondary pads, the appropriate wire diameter and distance of insulation between wires were considered. The coupling factor is affected by the size of the pad, the winding design, the external and internal diameters of the winding, and the separation distance. In order to increase the coupling factor, ferrite was added to the primary coil. On the secondary side, the pad is only composed of coils to reduce weight. To validate the analysis, a prototype of the proposed topology and the conventional SS topology was constructed.

The practical parameters employed for the prototype are presented in Table 1 and

Table 3. Practical parameters of the SS topology with conventional design for comparison.

Experimental Outputs
Pout	Short	400	300	200	100	Open
VL	Short	23.46	28.25	30.01	30.81	35.1
IL	24.15	17.75	10.56	6.67	3.27	0.02
RL	0.5	1.3	2.7	4.5	9.4	2000

. The gap between the primary pad and the secondary pad was 10 mm, which is closer than the normal separation distance of EVs, resulting in a relatively high k of 0.3. The operation frequency was 85 kHz. The duty cycle of the inverter operates at 0.5.

When configuring the experimental environment, the primary capacitor of the SS topology with the conventional design method was modified to work in the ZVS region. Owing to resonance caused by primary pad inductance, the primary capacitor value of the SS topology with the conventional design method was 60.4 nF. The SS topology with the conventional design method had minimum output power, and the output power increased proportionally with resistance value owing to the CC output characteristic.

The load resistance region of the SS topology with the conventional design method was assumed to be from 0.4 Ω to 0.8 Ω as the efficiency and output characteristics must be compared in the same power range. The output current of the SS topology with the conventional design method was determined by the input voltage, primary pad inductance, and secondary pad inductance. To compare efficiency at the same output voltage and current, the operation frequency and duty cycle of the inverter must be controlled. Therefore, in this experiment, only the same duty, switching frequency, input voltage, and rated output power were compared. Moreover, in order to compare the efficiency of the same circuit structure, the SS topology with the conventional design method experiment was conducted without adding a BM converter.

4.2. Experimental Result 1: Verification of Output Characteristic

Figure 8 shows the prototype IPT system manufactured for actual experimental verification. Figure 9a–c show the experimental waveforms of modes 1, 2, and 3 mentioned in Section 3, respectively. In short-circuit experiments, a short resistance with a value of 0.46 Ω was used. Figure 9b shows that mode 2 can demonstrate, based on the electric load, that the resistance is 2000 Ω with output voltage limitation. The maximum current and voltage were almost equal to the theoretical calculations, as illustrated in Figure 9a. Figure 9a,b show that the SS topology with the proposed design method can be verified to demonstrate self-limitation without any other control system or components. The measured short-current in Figure 9a is 24.1 A, which was equal to the value calculated using (18). The measured output voltage in Figure 9b was 35.1 V, which was equal to the value calculated using (17).

As shown in Figure 9, the SS topology with the proposed design method achieved ZVS in all the ranges, thus reducing switching loss.

Table 4. Result of prototype (Charging and fault) experiments.

Symbols	Parameters	Values
Us	DC link voltage	96 V
IL	Output load current	21.5 A
Cr	Leakage resonance capacitor	60.4 nF
RL	Load resistance	0.4–0.8 Ω

shows the results of the prototype experiments (voltage and current in the case of a short-circuit; P_o = 100, 200, 300, and 400 W; and an open-circuit). The short-circuit currents were measured by connecting a short resistance.

Figure 10a–c show waveforms from major charging to short-circuit, from major charging to open-circuit, and from short-circuit to open-circuit, respectively. Experimental results were almost consistent with the output equation theories specified in Section 3. Figure 10 shows that the SS topology with the proposed design method prevented overcurrent and overvoltage in dynamic short-circuit and open-circuit, respectively.

4.3. Experimental Result 2: Comparison of Output Characteristics and Efficiency with the Conventional Design Method

Figure 11a,b show the experimental waveform of the SS topology with conventional design. As illustrated in Figure 11, the output current is independent of the load resistance value, and the input current waveform of the conventional SS topology design has a zero-phase angle.

Figure 12 shows the efficiency of the SS topology with the conventional design method and the proposed design method, which were measured using the power analyzer PW6001 from HIOKI. Because of the CC characteristics (minimum output resistance is 0.4 Ω), the SS topology with the conventional design method was measured from 200 W to 400 W. The maximum efficiency of the SS topology with the proposed design method was 89.6% at 350 W. The maximum efficiency of the SS topology with the conventional design method was 87.1%. Owing to the current on the secondary side, the copper loss of the SS topology with the conventional design method was higher than with the proposed design method.

Figure 13 shows a graph of the loss ratio at full load for the two topologies compared experimentally. As the output power characteristics of the SS topology with the proposed design method were different at full load, it shows that the loss values were lower than those of the SS topology with the conventional design method in all sections.

Figure 14 shows a graph of the output characteristics. The x-axis of the graph consisted of a log scale, from short-circuit state to open-circuit state, verifying the theoretical analysis shown in Figure 7. As the resistance increased, the output load voltage almost converged with the designed value obtained by (19). When the secondary side was shorted, the current was limited to the maximum designed value.

5. Conclusions

In this study, a novel WPT system with self-limitation was proposed. In contrast to the conventional design method, which resonates with the self-inductance of a series on the primary and secondary sides, the proposed design method resonates with a leakage inductance on the primary side. Owing to the partial primary resonance, the proposed topology reached ZVS in all load ranges. The output characteristics of the load were analyzed. Under a short-circuit load, the output current converged to the limit, and under an open-circuit load, the output voltage converged to the limit. A prototype was constructed, and the experimental results validated the theoretical analysis. The system delivered approximately 400 W. Under the short-circuit condition, the output current was limited to 24.1 A. Under the open-circuit condition, the output voltage was limited to 35.1 V. Experiment results confirmed that the proposed design method showed reasonable performance in safety and efficiency. Output characteristics of the proposed design method can be calculated and designed for short-circuit current and open-circuit voltage by considering pad inductance, input voltage, and coupling coefficient. The proposed design method can be applied to low-cost WPT charging systems while ensuring safety and efficiency.