A Novel Three-Phase Switched-Capacitor Five-Level Multilevel Inverter with Reduced Components and Self-Balancing Ability

Abstract

This paper proposes a step-up 3-Ф switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology’s advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (V_DC), whereas the remaining switches experienced peak output voltage (2V_DC) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter’s theoretical justifications and real-time performance.

1. Introduction

In recent years, research has focused on renewable energy sources in order to conserve conventional energy resources and avoid global warming and climate change. Renewable energy sources, such as photovoltaic, windmills, and ocean, are the future of the energy system and a true solution to the world’s energy concerns, since they have a significant factor in technological and economic advancement and prosperity. This renewable energy source is one of the most promising long-term energy sources [1,2]. Inverters, which use DC-to-AC power conversion techniques, are used to generate, transmit, distribute, and utilize electric power. After considering the shape of the output voltage waveform, inverters are classed as two-level, three-level, PWM inverters, and multilevel inverters (MLIs). MLI has a major benefit over other inverters due to its lower dv/dt stress, less electromagnetic interference, enhanced power quality, and increased efficiency. MLI topologies, such as the neutral point clamped (NPC), the flying capacitor (FC), and the cascaded H-bridge (CHB),are some of the most common and classic topologies. These topologies have been used extensively in a wide variety of applications in energy storage and electrical conversion systems. NPC and FC inverters are responsible for the introduction of the balanced charging problem of DC link capacitors. In order to generate higherlevel output, the CHB design necessitates the utilization of a significant number of discrete DC voltage sources. In addition to this, each of these traditional topologies calls for an increasing quantity of semiconductor components in proportion to the number of output levels. Because of these factors, the reduction in semiconductor components as well as passive parts has become a key priority. This lessens the size and weight of the entire system, as well as the conduction and switching losses, and increases the efficiency of the system overall [3,4]. In contrast to NPC, FC, CHB, and MMC, which have been commercialized in medium- and high-voltage applications, SC-based MLIs (SCMLIs) have primarily been developed for low/high voltage applications because they have the advantages of voltage-boosting capability as well as the voltages of self-balanced capacitors. As a result, the switched-capacitor (SC) architecture, which has gained increased attention from researchers in recent years to improve input voltage, eliminate switching components, and lower the requirements of DC sources, is the greatest invention. Therefore, researchers havestarted focusing on switched-capacitor multilevel inverter (SC-MLI) topologies. These SCMLIs are categorized as single-stage or two-stage topologies.

A single-stage SCMLI generates a bipolar waveform, and as a result, it offers the opportunity to incorporate power switches that require fewer PIVs, despite the fact that the total number of power switches across all levels is relatively high.As an illustration, the SCMLI that was proposed in ref. [5] makes use of switches with PIV, which is restricted to the input voltage, but it provides a waveform with a low resolution and a low voltage gain. It synthesizes seven levels with many switching components. A self-balanced MLI topology is presented in this paper to achieve the lowest possible TSV and PIV for switches that have the capability of staircase multilevel bipolar voltage generation. This type of SCMLI is also quite popular. It is developed by inserting an SC-based circuit. By doing away with the end-side H-bridge inverter, the suggested construction ensures that every component can tolerate voltage stress, which is equivalent to the input DC voltage [6,7]. Both topologies exhibit peak inverse voltage (PIV) within the supply voltage but employ more switches. A single-stage eight-switch SCMLI is proposed in ref. [8], which results five different levels at its output terminal. Despite this, it has the lowest voltage gain, and only a few of its switches are able to sustain high-voltage stress.

During the first stage of a two-stage SCMLI, a unipolar multilevel waveform is generated, and then, an H-bridge (or an equivalent) is used to unfold it into a bipolar waveform. The amplitude of the output voltage causes significant voltage stress, which is felt by these H-bridge switches for high-voltage AC power supplies.The structures that are suggested in refs. [9,10] are examples of topologies that have two stages. The SCMLI structure that was proposed in ref. [9] is an easily expandable one; however, it has a very large component count, and it provides a modest voltage gain while exhibiting a high CF.

For instance, the series/parallel SCMLI that was described by Hinago et al. [10] is capable of producing 2n + 3 different levels of ac output voltage, where n is the number of SC cells, and each level is comparable to the dc input voltage. In addition, the voltages of the capacitors in this SCMLI are automatically adjusted without the use of any additional balancing circuits or control algorithms. Moreover, it has large TSV and switching components.

A seven-level boost-ANPC inverter with eight switches is the subject of investigation in ref. [11], where it is abbreviated as 7L-Boost-ANPC. Compared to the typical multilevel inverter family, the dclink voltage need is lowered byhalf, and both the active and passive components can be scaled back for generalpurpose applications (such as rolling mills, fans, pumps, marine appliances, mining, traction, and grid-connected renewable energy, etc.). An ANPC 7L self-voltage balancing inverter (7L-SVBI) has a high gain and places low voltage stress on the switches. Despite this, they still necessitate a great deal of both active and passive components, in addition to a larger dc link voltage, which is presented in ref. [12]. The input voltage can be increased using the two-stage topology described in refs. [12,13]. These topologies, however, include HB, which increases voltage stress and switching components.

A three-phase active neutral point clamped topology has been devised in recent years [14,15,16]. The first attempt to increase the voltage gain of a typical seven-level ANPC by 1.5 was madeby the author in ref. [14]. This was accomplished by suitably integrating a floating capacitor. It is common knowledge that two-stage boosting MLIs, which are excellent choices for photovoltaic power plants, are susceptible to damage as a result of the high voltage stress that is placed on the switches of the second stage. Single-stage boosting MLI, which requires a reduced number of switches, diodes, and capacitors, was proposed in ref. [15] for use in applications related to renewable power generation. For the generation of five different voltage levels, it onlyneeds a single capacitor and nine switches. Additionally, it lowers the voltage stress, which is placed on the switches.Researchers are investigating a novel six-switch five-level boost-ANPC inverter (5L-Boost-ANPC) for generalpurpose applications (such as rolling mills, fans, pumps, marine appliances, mining, tractions, and most notably, grid-connected renewable energy, etc.), which reduces the dc link voltage requirement to half of conventional 5L-NPC and 5L-FC family, as well as reducing the number of active and passive components [16]. In ref. [17], an MLI with five levels and grid connectivity is introduced. A shunt active filter is built to keep the system’s actual power flow unimpeded.Moreover, the topology has an advantage in terms of ability enhancement.A three-phase hybrid cascaded modular multilevel inverter topology is presented in ref. [18]. Because of the benefits offered by the topology, the number of power switches, losses, installation space, voltage stress, and cost of the converter are all reduced. It enables transformerless operation for renewable energy environments, such as photovoltaic (PV) systems connected to a microgrid system, which optimizes power quality and improves reliability. In ref. [19], a single-phase 13-level switching-capacitor multilevel boost inverter (SCMLBI) with fewer switches and a voltage boost gain of six times is given. The primary objective of this research is to demonstate a single DC source SCMLBI topology, which, when coupled with an appropriate sinusoidal pulse modulation (SPWM) approach, is capable of producing an AC output voltage that has a low level of harmonic distortion.

The SCMLI given in refs. [20,21] requires more switching to generate five levels. This topology has a smaller part count, and a higherlevel output can be achieved by cascading upgraded HB modules. There is only one isolated DC power source employed. Although an asymmetrical design generates more levels than a symmetrical operating mode, the easily available DC sources of varying magnitudes remain a worry even though an asymmetrical configuration generates more levels. Therefore, single-phase topologies are being advocated, since they are capable of functioning in either arrangement. Ref. [22] outlines an asymmetrical structure, which has a lower source count than previous models. These single-phase topologies can also be run in three-phase mode. Compared with traditional topologies, the switch count and gate drive count of the three-phase hybrid cascaded modular multilevel inverter (HCMMLI), which is described in ref. [18], are both significantly decreased. In ref. [23], there is a presentation of a single DC source hybrid seven-level three-phase architecture, which uses a hybrid control technique to increase efficiency. Ref. [24] presents a proposal for a three-phase symmetrical architecture, which uses fewer components. An improved control approach for renewable energy resources in microgrids that are gridconnected via voltage-sourced converters (VSCs) is provided in refs. [25,26,27,28]. Ahigh-gain SC capacitor scheme with 13 stages is described in ref. [29]. One of the main problems with this design is that one capacitor is being utilized to charge another capacitor.

To address the aforementioned issues, this study offers a new three-phase MLI design, which possesses minimum switching components, reduced voltage stress, and the ability to step up the input voltage.

The assets of the proposed topology (PT) are as follows:

• The topology has voltage boosting capability.
• Capacitors are inherently self–balanced.
• Reduced voltage stress across the switching components.
• It requires only an isolated DC source for the generation of five-level (line-to-line) voltages.
• The minimum number of switches is ensuredfor any level of generation.
• It can be operated for a wide range of power factors.
• The suggested topology provides a lower TSV value, lowering overall costs.

The following structure guides this paper. Section 2 discusses the specifics of the design, the underlying operating principle, and the recommended range of capacitance values. Section 3 discusses the modulation strategy of the proposed topology in detail. An evaluation of the power losses in the SC topology is presented in Section 4. Section 5 provides a comparative analysis with state-of-the-art topology to demonstrate its usefulness. Section 6 presents the results of the simulations and the experiments. Finally, Section 7 discusses the conclusion part of the proposed topology.

2. Proposed Single Source Three-Phase Topology

2.1. Explanation of the SCMLI Topology

The PT five-level 3-Ф SCMLI is displayed in Figure 1. Each phase leg of this inverter possesses four power semiconductor switches, one capacitor, and one power diode. To prevent the supply voltage from being accidentally shorted out, the SC cell’s switches operate in a complimentary manner. The supply voltage (V_DC) is common to all phases $X$ ($X\in$ phase R, phase Y, phase B). The proposed topology synthesizes five levels of the line-to-line voltage (0, ±1V_DC ± 2V_DC). All switches’ voltage stresses are well below the supply voltage, except for $S_{X4}$, where it is twice as high. The simple switching pattern for various modes of activity for phase $R$ is introduced in

Table 1. Different switching modes and their corresponding positive pole voltages for phase leg “R”.

Switching Mode	Active Switch				$\mathbf{Pole} \mathbf{Voltage} \mathbf{per} \mathbf{Phase} \mathbf{Leg} {\mathit{v}}_{\mathit{R}\mathit{n}}\left(\mathit{t}\right)$
	SR1	SR2	SR3	SR4
${\delta }_1$	0	1	0	1	0
${\delta }_2$	0	1	1	0	+1$V_{DC}$
${\delta }_3$	1	0	1	0	+2$V_{DC}$

. Switches’ on/off states are represented by the numbers 0 and 1.

2.2. Working Principle

The operating principle of the PT can be depicted with the assistance of per phase leg (say phase R), as shown in Figure 2. Since each phase leg of the PT is identical, the comparative analysis for the other two phases can be extended. As a result, the idea of using onlyone phase leg is considered to be more illuminating. The activity of the single-phase leg is clarified in the accompanying mode. In every mode of activity, the inverter synthesizes a specific voltage level with the assistance of the desired switching combination mentioned in Table 1. The sequence of the voltage generation path and charging path of the capacitor are set apart by dotted blue and green lines separately.

$$\mathrm{Mode} {\delta }_1: v_{Rn}\left(t\right)=0$$

In this mode of activity, the controlled switches S_R2, and S_R4 are in on state, and S_R1, _and S_R3 are in off condition to accomplish zero volts across the load terminals. The capacitor (C_R) is energized to a voltage of magnitude V_DC through the forward-biased diode (D_R) because of the activation of switch S_R2. The leading way for pole voltage is shown in Figure 3a.

$$\mathrm{Mode} {\delta }_2: v_{Rn}\left(t\right)=+1V_{DC}$$

To achieve the targeted output voltage V_DC, this mode of operation simultaneously activates the switches S_R2 and S_R3 while simultaneously deactivating the switches S_R4 and S_R1. Due to the activation of the switch S_R2, the capacitor is connected in shunt with the isolated dc voltage source and energized to a voltage of magnitude V_DC. The leading way for pole voltage is shown in Figure 3b.

$$\mathrm{Mode} {\delta }_3: v_{Rn}\left(t\right)=+2V_{DC}$$

This voltage is achieved by simultaneously activating S_R1 and S_R3, and deactivating S_R2, and S_R4. Due to the activation of the switch S_R1, the capacitor (C_R) is placed in cascade to the load through switch S_R3 and releases its stored energy to the output. Hence, the output level becomes 2V_DC. The leading way for pole voltage is shown in Figure 3c.

2.3. Capacitance Design and Self-Balancing

The capacitor ($C_X$) is used as a dc voltage source to provide the various output levels needed by the proposed SCMLI. Discharging to loads causes a decrease in their voltages.The capacitance of a capacitor typically decreases as the voltage ripple across it increases. Therefore, calculating the voltage ripple across the capacitor is the first task to complete in SC design. The voltage ripple can be computed as follows for a completely passive load, which represents the worstcase scenario because there is no load current flowing back to the capacitors [10].

$$\mathsf{\Delta }{V}_{CR}=\frac{1}{\omega C_R}{{\displaystyle \int }}_{t_a}^{t_b}\frac{2V_{DC}}{R}dt$$

(1)

The capacitor design in an SCMLI is a significant factorto avoid undercharging andvoltage ripples. Consequently, the ideal estimation of capacitance is chosen in such a way, so as to fulfill the following condition [6]:

$$C_{optimum}\ge \frac{\mathsf{\Delta }QC}{\mathsf{\Delta }{V}_{CX}}$$

(2)

where $\mathsf{\Delta }$Q_C represents the amount of discharge from the capacitor, K is the percentage of extremely tolerable voltage ripple, and V_DC is the supply voltage.

The stability of the capacitor relies on the magnitude of the load current, power factor, and longest releasing period of the capacitor. Therefore, the maximum discharge amount of capacitors is obtained as: Therefore, the releasemeasure of charge (∆Q_C) can be communicated as

$$\mathsf{\Delta }{Q}_C{{\displaystyle \int }}_{t_a}^{t_b}{I}_{peak}sin\left(2\pi ft-\phi \right)dt$$

(3)

where $I_{peak}$ is the maximum current flowing through the load, $f$ is the modulated wave frequency, and $\phi$ is the phase angle difference between voltage and current; The longest discharging times for each capacitor is (t_a − t_b).

This discharging period can be calculated from Figure 3b as follows [6]:

$$t_a=\frac{{sin}^{-1}\left(\frac{1}{2}\right)}{ 2\pi f}$$

(4)

$$t_b=\frac{\pi -{sin}^{-1}\left(\frac{1}{2}\right)}{2\pi f}$$

(5)

Taking into account the voltage ripple, the value of capacitance for C_R1 is

$$C_R\ge \frac{{{\displaystyle \int }}_{t_a}^{t_b}{I}_{peak}sin\left(2\pi ft-\phi \right)dt}{\mathsf{\Delta }{V}_{CR}}$$

(6)

The other capacitors ($C_Y$ and $C_B$) can be treated in the same way.

The capacitor C_R ischarged to V_DC during the voltage level of zero and +1V_DC by activating the switch S_R2 through the power diode D_R, as portrayed in Figure 3a,b. The capacitor delivers its stored energy to load at the voltage level +2V_DC shown in Figure 3c. This charging and releasing of a sequence of capacitors over every cycle keep it self-balanced automatically.

3. Modulation Scheme

The level shift sinusoidal pulse width modulation (LS-SPWM) control strategy is executed. A continuous comparison is made between two carrier signals and a referencesignal U(t) at 50 Hz with a modulation index of M = 0.95. Carrier signals above the zero reference axis are labeled C₁(t), and those below it are labeled C₂(t) for each phase leg X (t). As U(t) becomes more significant than the carrier signal, it produces a “1” above the zero reference axis and a “0” below. Under the zero reference axis, a reading of “0” is obtained when the reference signal is more dominant than the carrier signal, while a reading of “−1” is obtained otherwise. All of the signals from the comparator are put together to form a single signal a$\left(t\right).$ With the help of the lock-up Table 1, next, compare this aggregated signal to the fixed levels in order to obtained the gate signals. Figure 4a depicts the circuit design for the switching scheme for phase leg “X”, and Figure 4b shows the modulated signal, carrier signal, and output voltage.

4. Loss Analysis

Different kinds of losses take place in the PT, such as (i) conduction losses, (ii) switching losses, (iii) blocking state or off-state losses, and (iv) voltage ripple losses. At any rate, the blocking state losses are very small because, during the off state of the switches, the leakage current is exceptionally little. Hence, it will be negligibled [9].

4.1. Conduction Losses

When the switching components are in the conduction path for conveying their particular voltage level, conduction losses arise owing to the ohmic losses associated with the dynamic resistance of the switch. Therefore, conduction losses appear due to the power switch (R_S) and diode (R_D) are expressed mathematically as follows [7]:

$$P_C=\left[P_{C, S}+P_{C, D}\right]$$

(7)

where conduction losses ($P_C$) due to semiconductor switches ($P_{C,sw}$) and power diodes ($P_{C,D}$) an be expressed as:

$$P_{C, sw}=V_S{I}_{S,avg}+I_{S,rms}^2{R}_S$$

(8)

$$P_{C, D}=V_D{I}_{D,avg}+I_{D,rms}^2{R}_D$$

(9)

where $V_S$,$V_D$ are the conduction state voltage drops of the switch and diode respectively.

$I_{S,avg}$ = average current flowing through a switches.

$R_S$, $R_D$ = on-state resistance of the switch and diode respectively.

$I_{S,rms}$, $I_{D,avg}$ = root-mean-square and average current through the switch and diode respectively.

4.2. Ripple Losses

The voltage gap between the supply voltage and the voltage across capacitors is defined as a voltage ripple. The capacitor voltage ripple is expressed as [10]

$$\mathsf{\Delta }{V}_{C_x}=\frac{1}{C_x}{{\displaystyle \int }}_{t_a}^{t_b}{I}_{C_x}\left(t\right)dt$$

(10)

where $I_{C_x}\left(t\right)$ is theinstantaneous current passing through the capacitor.

$t_a$ and $t_b$ is the discharging period.

Thus, the ripple loss ($P_{rip}$) can bestatedas [9]

$$P_{rip}=\frac{f_{sw}}{2}{\displaystyle \sum }_{x=1}^n{C}_x\mathsf{\Delta }{V}_{C_x}^2$$

(11)

4.3. Switching Losses

Switching losses, caused by the overlapping of current and voltage during the switching state change, can be calculated [9,20]. During turn-on, the power loss is given by

$$P_{S,i,ton}=\frac{1}{6}(f_{sw}{V}_{sw,i}{I}_{on, i}{t}_{on})$$

(12)

Similarly, the switching loss due to turn-off can be calculated as

$$P_{SW,i,toff}=\frac{1}{6}(f_{sw}{V}_{sw,i}{I}_{off, i}{t}_{off})$$

(13)

where $I_{on, i}$ and $I_{off, i}$ signify the current flowing through the switches after the ith switch is turned on and before it is turned off, respectively. $f_{sw, }$ is the switching frequency, and $V_{sw}$ is the reverse voltage across the switch.

Thus, the total switching losses ($P_{sw}$) ofthe PT are calculated as follows:

$$P_{sw}={\displaystyle \sum }_{n=1}^5{\displaystyle \sum }_{i=1}^{12}\left(P_{sw,i,ton}+P_{sw,i,toff}\right)$$

(14)

As a result, the PT’s overall losses are composed of conduction and switching losses, as well as voltage ripple losses.

$$P_{total loss}=P_c+P_{sw}+P_{rip}$$

(15)

The PT’s overall efficiency can be calculated as follows:

$$\%\mathrm{Efficiency}\left(\eta \right)=(P_{output}/P_{input})\times 100$$

(16)

$$\%\eta =\left(\frac{P_{output}}{P_{output}+P_{total loss}}\right)\times 100$$

(17)

where $P_{output \mathrm{and} }{P}_{input}$ represent the power output and input of the proposed inverter, respectively.

5. Comparative Assessment with the Existing Topologies

This section includes a comparison study to emphasize the importance of PT. The PT is compared to various recently proposed inverter architectures in terms of the semiconductor switches, diodes, capacitors, gain, total voltage stress, and cost function, among other things.

Table 2. Comparative assessment for per phase leg with recent SCMLI topologies.

Topology	A	B	C	D	$\mathit{E}$	F	H	FC/L	G	CF	Losses (W)	Efficiency
[5]	7	10	-	4	1	10	8	3.14	1.5	4.57	25.44	92.4%
[7]	7	6	2	1	1	8	6	2.28	3	3.28	23.48	95.45%
[8]	5	6	2	2	1	8		2.2	2	3.6	23.67	95.23%
[12]	7	10	-	3	1	9	10	3.28	1.5	4.57	24.68	94.45%
[13]	7	9	-	3	1	6.5	8	2.87	1.5	3.78	25.89	94.76%
[14]	7	9	-	3	1	8	8	2.85	1.5	4	22.24	95.48%
[15]	5	9	-	1	1	9	9	3.8	2	5.6	22.45	95.34%
[16]	5	6	2	3	1	6	6	3.4	1	4.6	18.69	96.23%
[18]	5	10	-	-	2	14	9	3.8	1	13.2	25.25	92.14%
[P]	5	4	1	1	1	6	4	2	2	3.2	14.21	96.7%
$\mathrm{A}: N_L$$, \mathrm{B}: N_{SW}$$, \mathrm{C}: N_D$$, \mathrm{D}: N_C$$, \mathrm{E}: N_S$$, \mathrm{F}: \mathrm{TSV}, \mathrm{G}: \mathrm{Gain}, \mathrm{H}: N_{dri}$

compares the PTto existing inverter topologies in terms of the single-phase leg. However, the components necessary to build a three-phase architecture are three times those required for a single-phase leg. The component count per level $(F_{C/L})$ can be mathematically written as

$$F_{C/L}=\frac{N_C+N_{Sw}+N_D+N_S+N_{dri}}{N_L}$$

(18)

where $N_L$, $N_C$, $N_D$, $N_{Sw}$, and $N_S$ are the number of levels, capacitors, diodes, switches, and the number of isolated DC sources per phase, respectively. Additionally, the cost function will decide the overall cost of the PT. The weight factor (α) for the PT is set to one because the switching components and TSV are both valued equally.

The cost factor is defined by Equation (18) as

$$CF=\frac{\left[N_{SW}+N_C+N_D+N_{dri}+\alpha TSV\right]\times N_S}{N_L}$$

(19)

The PT has a smaller CF and $F_{C/L}$ than prior topologies. The proposed topology is compared with other existing topologies for TSV and in references [16,18] are better as compared to proposed topology and the proposed topology is better while comparing all other topologies in Table 2 for specific levels, i.e., five levels. Although topologies [7,8,22] share the same gain factor, they have a higher component count per level factor and cost function. As a result, PT employs the least number of components, resulting in a more compact inverter. As a result, the weight and energy consumption of the PTare decreased. Additionally, it lowers equipment costs by lowering the TSV and provides the lowest possible voltage and current THD performance. As a result, the proposed inverter beats its competitors in every way.In comparison to other existing topologies, the PT’s overall efficiency is superior.

Table 3. Cost analysis of the proposed topology compared with the existing topologies.

C	PN	R	UP	Topology
				[7]	[5]	[12]	[13]	[14]	[16]	[18]	[P]
MOSFET *	IRFP240PBF	100 V, 23 A	2.2	-	6	6	6	6	-	-	-
	IRFP350PBF	200 V, 20 A	2.68	6	24	21	21	24	18	18	9
	IRFP21N60LPBF	400 V, 16 A	3.48	12	-	-		-	-	12	3
	IRFP9140NPBF	600 V, 21 A	8.16		-	-		-	-	-	-
Diode *	VS-20ETF02-M3	200 V, 20 A	3.68	3	-	-		-	6	-	3
Capacitor	23M252F200BH1H1	200 V, 2500 μF	23.61	6	12	9	9	9	9	-	3
Gate Driver	IR2110	-	1.8	18	27	24	24	27	18	27	12
Total Cost (USD)				240.6	409.4	325.6	325.6	338.6	315.2	138.6	138.03
C = Components, R = Rating, UP = Unit Price (USD), PN = Part Number

* www.digikey.com, www.galco.com (accessed on 20 December 2022).

presents a cost comparison, which was evaluated to help further clarify the unique benefits of the proposed topology. All topologies were given the same voltage parameters for the sake of cost analysis. In addition, the cost analysis gave equal weight to all factors. The costs for alternative topologies are listed in Table 3, and the proposed topology is shown to have the lowest overall component costs.

6. Simulated and Experimental Results

6.1. Simulated Results

To validate the theoretical notion, the PT’s modeling and simulation results were taken using MATLAB/Simulink software. The modeling and experimental factors are enumerated in

Table 4. Simulation and experimental results: Useful parameters.

Parameter	Specification
Supply voltage (VDC)	100 V
Supply frequency	50 Hz
Carrier frequency	2 kHz
Capacitors (CR = CY = CB)	1100 μF
Load	R = 40 Ω, L = 30 mH
Switch	IRFP460 MOSFETs
Diodes	VS-20ETF02-M3
Controller	dSPACE DS1104
Modulation index	0.95

.

Figure 5 illustrates the time-varying outcomes of line voltages and pole voltages for a PT. The source configuration is held constant at Vdc = 100 V, while the modulation index is held at M = 0.95. Each phase leg’s pole voltage output is depicted in Figure 5a. The maximum voltage at the poles is 200 V. Figure 5b–d show the line voltages V_RY, V_YB, V_BR, line current (I_R, I_Y, I_B), and the capacitors’ voltages V_CR, V_CY, and V_CB when the load isvaried. This dynamic load current change is indicative of relatively stable load voltages. When the load current rises, the voltage ripples of the capacitors also grow.Figure 5d illustratesthat the capacitor voltage for phase R is self-balanced with small voltage ripples when the load varies suddenly. As can be seen in Figure 5d, the voltage across the capacitors tends to stabilize at its nominal value, V_CX = 100 V. This equilibrium is maintained in the presence of varying loads. As can be seen in Figure 5e, the blocking voltages for S_R1, S_R2, and S_R3 are all 100 V DC. The stress voltages applied to S_R4 should also total 200 V. Each leg switch has a stress voltage or blocking voltage of 500 V.

IRFP460 MOSFETs were utilizedas controlled switches on the PLECS SIMULINK platform, and the IRFP460 datasheet was brought in to quantify the power loss. This is seen in Figure 5f, which depicts the power loss distribution under full load.

6.2. Experimental Results

A prototype for hardware execution consists of twelve discrete power switches (IRFP460 MOSFETs and accompanying gate drivers circuit), three capacitors, three auxiliary power diodes, and one DC supply. The experimental configuration of the five-level prototype is depicted in Figure 6. Table 4, on the other hand, shows the components utilized to build the prototype. A controlled DC power supply is used as an isolated DC source for feeding a PT MLI topology. The experimental results are depicted in Figure 7.

The results of the simulation and the experiment are comparable in a satisfactory manner. The voltages at the output poles are depicted in Figure 7a. There are three different levels of voltages at the pole. These levels are: +200 V, +100 V, and 0 V. Figure 7b shows the line voltages that were measured. It is clear to see that the generated line voltage is composed of five distinct levels. The voltages are as follows: –200 V, –100 V, 0 V, 100 V, and +200 V. The variation of the load current due to change in loading is demonstrated in Figure 7c. Figure 7c depicts the phase currents in their entirety. The maximum value that the phase current can reach upto 3.5 A. Figure 7d illustrates the voltages measured across the capacitors. The voltage magnitudes of the produced capacitors are as follows: V_C1 = 100 V. Despite the sudden shift in load, the line voltage remained stable because the capacitors automatically balanced themselves. All the blocking voltages for S_R1, S_R2, and S_R3 are at 100 V DC. Additionally, S_R4 needs to be subjected to a total of 200 V in stress voltages. The blocking voltage of phase leg R is depicted in Figure 7e. Figure 7f shows the per-phase voltage and current under a steady state. It is worth noting that the experimental results closely match the simulated results. The efficiency at different powers andvoltages is shown in Figure 7g. The efficiency of the inverter is lowest at lower power values, rising to a maximum of around 300 W and then gradually falling back down again.

7. Conclusions

This article discusses the novel 3-SCMLI with explanatory notes. The proposed topology uses fewer switching components to achieve the three-phase system. The operation concept and modulation approach of the PT for a single-phase leg are demonstrated in detail, together with circuit schematics and waveforms. Compared to more traditional MLI topologies, the suggested architecture offers the lowest voltage stress across capacitors and switches. The number of sensors required and the complexity of the control system can be significantly reduced as a result of this self-balanced capacitor voltage. The suggested five-level SC-MLI topology is mathematically modeled, with loss and efficiency analysis. The profiles of pole voltage, line voltage, and output current under dynamic loading conditions are shown. The PT’s performance is proven through simulated and experimental investigation for a variety of output voltages and capacitor counts. The suggested five-level SC-MLI topology is mathematically modeled, with loss and efficiency analysis, and it is determined that its efficiency is adequate.