Structure and Principles of Operation of a Quaternion VLSI Multiplier

Abstract

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using $130\mathrm{nm}$ technology. The developed scripts in VHDL are available in the GitHub repository.

1. Introduction

The development of the theory and practice of data processing as well as the expansion and complexity of the range of problems being solved stimulate the use of increasingly advanced numerical systems. If complex-valued data processing was considered something exotic until quite recently, then there was no talk of the practical application of hypercomplex-valued data processing. Quaternions are being used in a wide range of scientific and engineering fields, such as deep neural networks, computer graphics and machine vision, robotics, navigation, data encoding, image and signal processing, multiresolution analysis, and graph theory (see, for example, [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21]). It should be noted, however, that hypercomplex-valued arithmetic operations ultimately still come down to performing elementary operations on real numbers.

In the case of real-valued data processing, multiplication has also always been the most time-consuming operation. To reduce the computation time, developers sought to elaborate algorithms with a minimum number of multiplications. Another solution to the problem of accelerating calculations was the introduction of hardware multipliers into the data processing system. This is how hardware multipliers appeared: first as separate chips, and then built into the chip. Since even the common multiplication of two complex numbers necessitates four multiplications and two additions of real numbers, it is the most time-consuming operation for processing complex-valued data. In the case of hypercomplex numerical systems, the problem of multiplication implementation time is even more acute. This is because 16 multiplications and 12 additions of real numbers are needed to complete a single multiplication of two quaternions. A lot has been written about hardware real-valued multipliers—it has already become a classic [22,23,24]. A lot has also been written about hardware complex number multipliers [25,26,27,28,29,30,31,32,33,34,35,36,37]. But only a few works have been written about hardware multipliers of hypercomplex numbers, particularly quaternions [38,39]. In addition, as an analysis of known solutions has shown, they do not use all the possibilities of computer optimization. We want to fill this gap.

2. Short Background

A quaternion $q\in \mathcal{H}$ is a hypercomplex number which can be presented as [2]:

$$q=q_0+i{q}_1+j{q}_2+k{q}_3,$$

(1)

where $\mathcal{H}$ is a four-dimensional vector space over the real numbers $q_0,q_1,q_2,$ and $q_3\in \mathcal{R}$, and $i,j,$ and k are basic imaginary units satisfying the following multiplication rules

$$jk=i,ki=j,ji=-k,kj=-i,ik=-j.$$

(2)

Suppose we need to compute the product of two quaternions a and b:

$$c=ab,$$

(3)

where

$$\begin{array}{ccc}\hfill a& =& \hfill a_0+a_{1}i+a_{2}j+a_{3}k,\hfill \\ \hfill b& =& \hfill b_0+b_{1}i+b_{2}j+b_{3}k,\hfill \\ \hfill c& =& \hfill c_0+c_{1}i+c_{2}j+c_{3}k.\hfill \end{array}$$

(4)

$$\begin{array}{ccc}\hfill ab& =& (a_0+a_{1}i+a_{2}j+a_{3}k)(b_0+b_{1}i+b_{2}j+b_{3}k)\hfill \\ & =& a_0{b}_0-a_1{b}_1-a_2{b}_2-a_3{b}_3\hfill \\ & +& (a_0{b}_1+a_1{b}_0+a_2{b}_3-a_3{b}_2)i\hfill \\ & +& (a_0{b}_2+a_2{b}_0+a_3{b}_1-a_1{b}_3)j\hfill \\ & +& (a_0{b}_3+a_3{b}_0+a_1{b}_2-a_2{b}_1)k.\hfill \end{array}$$

(5)

It is well known that the quaternion multiplication can be represented as a matrix–vector product:

$${\mathbf{y}}_4={\mathbf{B}}_4{\mathbf{x}}_4,$$

(6)

where

$$\begin{array}{ccc}\hfill {\mathbf{B}}_4& =& \hfill \left[\begin{array}{cccc}\hfill b_0& \hfill -b_1& \hfill -b_2& \hfill -b_3\\ \hfill b_1& \hfill b_0& \hfill b_3& \hfill -b_2\\ \hfill b_2& \hfill -b_3& \hfill b_0& \hfill b_1\\ \hfill b_3& \hfill b_2& \hfill -b_1& \hfill b_0\end{array}\right],\hfill \\ \hfill {\mathbf{y}}_4& =& \hfill {[y_0,y_1,y_2,y_3]}^T,\left\{y_m\right\}=\left\{c_m\right\},m=0,1,2,3,\hfill \\ \hfill {\mathbf{x}}_4& =& \hfill {[x_0,x_1,x_2,x_3]}^T,\left\{x_m\right\}=\left\{a_m\right\},m=0,1,2,3.\hfill \end{array}$$

Calculating this matrix–vector product directly calls for 16 real multiplications and 12 real additions. If, when implementing matrix–vector multiplications in hardware, to achieve maximum performance, we use the paradigm of the maximum parallelization of calculations, then 16 multipliers and four four-input adders will be required. Our goal is to reduce the required number of multipliers while maintaining performance. Below we will show one way to do this. The proposed approach is based on the idea described in [40].

3. Algorithmic Aspect

Let us multiply the first row of ${\mathbf{B}}_4$ by (−1). Then, we obtain   

$$\begin{array}{ccc}\hfill {\widehat{\mathbf{B}}}_4& =& \hfill \left[\begin{array}{cccc}\hfill -b_0& \hfill b_1& \hfill b_2& \hfill b_3\\ \hfill b_1& \hfill b_0& \hfill b_3& \hfill -b_2\\ \hfill b_2& \hfill -b_3& \hfill b_0& \hfill b_1\\ \hfill b_3& \hfill b_2& \hfill -b_1& \hfill b_0\end{array}\right].\hfill \end{array}$$

(7)

Therefore, the procedure for multiplying quaternions can be reduced to the following equivalent expression:

$$\begin{array}{cccc}\hfill \left[\begin{array}{c}\hfill -y_0\\ \hfill y_1\\ \hfill y_2\\ \hfill y_3\end{array}\right]& =& \hfill \left[\begin{array}{cccc}\hfill -b_0& \hfill b_1& \hfill b_2& \hfill b_3\\ \hfill b_1& \hfill b_0& \hfill b_3& \hfill -b_2\\ \hfill b_2& \hfill -b_3& \hfill b_0& \hfill b_1\\ \hfill b_3& \hfill b_2& \hfill -b_1& \hfill b_0\end{array}\right]\hfill & \left[\begin{array}{c}\hfill x_0\\ \hfill x_1\\ \hfill x_2\\ \hfill x_3\end{array}\right].\\ \hfill \underbrace{\hspace{0.25em}}& & \hfill \underbrace{\hspace{0.25em}}\hfill & \\ \hfill {\widehat{\mathbf{y}}}_4& & \hfill {\widehat{\mathbf{B}}}_4\hfill & \end{array}$$

(8)

This modification will eventually result in a reduction in the final algorithm’s computational complexity. Through this transformation, the matrix that has been altered in this way is represented as the algebraic sum of a block-symmetric Toeplitz-type matrix ${\overline{\mathbf{B}}}_4$ and a sparse matrix ${\underline{\mathbf{B}}}_4$, or a matrix with only a few non-zero elements:

$$\begin{array}{ccc}\hfill {\widehat{\mathbf{B}}}_4& =& \hfill \left[\begin{array}{cccc}\hfill b_0& \hfill b_1& \hfill b_2& \hfill b_3\\ \hfill b_1& \hfill b_0& \hfill b_3& \hfill b_2\\ \hfill b_2& \hfill b_3& \hfill b_0& \hfill b_1\\ \hfill b_3& \hfill b_2& \hfill b_1& \hfill b_0\end{array}\right]-2\left[\begin{array}{cccc}\hfill b_0& & & \\ & & & \hfill b_2\\ & \hfill b_3& & \\ & & \hfill b_1& \end{array}\right],\hfill \\ & & \hfill \underbrace{\hspace{0.25em}}\underbrace{\hspace{0.25em}}\hfill \\ & & {\overline{\mathbf{B}}}_4{\underline{\mathbf{B}}}_4\hfill \end{array}$$

(9)

$${\widehat{\mathbf{y}}}_4=({\overline{\mathbf{B}}}_4-2{\underline{\mathbf{B}}}_4){\mathbf{x}}_4={\overline{\mathbf{B}}}_4{\mathbf{x}}_4-2{\underline{\mathbf{B}}}_4{\mathbf{x}}_4.$$

(10)

Omitting mathematical derivations, we represent the multiplication of a matrix ${\overline{\mathbf{B}}}_4$ by a vector ${\mathbf{x}}_4$ in the form of the following matrix–vector procedure:

$$\begin{array}{ccc}\hfill {\overline{\mathbf{B}}}_4{\mathbf{x}}_4& =& \hfill {\mathbf{H}}_4\left({\displaystyle \frac{1}{4}}{\mathbf{D}}_4\right){\mathbf{H}}_4{\mathbf{x}}_4={\mathbf{W}}_4^{\left(0\right)}{\mathbf{W}}_4^{\left(1\right)}\left({\displaystyle \frac{1}{4}}{\mathbf{D}}_4\right){\mathbf{W}}_4^{\left(1\right)}{\mathbf{W}}_4^{\left(0\right)}{\mathbf{x}}_4,\hfill \\ & & \hfill \underbrace{\hspace{0.25em}}\underbrace{\hspace{0.25em}}\hfill \\ & & {\mathbf{H}}_4{\mathbf{H}}_4\hfill \end{array}$$

(11)

where

$$\begin{array}{ccc}\hfill {\mathbf{H}}_4& =& \hfill \left[\begin{array}{ccccc}\hfill 1& \hfill 1& |& \hfill 1& \hfill 1\\ \hfill 1& \hfill -1& |& \hfill 1& \hfill -1\\ \hfill --& \hfill --& --& \hfill --& \hfill --\\ \hfill 1& \hfill 1& |& \hfill -1& \hfill -1\\ \hfill 1& \hfill -1& |& \hfill -1& \hfill 1\end{array}\right]\hfill \end{array}$$

is the fourth-order Hadamard matrix,

$$\begin{array}{ccc}\hfill {\mathbf{D}}_4& =& \hfill diag(s_0,s_1,s_2,s_3),\hfill \end{array}$$

$$\begin{array}{ccc}\hfill {\mathbf{W}}_4^{\left(0\right)}& =& \hfill {\mathbf{H}}_2\otimes {\mathbf{I}}_2=\left[\begin{array}{ccccc}\hfill 1& & |& \hfill 1& \\ & \hfill 1& |& & \hfill 1\\ \hfill --& \hfill --& --& \hfill --& \hfill --\\ \hfill 1& & |& \hfill -1& \\ & \hfill 1& |& & \hfill -1\end{array}\right],\hfill \end{array}$$

$$\begin{array}{ccc}\hfill {\mathbf{W}}_4^{\left(1\right)}& =& \hfill {\mathbf{I}}_2\otimes {\mathbf{H}}_2=\left[\begin{array}{ccccc}\hfill 1& \hfill 1& |& \hfill 0& \hfill 0\\ \hfill 1& \hfill -1& |& \hfill 0& \hfill 0\\ \hfill --& \hfill --& --& \hfill --& \hfill --\\ \hfill 0& \hfill 0& |& \hfill 1& \hfill 1\\ \hfill 0& \hfill 0& |& \hfill 1& \hfill -1\end{array}\right],\hfill \end{array}$$

and ${\mathbf{I}}_N$ is the order N identity matrix, ${\mathbf{H}}_2=\left[\begin{array}{cc}\hfill 1& \hfill 1\\ \hfill 1& \hfill -1\end{array}\right]$ is the second-order Hadamard matrix, and ⊗, ⊕ denote the Kronecker product and direct sum of two matrices, respectively.

It is simple to verify that the entries of the matrix ${\mathbf{D}}_4=diag\left({\mathbf{d}}_4\right)$ may be computed by applying the subsequent matrix–vector procedure, which minimizes the number of real additions involved:

$${\mathbf{d}}_4={\displaystyle \frac{1}{4}}{\mathbf{H}}_4{\mathbf{b}}_4={\displaystyle \frac{1}{4}}{\mathbf{W}}_4^{\left(1\right)}{\mathbf{W}}_4^{\left(0\right)}{\mathbf{b}}_4,$$

(12)

where

$${\mathbf{d}}_4={[s_0,s_1,s_2,s_3]}^T,{\mathbf{b}}_4={[b_0,b_1,b_2,b_3]}^T.$$

(13)

Regretfully, there is no way to lessen the computational cost of the product $2{\underline{\mathbf{B}}}_4{\mathbf{x}}_4$; hence, it must be calculated directly without using any techniques. Upon integrating the computations for both matrices into a solitary process, we ultimately derive the following:

$${\mathbf{y}}_4={\mathbf{S}}_{4\times 8}({\mathbf{H}}_4\oplus {\mathbf{I}}_4){\mathbf{D}}_8({\mathbf{H}}_4\oplus {\mathbf{I}}_4){\mathbf{P}}_{8\times 4}^{\left(0\right)}{\mathbf{x}}_4,$$

(14)

$$\begin{array}{ccc}\hfill {\mathbf{P}}_{8\times 4}^{\left(0\right)}& =& \hfill {\mathbf{1}}_{2\times 1}\otimes {\mathbf{I}}_4=\left[\begin{array}{cccc}\hfill 1& & & \\ & \hfill 1& & \\ & & \hfill 1& \\ & & & \hfill 1\\ \hfill --& \hfill --& \hfill --& \hfill --\\ \hfill 1& & & \\ & \hfill 1& & \\ & & \hfill 1& \\ & & & \hfill 1\end{array}\right],{\mathbf{1}}_{2\times 1}={[1,1]}^T,\hfill \end{array}$$

$$\begin{array}{ccc}\hfill {\mathbf{S}}_{4\times 8}& =& \hfill \left[\begin{array}{ccccccccc}\hfill -1& & & & |& \hfill 1& & & \\ & \hfill 1& & & |& & \hfill -1& & \\ & & \hfill 1& & |& & & \hfill -1& \\ & & & \hfill 1& |& & & & \hfill -1\end{array}\right],\hfill \\ \hfill {\mathbf{D}}_8& =& {\displaystyle \frac{1}{4}}{\mathbf{D}}_4\oplus {\underline{\mathbf{D}}}_4,\hfill \end{array}$$

$${\underline{\mathbf{D}}}_4=diag(s_4,s_5,s_6,s_7)=diag\left(2{\underline{\mathbf{B}}}_4{\mathbf{x}}_4\right).$$

(15)

Expression (14) describes a fast algorithm for quaternion multiplication.

The data flow diagram of the processing block for calculating elements $\left\{s_m\right\}$, $m=0,1,2,3$, is depicted in Figure 1, whereas the data flow structure of the quaternion multiplication unit is shown in Figure 2. Figure 3 shows a data flow structure of the process for calculating elements $\left\{s_{m+4}\right\}$, $m=0,1,2,3$.

The data flow diagrams in this paper are left-to-right-oriented. The data transfer operations in the diagrams are represented by straight lines. Points indicate summation where lines converge. The subtraction procedure is indicated by the dotted lines. To avoid overcrowding the image, we purposefully employ the standard lines without arrows. These figures’ circles depict the process of multiplying by a number, either constant or variable, that is written inside a circle. In turn, the rectangles indicate the matrix–vector multiplications by the matrices inscribed inside rectangles.

Let us consider the data flow diagrams shown in Figure 2 and Figure 3. It can be seen that the implementation of the computations according to (12) and (14) requires only eight multiplications, 28 additions, four right shifts (multiplications by 1/4) and four left shifts (multiplications by 2). And since the left–right shift operations are very simple and do not require additional memory access, they are usually omitted when evaluating the computational complexity. Note that here we take into account the fact that the multiplication of a fourth-order Hadamard matrix by a vector requires only 8 additions instead of 12. Figure 4 shows a detailed schematic view of the matrix–vector multiplications of the corresponding vectors by the factorized matrix ${\mathbf{H}}_4$. Furthermore, when assessing computational complexity, left–right shift operations are typically left out because they are fairly simple and do not call for additional memory access. Take note that in this case, we account for the fact that, as opposed to 12, only 8 additions are needed to multiply a fourth-order Hadamard matrix by a vector. A thorough schematic representation of the matrix–vector multiplications of the appropriate vectors by the factorized matrix ${\mathbf{H}}_4$ is shown in Figure 4. This is the so-called four-point “fast Hadamard transform”.

It should be noted that in applications related to quaternion-valued DSPs, often one of the multiplied quaternions contains coefficients that are real constants. In this case, the coefficients can be calculated in advance and stored in the processor’s memory. Therefore, the arithmetic complexity of the proposed algorithm can be further reduced and it requires only eight real multiplications and only 20 real additions.

4. Quaternion Multiplier Structure

Figure 5 shows a rough outline of the structure of a quaternion multiplier that implements the proposed approach.

The quaternion multiplier works as follows. At the beginning of the system operation, the coefficients of the multiplied quaternions, naturally ordered, are written to the corresponding buffer memory cells, as seen in Figure 5 on the left and at the bottom. The multiplicand is written to the upper-left group of registers, and the multiplier is written to the registers, which are located at the bottom of the figure.

In the next time period, the DM demultiplexers prepare and transmit data, as shown in the figure. In this case, the first half of the entries of the first data vector, using a demultiplexer located in the upper-left part, goes to the fast Hadamard transform block, and then to the first inputs of the upper half of the multiplication blocks. The reordered second half of the entries in this vector goes directly to the first inputs of the lower half of the multiplication blocks. In this case, the appropriately prepared data are fed through the lower demultiplexer to the second inputs of the lower half of the multiplication blocks (see the left half of the demultiplexer outputs). In turn, the right half of the outputs of this demultiplexer is connected to the inputs of the fast Hadamard transform block; for these outputs, the data are supplied to the second inputs of the second half of the multiplication blocks.

In the last time period, data from the outputs of the first four multiplication blocks arrive to the inputs of the upper-right block of the fast Hadamard transform, and then to the first inputs of the corresponding adder subtractors. In this case, data from the outputs of the four lower multiplication blocks arrive at the second inputs of the adder subtractors. The result of the calculation goes into the output buffer.

As you can see, the main working blocks of the proposed structure are three blocks that implement the four-point fast Hadamard transform algorithms, eight multipliers, and four two-input adder subtractors. To avoid problems with data input/output, four register buffers are located at the input and output. Data are supplied to the binary multipliers using two special demultiplexers, the operation of which is clear from Figure 5. The quaternion multiplier operates under the control of a master device.

5. Hardware Implementation of Quaternion Multiplication

5.1. Implementation on FPGA

The fast quaternion multiplication shown in Figure 5 was implemented on Artix-7 xc7a100tfgg484-1. The project was realized using the Vivado 2016.4 tool. This multiplication was carried out in two ways: based on regular and pipeline processing. In the first case, the clock frequency achieved was 50 MHz, and in the second, 250 MHz was achieved. Due to the buffering occurring in pipeline processing, an additional 768 flip flops (FFs) were used, which, however, constitute only 0.61% of the matrix resources.

In the case of the direct pipelined implementation of quaternion multiplication, the multiplications were separated from the additions by inserting registers after each operation. In the case of the fast pipelined implementation, registers were added between each operation, and additional registers in some signal paths were added to synchronize the signals at the output. These changes allowed the clock frequency to be increased from 50 MHz to 250 MHz.

An important comparison criterion, apart from clock frequency and power consumption, is the use of processors (DSPs). As mentioned in the previous sections, the developed algorithm reduces the number of required multiplications, which should translate directly into the number of DSPs. The operations of multiplying by 2 and dividing by 4 in Figure 5 do not involve additional DSPs because they are implemented as shifts in registers. For comparison, a direct algorithm resulting from the notation in Equation (5) was implemented. According to this relationship, 16 multiplication operations are required. This algorithm was also implemented in two versions: pipeline processing, with a clock frequency of 250 MHz, and regular processing, with a clock frequency of 50 MHz. The number of processors requiring the largest area on the chip has doubled (16 DSPs). The power consumption in the case of direct multiplication is practically the same as in the case of fast multiplication.

The simulation results are summarized in tables.

Table 1. Pipeline implementation of direct and fast quaternion multiplication obtained for a 250 MHz clock.

Resources	Utilization		Available Resources
	Direct Multiplying	Fast Multiplying
LUT		640 (1.01%)	63,400
FF	96 (0.08%)	768 (0.61%)	12,680
DSP	16 (6.67%)	8 (3.33%)	240
IO	256 (90.18%)	257 (90.18%)	258
BUFG	1 (3.13%)	1 (3.13%)	32
Energy consumption
clocks	0.003 W (1%)	0.01 W (2%)
signals	0.019 W (5%)	0.037 W (10%)
logic	<0.001 W (<1%)	0.016 W (4%)
dsp	0.04 W (11%)	0.02 W (5%)
io	0.302 W (82%)	0.305 W (79%)
dynamic (sum of the above)	0.364 W (80%)	0.388 W (81%)
static	0.092 W (20%)	0.092 W (19%)

compares resource utilization and power consumption for a pipelined implementation of direct and fast quaternion multiplication. In

Table 2. Usual implementation of direct and fast quaternion multiplication obtained for a 50 MHz clock.

Resources	Utilization		Available Resources
	Direct Multiplying	Fast Multiplying
LUT	62 (0.1%)	512 (0.81%)	63,400
FF			12,680
DSP	17 (7.08%)	8 (3.33%)	240
IO	257 (90.18%)	257 (90.18%)	258
BUFG	1 (3.13%)	1 (3.13%)	32
Energy consumption
clocks	0.001 W (1%)	0.001 W (1%)
signals	0.007 W (5%)	0.013 W (9%)
logic	<0.001 W (<1%)	<0.005 W (<3%)
dsp	0.016 W (11%)	0.008 W (5%)
io	0.121 W (82%)	0.122 W (79%)
dynamic (sum of the above)	0.145 W (61%)	0.149 W (62%)
static	0.091 W (39%)	0.091 W (38%)

, a similar comparison was made for the regular implementation. Apart from achieving a 5-times higher frequency, regular and pipelined implementations are comparable in terms of resource utilization. Higher dynamic energy consumption in a pipelined implementation is associated with obtaining a higher clock frequency. However, the fast and direct multiplication methods differ in both cases by twice the number of processors (DSPs).

5.2. ASIC Implementation

Both quaternion multiplication operations have also been implemented as ASICs. The OpenLane environment was used for this purpose. OpenLane is an environment composed of tools for the synthesis of digital circuits, the result of which is an integrated circuit in the form of a GDSII file. It should be mentioned that the tools creating OpenLane are integrated with the publicly available SkyWater 130 nm technological process. This makes it possible to produce a physical layout. The entire synthesis process is automated; the environment synthesizes the system into interconnected logic cells. In the next step, it arranges and connects previously generated cells, each time analyzing the system using DRC and LVS until the synthesis assumptions are met. The starting point in this project is the description of the system in a high-level hardware language.

The two versions of the multiplier considered are described in VHDL. The direct algorithm resulting from Formula (5) in this description is available as a free software on GitHub repository http://github.com/AHandkiewicz/IIR3D (accessed on 23 July 2024) in the quaternion VHD directory. The part of this description resulting from the Formula (5) is presented in Listing 1.

Listing 1. Direct implementation of quaternion multiplication

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;   architecture Flow of mul is begin process(clk,a0,a1,a2,a3,b0,b1,b2,b3) begin if rising_edge(clk) then y0 <= a0∗b0-a1∗b1-a2∗b2-a3∗b3; y1 <= a0∗b1+a1∗b0+a2∗b3-a3∗b2; y2 <= a0∗b2+a2∗b0+a3∗b1-a1∗b3; y3 <= a0∗b3+a3∗b0+a1∗b2-a2∗b1; end if; end process; end Flow;

The automatically generated testbanch for designing a fast quaternion multiplication system is also available as a free software on GitHub repository, http://github.com/AHandkiewicz/IIR3D (accessed on 23 July 2024).

The resulting layout of this system is shown in Figure 6.

For comparison, the ASIC generated for direct multiplication is shown in Figure 7. In the first case, the system was generated in 43 min, and in the second one, the system was generated in 69 min.

The most important parameters related to the ASIC implementation of both quaternion multiplication methods are summarized in

Table 3. ASIC implementation of fast and direct quaternion multiplication.

Multiplication	Fast	Direct
Core Area (mm2)	0.3649850496	0.469800576
# Cells	19,004	23,813
AND	1118	4310
NAND	646	802
NOR	2344	1112
OR	2613	3143
XOR	5061	7018
XNOR	2444	2231
Frequency (MHz)	19.6078	19.6078

.

As you can easily see, the fast algorithm gives over 25% savings in chip area and resource use. Identical synthesis settings were used when designing the systems, so the results obtained are more objective and fully comparable.

6. Conclusions

The paper presents the original structure of a processing unit for multiplying quaternions and demonstrates significant savings in resources on FPGA blocks and chip areas on ASICs. The direct quaternion multiplication takes 16 real multiplications and 12 real additions. The algorithm presented in the paper, based on the Hadamard matrices, reduces these numbers to eight real multiplications and 20 real additions. This is reflected in the hardware implementation of the algorithm. The utilization of individual FPGA blocks is shown in the Table 1 and Table 2. Resource savings of more than 50% are clearly visible among others, for example, in the case of digital signal processors (DSPs). The results of the implementation of the developed algorithm in the form of an integrated circuit (ASIC) are presented in Table 3. Also in this case, a significant reduction in resource consumption is achieved, e.g., a chip area reduction in network of more than 25%.