Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory

Abstract

The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digital computations. The proposed configurable memory unit operates in three modes: (1) memory mode in which it works as a normal dynamic memory, (2) logic–arithmetic mode where it performs bit-wise Boolean logic and full adder operations on two words stored within the memory array, and (3) convolution mode in which it executes digitally XNOR-and-accumulate (XAC) operation for binarized neural networks. A 1.0-V 4096-word × 8-bit computational DRAM implemented in a 45-nanometer CMOS technology performs memory, logic and arithmetic operations at 241, 229, and 224 MHz while consuming the energy of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, it saves energy and latency of the arithmetic operation by at least 47% and 46%, respectively. For V_DD = 1.0 V, the proposed CIM unit performs two 128-input XAC operations at 292 MHz with an energy consumption of 20.8 pJ/cycle, achieving 24.6 TOPS/W. This marks at least 11.9× better energy efficiency and 38.8× better delay, thereby achieving at least 461× better energy-delay product than traditional 8-bit wide computing hardware.

1. Introduction

Massive and frequent data move between memory banks and processing elements incurs substantial latency and energy cost in the traditional von Neumann machine. Compute-in-memory (CIM), which performs computations inside the memory units, is an attractive approach to solve such memory wall issues and thereby sustain the throughput and energy requirements of data-driven computing applications such as voice/image recognition, autonomous driving, artificial intelligence (AI), and similar big data technologies [1,2]. It is desirable for the CIM design to be compatible with logic CMOS process, to achieve short latency as well as high energy efficiency, and to offer dense bit cell footprint and robust computation against process variations.

In recent years, various memory hierarchies such as SRAM, 1T/1C DRAM, and emerging memories have been explored in order to implement CIM schemes. The SRAM-based CIM designs [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31] are compatible with the logic CMOS process and feature short latency. But the bit area is large (e.g., 6T, 7T, 8T, 8T/1C, 9T, 9T/1C, 10T, 12T, or 16T bit cells), thus the limited memory capacity in the CIM macros restricts the complexity of energy-efficient computing systems. Furthermore, SRAM arrays suffer from substantial leakage power dissipation, often dominating the total power budget of the entire computing systems. The embedded 1T/1C DRAM-based CIM design [32] might be an alternative to SRAM-based architecture with its higher integration density. However, the 1T/1C DRAM structure requires additional process steps for storage capacitors and cannot perform dot product computations directly on the memory bitlines because of its destructive readout. The CIM implementations based on nonvolatile memories such as RRAM [33,34,35,36,37,38,39,40], PCRAM [41], STT-MRAM [42], or memristor [43] have also fostered computing in memory, but such emerging technologies are still immature. Poor reliability and the low endurance of RRAM devices [44], the long write time and high write energy of PCRAMs [45], the low on–off ratio of STT-MRAM cells [46], the bad scalability and limited yield of memristive devices [47], etc., make them less attractive for accurate and efficient CIM units.

In particular, the embedded gain cell DRAM (GCDRAM) is one of the prospective candidates to realize the CIM scheme, owing to its compatibility with standard logic CMOS process and compact bit cell area. Despite the relatively short retention time of the embedded gain cell itself, the prior GCDRAMs [48,49,50,51,52,53] achieved better area efficiency and much smaller standby power dissipation compared with 6T or read-decoupled (RD) 8T SRAMs. In addition, recent GCDRAM-based CIM works [54,55,56,57,58,59,60,61] have demonstrated the multiply-and-average (MAV) or multiply-and-accumulate (MAC) computations within the gain cell array. They improved substantially both power consumption and throughput in processing the deep neural networks (DNNs). In this work, we propose another GCDRAM-based CIM unit, called the digital computing gain cell DRAM (DC-GCDRAM). The proposed DC-GCDRAM array supports three modes of operation: memory mode, logic–arithmetic mode, and convolution mode. In the memory mode, the DC-GCDRAM works as a usual DRAM compatible with standard CMOS technology. In the logic–arithmetic mode, the proposed architecture performs bit-wise Boolean logic as well as arithmetic computations on operands stored within the memory array. In the convolution mode, the proposed DC-GCDRAM executes the binary XNOR-and-accumulate (XAC) operation on weights stored within the cell array and external input activations. This full-digital CIM unit maintains high circuit reliability. It effectively eliminates the analog design issues such as data conversion overheads and computing accuracy loss caused by process variations. All of the results were obtained using 45-nanometer generic CMOS technology.

The rest of this article is organized as follows. Section 2 briefly describes the basics of the memory cell used in this work. Section 3 details the proposed DC-GCDRAM architecture. Section 4 outlines and discusses the evaluation results. Finally, we conclude this work in Section 5.

2. Logic-Compatible 3T Memory Cell

In Figure 1, we show the hybrid 3T gain cell schematic and its layout. Here, MW denotes the high threshold-voltage (V_TH) write-transistor, MR is the standard V_TH read-transistor, and MS is the standard V_TH storage-transistor. In addition, DN means data node, RBL is read-bitline, RWL is read-wordline, WWL is write-wordline, WBL is write-bitline, and so on. The bit cell area is 0.5 × 0.515 µm², which is 59.2% and 49.9% smaller than those of RD-8T and 6T SRAM in the same 45 nm generic process.

The voltage waveforms depicted in Figure 2 explain the operating principle of the 3T cell. During the standby, RWL and WWL are grounded while both WBL and RBL are precharged to V_DD. This hold condition turns MW and MR off, thus storage in the DN is preserved. To read the stored information, RWL is raised to high while WWL is grounded. If DN is low, MS is in the off state; hence, RBL is kept at V_DD. If DN is high, MS is turned on; thus, a read current from RBL flows to the ground. This lowers the RBL level. Two different RBL levels are detected by a voltage sense amplifier (SA). To write a datum on the cell, WBL is driven to either low or high while RWL is grounded. WWL is then boosted to V_PP which is higher than the supply voltage. This allows a new datum from the write-bitline to be fully written to DN through the high V_TH write-transistor.

3. Proposed DC-GCDRAM Architecture

3.1. Overview

Figure 3 represents the overall structure of the reconfigurable DC-GCDRAM. The bit storage element of this CIM macro is the 3T gain cell described in Section 2. Basically, the memory array comprises a pair of 16 kbit storage blocks. Each block consists of 128 columns and 128 rows. The memory I/O is 8 bits wide. This CIM macro contains two WWL boosters, dedicated to 16 kbit block each, supplying the V_PP voltage. The entire CIM macro is operating at single power supply.

The proposed DC-GCDRAM allows functional mode switching among memory, logic–arithmetic, and convolution operations. The operational modes are selected with the external signals named FM₀ and FM₁. If both FM₁ and FM₀ are low or high, the CIM macro operates in the memory mode where it performs read/write/refresh as regular DRAM. If FM₁ is low and FM₀ is high, the macro operates in the logic–arithmetic mode. In this mode, the macro turns on two rows at once and uses binary logic SAs within the computing logic to generate bit-wise Boolean logic primitives and addition results. If FM₀ is low and FM₁ is high, the macro enters the convolution mode. In this functional mode, the macro allows the XNOR and population count operation for binarized neural networks (BNNs). For each cycle, the CIM macro utilizes XNOR sense amplifiers (XNOR-SAs) within each memory block to compute bit-wise XNORs between activation inputs and row-wise stored weights, and then generates the accumulation results at each population counter output. The details of these three modes of operation are described in the following subsections.

3.2. Memory Mode

Figure 4 details the physical and logical organization of compute-in-memory. The whole memory array comprises bilaterally symmetric two 16 kbit storage blocks with row decoders in the middle. The fundamental organization is 4k-word × 8-bit. Inside each 16 kbit storage block, the bitline (BL) switches, BL sense amplifiers (BL-SAs), column decoders, and column gates are placed on the bottom of array, while the XNOR-SAs, activation switches and BL prechargers are placed on the other side of array. The population counters are placed over the storage blocks, while the computing logics (CMPLGs) and write drivers (WDRs) are placed under the two adjacent blocks. The read-datalines (RDLs) and write-datalines (WDLs), which are shared by two storage blocks, are used to transfer single-ended 8-bit signals between selected columns and CMPLGs or WDRs.

Figure 5 depicts the simplified circuitry of a 16 kbit storage array. During the hold, the BL switches are in an off state, and both WBL and RBL are precharged to V_DD. Every memory access turns on a row and activates the corresponding BL-SA. The latch-type BL-SA in this design makes use of a reference signal (V_REF) that is positioned in-between data ‘0’ and data ‘1’ signals. In Figure 6a, we show the simulated waveforms for read operation. After turning off the BL prechargers, the read access begins by activating RWL, causing the RBL level to remain stationary or to discharge. Meanwhile, WBLS and RBLS are initially precharged to V_REF and V_DD, respectively, and then floated by raising nSAPRE to V_DD. Triggering RS and RSB forwards the RBL signal to RBLS. Before sensing the data, the read BL switches are turned off. Then, the BL-SAs are activated by firing SAP and SAN. Afterward, triggering YR and YRB transfers a full-swing RBLS signal to RDL. The latency from RWL to block SA output (BSA_OUT) measures 1.5 ns at the 1.0 V supply. Simulated waveforms in Figure 6b illustrate the write operation. After BL-SAs determine the status of accessed cells, an internal write-back operation follows. To store external data on the cells, the new data for selected columns are driven into WBLSs when YW and YWB are triggered. The BL-SAs toggle if the new contents are different from the accessed ones. Next, WBLs are connected to WBLSs by switching WS and WSB. Then, WWL is fired, allowing the external data to be fully written to the selected cells.

In Figure 7, we show the data refresh scheme used in this design. Basic refresh circuitry consists of a refresh controller and a 7-bit address counter with an oscillator. The row address buffers switched by internal refresh signals provide either the refresh address (RFA<0>~RFA<6>) or the normal row address (A<0>~A<6>) to the storage array. If an external signal RF is low, the CIM macro is available for memory or two other mode operations. To enter into the auto-refresh, RF is set to high for 0.96 μs or over. This blocks the incoming functional command and initiates a series of refresh cycles for all memory rows, corresponding to simple read and write-back with column gate off. The rise in RF activates a refresh demanding signal RFRSH, then the 7-bit counter begins to increase the address of row to be refreshed one by one. A refresh cycle activates two rows (one from each 16 kbit storage block in Figure 4) at the same time, thus 256 bits are restored for each cycle. Right after the last row refresh, RFRSH is finally reset to low. In this design, a refresh time of 100 μs or longer achieves a refresh overhead less than 1%.

3.3. Logic–Arithmetic Mode

The configurable DC-GCDRAM can perform a certain logical and arithmetical operations between the row-wise stored DRAM words. In Figure 8, we show their computation schemes. During this operation mode, the CIM macro employs two row address decoders to activate two RWLs simultaneously and utilizes a NOR sense amplifier (NOR-SA) and a NAND sense amplifier (NAND-SA) within the computing logic to produce bit-wise Boolean logic primitives and addition results. The 8-bit-wide computation is realized by 16:1 column multiplexing.

The logic–arithmetic operation begins by turning on the RBL switches and the read column gates after the BL and dataline (DL) prechargers are disabled. Then, two RWLs (RWL<i> and RWL<j>), which correspond to the memory cells storing operands ‘A’ and ‘B’, are activated. Depending on the status of the operands, the RDL will discharge, as shown in Figure 9, at three different levels. If AB = 00, the RDL does not discharge. Hence, the corresponding RDL voltage (V_RDL0) is V_DD. If AB = 10 or 01, one bit discharges the RDL. The resulting RDL voltage is V_RDL1. If AB = 11, the RDL discharges more quickly, resulting in a lower RDL voltage (V_RDL2). Comparing the RDL level against a NOR reference voltage (V_{REF_NOR}) with the NOR-SA (SA_NOR) generates the NOR/OR results. Simultaneously, comparing the RDL level against a NAND reference voltage (V_{REF_NAND}) with the NAND-SA (SA_NAND) produces the NAND/AND results. Moreover, the XOR operation is implemented by wiring the NOR and AND results to a NOR circuit. Similarly, the XNOR result is obtained by wiring the NAND and OR results to a NAND circuit. In addition, these Boolean logic primitives permit a full adder (FA) to be realized. A traditional FA produces SUM and carry-out (C_OUT) by adding three input operands A and B and carry-in (C_IN). The Boolean equations for the SUM and carry-out can be expressed as follows:

$$SUM=\left(A\oplus B\right)\oplus C_{IN}$$

(1)

$$C_{OUT}=\overline{\overline{AB}\ast \overline{\left(A+B\right)\ast C_{IN}}}$$

(2)

These indicate that a primitive $\mathrm{A}\oplus \mathrm{B}$ can implement the FA’s sum using a XOR gate, and that two primitives,$\left(\mathrm{A}+\mathrm{B}\right)$ and $\overline{\mathrm{AB}}$, can implement C_OUT using two additional NAND gates. In Figure 9a, we have shown a circuitry implementing the bit-wise FA operation by the name of FA-logic. By cascading FA-logics, we realized an eight-bit ripple-carry adder (RCA), as shown in Figure 10. This 8-bit RCA operation is fully performed in one operating cycle.

One thing to be designed with care might be the voltage reference scheme. In order to produce the correct logic functions, the reference voltages should satisfy the following conditions:

$$V_{RDL1}+V_{OS}<V_{REF\_NOR}<V_{DD}-V_{OS}$$

(3)

$$V_{RDL2}+V_{OS}<V_{REF\_NAND}<V_{RDL1}-V_{OS}$$

(4)

where V_OS is an offset voltage of the latch-isolation NOR/NAND-SAs in Figure 9b,c. In this design, we set the target levels of V_{REF_NOR} and V_{REF_NAND} to 0.86V_DD and 0.38V_DD as shown in Figure 11. In Figure 12a, we show the reference circuits for the NOR/OR and NAND/AND operations. They form a ratioed circuit with two resistors. When the control signals (VREN_NOR, VREN_NAND) transit from low to high, the V_REF voltage levels are simply determined by the ratio of two poly-silicon resistors: $V_{REF\_NOR}\cong R_2{V}_{DD}/\left(R_1+R_2\right)$ and $V_{REF\_NAND}\cong R_4{V}_{DD}/\left(R_3+R_4\right)$ where the equivalent resistances of transistors MP1, MN1, MP2, and MN2 are negligible. To obtain robust reference levels, the resistors were sized carefully across all specified temperature and process variations. Figure 12b shows the simulated characteristics of the V_{REF_NOR} and V_{REF_NAND} generators for temperature variations (−40 °C, 25 °C and 85 °C) as well as all possible process corners including skewed FS and SF. At the 1.0 V supply, the relative errors between the reference targets (0.86V_DD and 0.38V_DD) and generated voltages are less than 0.35% for V_{REF_NOR} and 0.53% for V_{REF_NAND}. In Figure 13, the 2500-point Monte Carlo simulations for the NOR/OR and NAND/AND outputs are shown for the three possible cases (AB = 00, 01/10, and 11). The functional results are all correct with the proposed reference scheme.

The other thing to be considered with care when designing the DRAM-based CIM unit would be the data retention of the dynamic memory. In the DC-GCDRAM, the data stored on the gain cells are destroyed by the cell leakages. This storage degradation not only affects the retention time of the GCDRAM but may also induce a computational error in the logical operation. To prevent this leakage-induced computing error [55,56], we set a constraint on retention time, as shown in Figure 14. During standby, storage in the DN is left floating, and thus the gain cell leakages cause the stored information to change with time. Note that the retention time of all-NMOS cells with unbalanced leakages is predominantly determined by the bit cells with data ‘1’ [49,52]. Meanwhile, in the logic operation, the unit cell current I_CELL drawn by a single bit with data ‘1’ for a time interval of τ develops an RDL voltage difference, i.e., $\Delta V=\tau \times I_{CELL}/\left(C_{RBL}+C_{RDL}\right)$, where C_RBL and C_RDL are the RBL and RDL capacitance. If two bits discharge the RDL, the corresponding voltage drop will be $2\times \Delta V$. Here, we define a minimum high-level storage DN(1)_MIN to ensure that the RDL voltage drop by two bits is larger than $\left(V_{DD}-V_{REF\_NAND}+V_{OS}\right)$. This specific DN level might guarantee the correct NOR/OR and NAND/AND operations during the logic–arithmetic mode. From extensive simulations, DN(1)_MIN in this work has been observed to be 0.64 V at 1.0 V and 85 °C with V_OS of 80 mV. The corresponding retention time at this condition was found to be 120 μs.

3.4. Convolution Mode

The convolutional neural networks (CNNs) and deep learning are currently widely used for modern AI tasks such as traffic prediction, speech recognition, or image classification. But they consume extensive computing and memory resources. To reduce their arithmetic complexity and memory access, in recent algorithms called binarized neural networks [62], network weights and input activations are restricted to single bits (+1 or −1), such that the MAC operation, the most dominant operation in DNNs, is replaced by a simple bit-wise XNOR followed by population count (XNOR-and-accumulate) operation. The binarized neural networks (BNNs) are one of good candidates for deep learning implementation on DNN hardware, owing to their extreme energy efficiency.

In Figure 15, we show how the configurable DC-GCDRAM perform the XAC operation for BNNs. The memory array composed of 3T cells stores network weights (W_i) in a binary format. Activation switches [34] in Figure 15a, controlled by the input activations (marked with A_i and /A_i in a complementary style), connect a pair of bitlines to a bit-wise XNOR-SA. Thus, an XNOR result between W_i and A_i can be calculated during a read access. Figure 15b represents a simplified configuration to illustrate how the DC-GCDRAM executes the XAC operation. For each operating cycle, two rows (one from each 16-kbit array) are activated by enabling their RWLs. After the BL-SAs (SA_BL) are fired, the XNOR-SAs compute the bit-wise XNORs between activations and weights, and then the results are forwarded to the bit counters to carry out the population count operation. Each counter takes 128 bit inputs and generates an 8-bit count as output. Although this digital architecture has a limited throughput compared to the analog XAC implementations which activate all their rows at once [18,19], this approach does not need analog-to-digital converters incurring huge area/power overhead and provides extremely accurate computation results even with process–voltage–temperature (PVT) variation.

Figure 16 shows the digital bit counter implemented in this design, which adds all of the bit-wise XNOR results to generate a population count. The counter circuit uses a Wallace-tree structure to compress the 128-bit digital input (XNOR<0:127>) to an 8-bit digital output (PC_OUT<0:7>), which ranges from 0 to 128. The 12-layer tree structure achieves maximum possible reduction using 120 FAs and 15 half-adders (HAs), in which the schematics of adders are shown in Figure 17. Here, two kinds of FAs (22T FA with driving inverter and 16T FA without driving inverter) are interleaved to trade off the circuit delay against the circuit area. At 1.0 V and 25 °C, the total power dissipation and critical-path delay of the bit counter in performing a 128-bit population count have been observed to be 0.84 mW and 0.58 ns, respectively.

To verify the operation of convolution mode within the DC-GCDRAM array, circuit-level simulations have been performed for all XAC combinations. The simulated waveforms shown in Figure 18 plot the results for the case when both 128 network weights and 128 input activations are all logic-high. The convolution operation, similar to the read operation of memory mode, begins by pulling RWL up to a high level after the BL and XNOR-SA prechargers are disabled. At the same moment, WBLS and RBLS are initially precharged to V_REF and V_DD, respectively, and then floated by raising nSAPRE to high. Triggering RS and RSB forwards the RBL signal, which depends on the status of weight, to RBLS. Then, the RBL switches are disabled, and the BL-SAs are fired. After RWL is returned back to a low level, both WBL and RBL switches are turned on to reflect the value of weight onto WBL and RBL in a complementary format. Afterward, the activations in a complementary format, which come from the activation input buffers, are developed at the gates of the activation switches. This allows the XNOR-SAs to compute the bit-wise XNORs between weights and activations and to send the results to the Wallace tree bit counter. The latency from RWL to the bit counter output (PC_OUT) measures 1.98 ns at 1.0 V supply.

4. Evaluation Results and Discussion

The proposed DC-GCDRAM shown in Figure 3 has been evaluated under different operating modes by extensive simulations using 45 nm CMOS technology. Basically, the designed computational DRAM consists of two 16-kbit memory arrays and the peripheral circuitries like address buffers, predecoders, block signal generators, control buffers, control logic, refresh controller, oscillator, refresh address counter, and I/O buffers. The CIM macro contains two WWL boosters, 256 row decoders, 32 column decoders, 8 computing logics, 8 write drivers, and 2 population counters. In the memory mode, the data-in or data-out is 8 bits wide. In the logic–arithmetic mode, the macro outputs 8-bit wide logic computation results or produces 8-bit wide addition results with a single-bit carry-out. In the convolution mode, the CIM macro takes two 128-bit activations and generates two 8-bit counts as output. The operation cycle of each functional mode is self-timed from the positive clock (CLK) edge.

In Figure 19, we have shown the maximum frequency and energy dissipation of the memory operation from 1.1 down to 0.8 V. The energy consumption here represents a whole energy wasted in bitlines, datalines, main datalines, wordlines, decoders, BL-SAs, BSAs, write drivers, WWL booster, predecoders, control logic, I/O buffers, and other peripheral circuits. The simulations are consistent with the predictions; reducing the supply voltage brings about longer delays and lower energy consumption. For the supply voltage of 1.0 V, the DC-GCDRAM functions at 241 MHz with write and read energy figures of 8.12 and 7.72 pJ/cycle, respectively. The write energy is 5.2% higher than the read energy because of the WWL boost.

The operation of the logic–arithmetic mode is alike to the read operation in the memory mode, but the difference is that two RWLs are activated at the same time and two binary logic SAs are used in the logic–arithmetic mode. In Figure 20, we show the simulated frequency and energy consumption across the supply voltage for the logic (NOR/OR, NAND/AND, XNOR/XOR) and arithmetic (SUM, carry-out) operations between two words in two rows at room temperature. As V_DD decreases, the energy dissipation and the frequency of both operations are reduced. The logic operation, in general, consumes higher energy than that dissipated by the memory read operation due to activations of two rows and two SAs. The latency of logic operation is about 5% longer than that of the memory read operation. Compared with the logic operation, the arithmetic operation has a slightly longer delay and slightly worse energy consumption because of a few additional logic gates. At V_DD = 1.0 V, the maximum frequencies for the logic and arithmetic operation are 229 and 224 MHz, and the energy consumptions measure 8.09 and 8.19 pJ/cycle, respectively. Using the simulation results in this study, we compared CIM with conventional digital computing, which reads two words for two memory cycles and calculates them within ALUs, in Figure 21. For the arithmetic (FA) operation at 1.0 V supply, it is estimated that the proposed CIM architecture saves energy and latency by at least 47% and 46% compared with the conventional digital hardware.

We also evaluated the energy wasted by the binary XAC operation under a range of conditions. In the convolution mode, the total power or energy consumption of the DC-GCDRAM much depends on the bit-wise XNOR results. This is because the outputs of the XNOR-SAs are initially all tied to the ground. The CIM macro computes two independent 128-input XACs in one cycle. Thus, the weights and activations which correspond to two XAC values being 128 each is the worst case for power consumption. Under this worst case, we evaluated the energy dissipation and frequency across the operating voltage as shown in Figure 22. The energy consumption and maximum frequency increase with the supply voltage. At 1.0 V and room temperature, the CIM macro takes 3.42 ns and consumes 20.8 pJ for two 128-input XAC operations, reaching an efficiency of 24.6 TOPS/W. Using the evaluation results in Figure 19 and Figure 22, we compared the proposed CIM architecture with conventional digital computing in Figure 23. For two 128-input XAC operations at 1.0 V supply, it was estimated that the proposed CIM macro obtains at least 11.9× higher energy efficiency, improves the delay by at least 38.8×, and thereby achieves at least 461× better energy-delay product compared with the conventional 8-bit wide digital hardware, which reads 256 weights byte-by-byte; receives 256 activations, also byte-by-byte; and eventually accumulates two XAC values over 32 cycles.

In

Table 1. Performance comparison with prior GCDRAM-based CIM units.

	[54]	[55]	[56]	[57]	[61]	This Work
Technology	65 nm	65 nm	28 nm	65 nm	28 nm	45 nm
Cell structure	3T1C	4T2C	2T1C	2T1C	3T	3T
Bit cell area (1)	389 F2	256 F2	413 F2	N/A	185 F2	127 F2
Array size (bit)	4 × 64 × 32	128 × 128	144 × 128	32-k	256 × 16 × 10	2 × 128 × 128
Supported functions	MAC	MAC	MAC	MAV	DRAM MAC	DRAM Logic Arithmetic XAC
Computing method	Analog	Analog	Analog	Analog	Digital	Digital
Operating voltage	0.85~1.1 V	0.5/0.7 V	N/A	1.0 V	0.9~1.2 V	0.8~1.1 V
Nominal frequency (MHz) [Operation]	105 [MAC]	200 [MAC]	250 [MAC]	N/A	800 (@1V) [DRAM/MAC]	241 [DRAM] 229 [Logic] 224 [Arithmetic] 292 [XAC]
Throughput (GOPS)	N/A	48	N/A	22~691	200 (2)	150 (3)
Energy efficiency (TOPS/W)	102.2~216.8	17.8~552.5	81.5~115	7.4~236	8~19.7 (2)	24.6 (3),(4)
Accuracy (%)	90.6/91.2	82.8/96.78 (5)	91.52	92.02/99.84	N/A	100 (5)

⁽¹⁾ Normalized to minimum feature size. ⁽²⁾ For MAC operation. ⁽³⁾ For binary XAC operation. ⁽⁴⁾ Includes peripheral/IO-related energy and latency. ⁽⁵⁾ Simulated accuracy.

, the performance of this design has been summarized in comparison with prior GCDRAM-based CIM units. Compared to the previous analog CIM macros [54,55,56,57] which support only the MAC or MAV operation with a certain amount of computation errors, the digital CIM architectures (this work and [61]) are configurable between different operating modes and supports data storage as well as versatile CIM operations without accuracy degradation even under PVT variation. This design supports the logic, arithmetic, and XAC computations, while the work in [61] offers the MAC computation based on an embedded DRAM look-up table.

5. Conclusions

The embedded GCDRAM is one of the prospective candidates for the realization of the CIM scheme because of its compatibility with the logic CMOS process and compact bit area. In this study, we proposed a computational GCDRAM architecture called DC-GCDRAM, which supports a range of Boolean logic and FA operations for off-load computations and computes XAC operations for binarized neural networks while operating as a normal DRAM for general-purpose workloads. To validate the effectiveness of the proposed DC-GCDRAM, a 4096-word × 8-bit CIM macro using logic-compatible 3T dynamic cell, which can be configurable to memory and a range of computing operations, has been implemented with a 45-nanometer generic CMOS technology. For V_DD = 1.0 V, the proposed architecture performs memory, logic, and FA operations at 241, 229, and 224 MHz with energy figures of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, the DC-GCDRAM saves energy and latency of the FA operation by at least 47% and 46%, respectively. At the same supply voltage, the proposed CIM design takes 3.42 ns and consumes 20.8 pJ for two 128-input XAC operations, reaching 24.6 TOPS/W. The results indicate that the proposed architecture achieves an at least 11.9× higher energy efficiency as well as an at least 461× better energy-delay product compared to the traditional 8-bit-wide computing hardware.