Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines

Abstract

As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically, in the 6F² DRAM structure, activating a word line (WL) lowers the energy barrier of adjacent WLs, leading to the Pass Gate Effect (PGE). This study investigates the use of buried oxide beneath the WL to mitigate the PGE through simulation. Using SILVACO TCAD, we analyzed the impact of varying the size and position of the buried oxide on the PGE. The results showed that increasing the oxide size or reducing the distance to the WL effectively reduced the PGE. However, the presence of interface traps, which increase with the addition of buried oxide, was found to exacerbate the PGE, indicating that minimizing interface traps is crucial when incorporating buried oxide.

1. Introduction

Today, Von Neumann architecture, which consists of a CPU (Control Processor Unit), memory, and I/O (Input and Output), is considered a standard in computer architecture. Among other components, memory is a significant device as it stores command sets and calculated data. Many memory devices have been introduced today, such as SRAM, DRAM, SDRAM, etc.; however, DRAM (Dynamic Random Access Memory) has become the standard for reasons such as high reliability and ease of integration due to its 1T1C structure. Over time, DRAM has become required to process more data, and these requirements were particular accelerated by the Fourth Industry Revolution. To meet these demands, DRAM has been developed via scaling down like other semiconductors, leading to increased performance and decreased power consumption. However, scaling down has introduced several negative effects, such as GIDL (Gate Induced Drain Leakage), GIJL (Gate Induced Junction Leakage), 1-Row Hammer, and the PGE (Pass Gate Effect), which have emerged due to increased interferences [1,2,3,4,5,6,7,8,9,10]. These negative effects can lead to data loss and therefore adversely impact the reliability of DRAM. Figure 1a illustrates the layout of DRAM in the unit array area. Although data can be recovered by performing a refresh operation, this results in higher power consumption and decreased performance [11]. The PGE occurs when the FPWL (Field Pass Word Line) is in the on state. Through the supplied voltage of the FPWL, the active word line is affected by an electric field. This mechanism decreases the threshold voltage of the active word line and leads to unwanted data access. Due to the structural characteristic where the word line crosses multiple cells, DRAM can lose data simultaneously because of this effect [12,13]. Refreshing, which offers data recovery, can restore lost data; however, it consumes more power and decreases overall performance.

In this study, we propose a 6F² structure with buried oxide under the active word line that protects the energy field from the FPWL to mitigate the PGE. To find the optimal value, we studied various modifications to the buried oxide, such as increasing oxide thickness, increasing oxide length, and decreasing the distance from the AWL to the buried oxide. Additionally, by adding interface traps to the buried oxide, we were able to conduct a study about the effect of traps. Figure 1a illustrates a diagram of the 6F² DRAM array at the top view, and Figure 1b shows a cross-section of the cell indicated by a red dotted line.

2. Simulation Methods

2.1. PGE Measurement

When FPWL is in an on state, the applied voltage generates an energy field, causing the energy band of the AWL to be lowered. Thus, the charge flows at a lowered voltage, which is expressed as a lowered threshold voltage (Vth). Through this phenomenon, the PGE value is calculated by the difference in FPWL’s Vth from an off state to an on state. The purpose of our study is to prevent the AWL from reaching the electric field of FPWL. Figure 2 shows the energy band and the I_d–V_g curve as they change with the on and off states of the Field Pass Word Line.

2D DRAM models were simulated using SILVACO TCAD simulation (DeckBuild version 5.2.17.R and DevEdit version 2.8.26.R).

Table 1. Simulation conditions.

Structure Condition			Simulation Condition
Symbol	Region	Size [nm]	Region	Voltage [V]
$T_{\mathrm{o}\mathrm{x}}$	Gate oxide thickness (side, bottom)	8/6	Substrate	−0.6
$W_{\mathrm{W}\mathrm{L}}$	WL width (AWL, FPWL)	12	Bit Line	1
$D_{\mathrm{A}\mathrm{W}\mathrm{L}}$	Active WL depth	80	Active Word Line (Von, Voff)	3/−0.2
$D_{\mathrm{F}\mathrm{P}\mathrm{W}\mathrm{L}}$	Field Pass WL depth	100	Field Pass Word Line (Von, Voff)	3/−0.2
$W_{\mathrm{A}\mathrm{c}\mathrm{t}}$	Silicon active width	23

shows the structure condition and the simulation condition. Every value is based on the 6F² DRAM structure, which is precisely widely used. Figure 3 illustrates the buried oxide under the active word line in a 2D DRAM structure. To find the optimal value, we modified the buried oxide by changing the size or lowering the distance from the AWL.

The silicon body was doped with boron at a concentration of 10¹⁷ cm⁻³, and the AWL and FPWL utilized an STI structure with SiO₂. All these conditions replicate the structure using a saddle fin [14,15,16,17,18,19,20,21,22,23,24].

2.2. Optimizing Buried Oxide

To investigate the tendency of the PGE based on the form of buried oxide, it is necessary to set a structural standard. So, we set the initial values for buried oxide to have a width of 28 nm, a thickness of 30 nm, and a distance of 18 nm from the AWL to the buried oxide. The buried oxide is positioned directly beneath the word line and aligned in the same direction as the word line. Its material is based on SiO₂.

Table 2. Conditions and steps of buried oxide.

Parameter	Initial Value	Step
Material	SiO2	N/A
Distance from oxide to AWL (Dbo)	18 nm	−4 nm
Thickness of oxide (Tbo)	30 nm	+4 nm
Width of oxide (Wbo)	28 nm	+4 nm

shows the parameters and steps of buried oxide, and Figure 3 illustrates the location and parameters of buried oxide. Using the initial values we set, we conducted a study on modifying buried oxide by lowering the distance (D_bo), increasing the width (W_bo), and increasing the thickness (T_bo). The tendencies of PGE values were verified by extracting 5 results for each modification, and we finally verified how much the PGE value had decreased.

The D_bo was measured by moving 4 nm closer to the AWL at each step. Although theoretically, this could result in five measurements, starting from 18 nm and reducing to 2 nm, the 2 nm interval is challenging to achieve with current technology. Therefore, instead of including the 2 nm measurement, a result at 22 nm was added to provide a clearer trend, starting from 18 nm and increasing by 4 nm. The W_bo was increased by 4 nm in total for each step, with 2 nm added to both the left and right sides. Similarly, for the T_bo, the thickness was increased by 4 nm in total, with 2 nm added above and below. Figure 4 illustrates the changes in the buried oxide for each case.

2.3. Effect of Interface Traps in Buried Oxide

The primary objective of the buried oxide is to mitigate the Pass Gate Effect (PGE). Therefore, it is critical that the addition of this structure does not inadvertently worsen the PGE. However, at the interface where Si meets amorphous SiO₂, incomplete bonds in some Si atoms lead to the formation of positive charges, creating interface traps. These traps decrease the threshold voltage (Vth), negatively affecting the PGE. As a result, preventing the formation of interface traps during the deposition of the buried oxide is essential. To better understand how interface traps influence the PGE, we varied the trap density and analyzed the corresponding changes in the PGE values.

3. Results

To verify the effectiveness of the buried oxide, we first compared the PGE of the existing structure with the new structure. In the existing structure, the $V_{\mathrm{t},\mathrm{o}\mathrm{f}\mathrm{f}}$ value was 1.269 V, and the $V_{\mathrm{t},\mathrm{o}\mathrm{n}}$ value was 0.837 V, resulting in a final PGE of 0.433 [$∆\mathrm{V}$]. In the structure with the added buried oxide, the $V_{\mathrm{t},\mathrm{o}\mathrm{f}\mathrm{f}}$ value was 1.173 V, and the $V_{\mathrm{t},\mathrm{o}\mathrm{n}}$ value was 0.762 V, yielding a PGE of 0.411 [$∆\mathrm{V}$]. This indicates a reduction in the PGE of approximately 5.04% due to the addition of the oxide.

Table 3. Difference in PGE and threshold voltage with and without buried oxide.

Structure	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{f}\mathbf{f}}\left[\mathbf{V}\right]$	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{n}}\left[\mathbf{V}\right]$	$\mathbf{PGE} [∆\mathbf{V}]$
Without buried oxide	1.269	0.837	0.433
With buried oxide (initial value)	1.173	0.762	0.411

shows the differences in PGE and V_th with and without buried oxide, and Figure 5 shows the PGE difference with and without the buried oxide.

When voltage is applied to the FPWL, it enters the on state, forming an electric field that lowers the energy band of the AWL, thereby reducing the threshold voltage. The addition of buried oxide restricts the channel area formed in the AWL, thereby strengthening gate control. This effect contributes to the reduction in threshold voltage, which is a key mechanism for mitigating the PGE.

As previously mentioned, we attempted to carry out modifications to find the optimized form of the oxide. Adjusting D_bo, W_bo, and T_bo all led to a reduction in the PGE. Among these, adjusting D_bo resulted in the highest reduction rate per step, followed by increasing T_bo and W_bo. For D_bo, starting from the initial buried oxide value of 18 nm with a PGE value of 0.411 [ΔV] and reducing the distance to 6 nm resulted in a decrease to 0.390 [ΔV]; this represents a 5.11% reduction in the PGE. Similarly, the reduction rates observed when modifying T_bo and W_bo were 4.14% and 3.65%, respectively. In all cases, the reduction trend was nearly linear, highlighting the importance of positioning the oxide layer at an optimal size and location to achieve significant PGE reduction while maintaining manageable fabrication complexity.

Table 4. Threshold voltage and PGE values when adjusting the parameters of the buried oxide.

Dbo [nm]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{f}\mathbf{f}}$ [V]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{n}}$ [V]	PGE ∆[V]
22	1.184	0.767	0.417
18 (initial value)	1.173	0.762	0.411
14	1.160	0.755	0.405
10	1.146	0.749	0.397
6	1.131	0.741	0.390
Tbo [nm]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{f}\mathbf{f}}$ [V]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{n}}$ [V]	PGE ∆[V]
30 (initial value)	1.173	0.762	0.411
34	1.161	0.755	0.406
38	1.148	0.745	0.402
42	1.135	0.737	0.398
46	1.123	0.729	0.394
Wbo [nm]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{f}\mathbf{f}}$ [V]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{n}}$ [V]	PGE ∆[V]
28 (initial value)	1.173	0.762	0.411
32	1.156	0.751	0.405
36	1.141	0.739	0.402
40	1.127	0.728	0.399
44	1.113	0.717	0.396

shows the V_t,off, V_t,on, and PGE values when adjusting the parameters of the buried oxide, while Figure 6 presents a graph illustrating the trend of PGE values based on the changes in the buried oxide parameters.

Various modifications to the buried oxide further increase this gate control, although further research is needed to fully understand the underlying causes. If the exact cause of PGE reduction is identified, a more optimized form of the buried oxide can be developed.

As expected, the results from adding interface traps showed an increase in the PGE. When the trap density ranged from 10¹⁰ to 10¹¹ [cm⁻²], the PGE value showed a slight increase from 0.4112 to 0.4118 [ΔV]. However, within the 10¹¹ to 10¹² [cm⁻²] range, the PGE value sharply increased from 0.4118 to 0.4385 [ΔV]. This suggests that while a certain level of traps can be ignored, it is crucial to eliminate traps beyond a certain threshold to maintain the effectiveness of the buried oxide in mitigating PGE.

Table 5. Threshold voltage and PGE values when adjusting the interface trap density of the buried oxide.

Interface Trap Density [cm−2]	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{f}\mathbf{f}}\left[\mathbf{V}\right]$	${\mathit{V}}_{\mathbf{t},\mathbf{o}\mathbf{n}}\left[\mathbf{V}\right]$	$\mathbf{PGE} [∆\mathbf{V}]$
No trap (initial value)	1.1730	0.7620	0.4110
1 × 1010	1.1689	0.7577	0.4112
3 × 1010	1.1605	0.7492	0.4113
5 × 1010	1.1520	0.7407	0.4113
7 × 1010	1.1435	0.7320	0.4115
9 × 1010	1.1351	0.7234	0.4117
1 × 1011	1.1311	0.7193	0.4118
3 × 1011	1.0492	0.6339	0.4153
5 × 1011	0.9710	0.5494	0.4216
7 × 1011	0.8973	0.4653	0.4320
9 × 1011	0.8292	0.3908	0.4385

shows the V_t,off, V_t,on, and PGE values based on the interface trap density of the buried oxide, while Figure 7 graphically represents the trend of PGE values as the interface trap density of the buried oxide. The reason PGE increases with trap concentration is that, as trap concentration increases, gate controllability decreases; this leads to a significant influence from adjacent word lines. When the trap concentration increases above 10¹¹ [cm⁻²], the PGE rises abruptly, indicating that the trap density should be kept below 10¹¹ [cm⁻²].

4. Conclusions

In this study, we simulated a structure in which an oxide layer was buried beneath the AWL to reduce the PGE occurring in DRAM. To find the optimal oxide configuration, various modifications were tested. Among them, reducing the distance between the AWL and the oxide showed the highest PGE reduction rate, followed by increasing T_bo and widening W_bo. The trend of PGE reduction was nearly linear, emphasizing the importance of selecting the appropriate size and location for the oxide layer. Additionally, the results demonstrated that increasing the density of interface traps leads to a corresponding increase in the PGE, underscoring the importance of eliminating traps during the fabrication of such structures. The results confirmed that the buried demonstrates a significant reduction in the PGE.