A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

Abstract

Towards the integration of Digital-LDO regulators in the ultra-low-power System-On-Chip Internet-of-Things architecture, the D-LDO architecture should constitute the main regulator for powering digital and mixed-signal loads including the SoC system clock. Such an implementation requires an in-regulator clock generation unit that provides an autonomous D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the oscillating frequency, this work presents a design with nano-power consumption, fabricated with an active area of 0.035 $\mathrm{m}{\mathrm{m}}^2$ at a 55-nm Global Foundries CMOS process that introduces a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of D-LDO frequency. In combination with linear search coarse regulation and asynchronous fine regulation, it succeeds 558 nA minimum quiescent current with $C_L$ 75 pF, maximum current efficiency of 99.2% and 1.16x power efficiency improvement compared to analog counterpart oriented to SoC-IoT loads.

1. Introduction

With recent advances in System-on-Chip (SoC) architecture in the context of Internet-of-Things (IoT) devices, a need for autonomous devices that can be powered by harvesting the energy from outside sources has arisen [1]. One possibility is to use the query signal as the power source, such as in Ultra-High-Frequency Radio Frequency Identification (UHF-RFID). For these autonomous devices to work with such a low amount of available power, they need highly efficient power management. A key component of such SoC-IoT applications is the Low Drop-Out regulator (LDO). LDOs are DC voltage regulators that regulate the output voltage even when it is close to supply output voltage, which is the case in sub-1 V general IoT [2,3] and passive radio communication systems. In such a system as seen in Figure 1, the power efficiency is maximized with the minimization of the drop-out voltage which is defined as the difference from the rectified voltage to the power line voltage. Conventional Digital-LDO architectures (D-LDO) show-off drop-out voltage as low as 50 $\mathrm{m}\mathrm{V}$ at 0.5 $\mathrm{V}$ regulation voltage that offers a significant advantage compared to analog-LDOs [4] that are incapable of supporting comparable drop-out voltage in ultra-low-power and ultra-low-voltage specifications. In combination with state-of-the-art bandgap voltage references [5,6,7,8] that operate down to 0.5 V opens-up the perspective of operating the system at sub-1 V voltage with high efficiency.

At IoT applications, voltage regulators condition the incoming power from the energy scavenger unit and power digital loads such as the SoC system oscillator. In the prospect of a D-LDO, which constitutes the main regulator at an ultra-low-power IoT system as demonstrated in Figure 1, D-LDO should have an optimized design in order to be independent of external oscillator units such that is able to wake-up and power the system including the system clock. Consequently, the clock generation unit should be included in the D-LDO design. In contrast to conventional D-LDO architectures [9,10,11] as well as the hybrid schemes [12] that are oriented for high efficient regulation at sub-watt applications, there is limited literature available on D-LDO designs applicable to ultra-low power IoT systems by implementing integrated oscillator [13,14,15]. Such integration offers the advantage that coarse and fine regulation is not dependent on the operation of an external clock generation unit. Ring-oscillators are the main architectures that these designs use. A design that employs an integrated ring-oscillator and adapts the sampling frequency across a wide load range has been previously presented [13]. Furthermore, a D-LDO design with event-driven, self-triggering control that has been presented in [14] is based on an architecture that employs an Analog-to-Digital Converter (ADC) with multiple asynchronous comparators, a Proportional-Integrator controller, and burst current-starved ring-oscillator. Additionally, the architecture presented in [15] is based on binary-search coarse regulation and linear search fine regulation supported by an ultra-low frequency ring-oscillator that operates the synchronous fine regulation as well as charge-pump assisted transient comparators. In contrast to the aforementioned designs, this work presents a D-LDO regulator dedicated to ultra-low-power SoC-IoT that introduces an optimized instant pulse clock generation unit based on a high-gain latch stage. This specific configuration provides instant response to load disturbance independent of the D-LDO clock frequency as well as shows off a power efficiency improvement of 1.16x compared to analog-LDO rated for similar IoT loads [4].

2. Proposed Architecture

With the purpose to meet the SoC-IoT specifications as described, the proposed D-LDO is designed with fine regulation performed in asynchronous scheme, and synchronous coarse regulation assisted with burst-operated oscillator. Commonly used cold start-up operation of a ring-oscillator relies on charging and discharging of consecutive delay stages [16], thus the burst-clock response $t_b$ naturally depends on the oscillator frequency $T_{CLK}$ ($t_b\propto T_{CLK}$) as illustrated in Figure 2. In contrast, the presented oscillator is based on a multi-vibrator design assisted by a latched comparator accompanied by an appropriate wake-up circuit which triggers the serial shifter with delay independent of the oscillator frequency. As shown in Figure 2, with the purpose to perform load regulation, the system incorporates the control logic block that controls the current state which is alternated between fine and coarse regulation in case of load surge. The control logic unit produces the EN and LR signals that control the ignition of the oscillator and the direction of serial shifter respectively in the case of coarse regulation, while Comp 1 comparator regulates the load with delay hysteresis under fine regulation. $Q_C$ pMOS devices correspond to coarse regulation while $Q_F$ pMOS device to fine regulation as operated from Comp 1 comparator.

As previously stated, in comparison with current-starved ring-oscillators, a multi-vibrator provided with a latch comparator offers a higher gain with fewer stages consequently, the wake-up process becomes faster. Figure 3a illustrates the oscillator unit that provides the burst-clock generation. While signal EN is set to low, as seen in Figure 3b, at fine regulation, the capacitance $C_{OSC}$ is decoupled from the multiplexer. With the purpose to minimize the charge injection into the $C_{OSC}$ capacitor a transmission gate is used that holds the $V_C$ signal steady. Meanwhile, the output of the latched comparator Comp 2 is set to low. As EN is pulled up by the control logic when it detects either over-voltage or voltage droop, an edge detector detects the falling edge of the signal and sets the CHRG signal low. The latched comparator is equipped with a branch that sources current to one side of the latch connected to nMOS $Q_1$ device and another that drains current from the other side connected to nMOS device $Q_2$, thus the wake-up procedure triggers the latch differentially. As the voltage at the gates of $Q_1$ and $Q_2$ varies inversely proportional and surpasses differentially the threshold set by certain latch sizing [17], the output OUTA is charged. When the circuitry is latched, the negative edge of CLK output is triggered as well. As the multiplexer selects the current sink, $V_C$ decreases, and the capacitance $C_{OSC}$ starts to discharge which means that the oscillations begin. The CHRG signal remains low until the propagation delay of $\overline{CLK}$ signal set it to high. Therefore, the CHRG signal remains low for a time span irrelevant to the oscillation period. Consequently, burst oscillation responds within $t_b$ time under load current surge that is independent of the oscillator frequency. The oscillation period is defined predominately by the Comp 2 hysteresis levels $Vtr{p}_{+}$ and $Vtr{p}_{-}$, $C_{OSC}$ capacitance and $I_{OSC}$ parameter as seen in Equation (1).

$$T_{CLK}=2\ast C_{osc}·\frac{Vtr{p}_{+}-Vtr{p}_{-}}{I_{osc}}$$

(1)

The block diagram of the control logic is illustrated at Figure 4. The comparators Comp 3 and Comp 4 as shown are controlled by voltages $V_L$ and $V_H$ respectively, that define the droop and over-voltage detection thresholds. Each comparator Comp 3 and Comp 4 feeds Set-Reset latches with the signals DET_LOW and DET_UP respectively, and pull up each of them in case of a triggering event. Comparator Comp 1, which is responsible for the hysteretic fine regulation of the output, resets the latches that correspond to Comp 3 and Comp 4 when the coarse regulation converges after a droop or over-voltage recovery. The OR-Gate pulls up the EN signal in case of a droop or over-voltage while EN remains pulled down during fine regulation. The shifting direction is determined through the output of an additional SR latch that is set with the DET_LOW signal and is reset by DET_UP signal. Comp 1 has been implemented as a four-stage comparator that incorporates a differential pair, latch, preamplifier, and a push-pull final stage while Comp 3 and Comp 4 are realized via two-stage latch-based comparators.

Figure 5 illustrates the detailed timing diagram alongside with the system response under voltage droop and over-voltage. As droop happens in Figure 5a, EN signal is set by DET_LOW and coarse regulation is ignited with CLK negative edge after the $t_d=t_c+t_b$ delay that depends on the comparator Comp 3 and oscillator start-up delay, $t_c$ and $t_b$ respectively. As seen, after the comparator $t_c$ delay the EN signal is set and output of the comparator Comp2 (OUTA) is charged. As the comparator output surpasses the inverter trip point, the CLK signal is dropped and the oscillations begin soon after where the oscillator wake-up time interval ($t_b$) ends. The CHRG is reset to high state as the clock signal CLK is dropped to LOW. As the clock generation begins, the shift register activates each bit successively and the voltage droop is tamed. When the $V_{ref}+e$ voltage level is reached, where e is the offset from the reference of the output voltage due to comparison delay, the latch connected to Comp 3 is reset by signal $QF$ and EN signal is set to low. Since the DET_UP remains low and $\overline{QF}$ is low as well, the upper SR latch remains in the previous reset state. That ceases the coarse regulation and fine regulation takes place with ripple magnitude defined merely by the comparison delay of the comparator Comp 3. A similar operation is performed in case of over-voltage as seen in Figure 5b.

3. Implementation and Methodology

A 9-bit D-LDO was implemented in an active area of 0.035 $\mathrm{m}\mathrm{m}$${}^2$ at a 55-nm general-purpose Global Foundries CMOS process. The implementation also includes a digital controlled current source load and a 75 $\mathrm{p}\mathrm{F}$ load capacitance. Figure 6 illustrates the die photo of the implemented design.

The assessment of the performance of the load regulation in terms of transient performance is performed with the aid of Figure-Of-Merit [15], described in (2), which suits to ultra-low-power applications.

$$FOM=\frac{I_Q}{I_{tr}}·\frac{∆V_{tr}}{V_{OUT}}·C_L$$

(2)

In case that a design is implemented in an incomparable process, FOM scaling is performed to 55 $\mathrm{n}\mathrm{m}$ according to (3)

$$FO{M}_{norm}=DesignFOM·\frac{55\mathrm{n}\mathrm{m}}{DesignProcess}$$

(3)

which allows the equal assessment among the designs. The measurements were performed with wafer probes at probe station chamber under constant temperature of 28 ${}^{\circ }$C. Figure 7 illustrates the measurement setup. As shown, the reference signals $V_H$, $V_L$, $V_{ref}$ are produced externally, while the $V_{DD}$, $V_{DDEXT}$, $V_{DDREG}$ signals power the system, the digital load and feed the regulated output respectively. Meanwhile, D bus controls the digital selection of specific current load.

4. Measurements Results

With $V_{DDREG}=0.55\mathrm{V}$ and $V_{DD}=0.55\mathrm{V}$, the quiescent current was measured and it varies from 558 $\mathrm{n}\mathrm{A}$ to 621 $\mathrm{n}\mathrm{A}$ for load current of 764 $\mathrm{n}\mathrm{A}$ to 73.9 $\mathsf{\mu }\mathrm{A}$. To elaborate more, the off-state quiescent current of the oscillator consumes 8% of the total minimum quiescent current, Comp 3 and Comp 4 50%, Comp 1 27% while the remaining 15% is distributed to the voltage divider, power-on-reset circuit, current distribution circuitry, and leakage current of the control circuitry. The reference $V_{ref}$ of output regulation voltage is fixed at 0.5 V during measurements such that maximum power efficiency is achieved for given drop-out voltage and load current. Figure 8 illustrates the steady-state measurements of the current efficiency and voltage regulation. As illustrated, the maximum load regulation comes at 528 $\mathrm{m}\mathrm{V}$/$\mathrm{m}\mathrm{A}$ and maximum line regulation of 120 mV/V was observed. As seen at Figure 9, for current load more than 15.9 $\mathsf{\mu }\mathrm{A}$, the minimum measured efficiency is 96.2% while the maximum value reaches 99.2%. The maximum value of power efficiency is 88.5%, which is higher than 76% as reported for SoC-IoT-oriented analog LDO [4]. Hybrid implementation of the regulator as presented in [12] combines inductor-based switching regulator with D-LDO and naturally shows off higher power efficiency of 94%. However, higher efficiency comes at the expense of higher power consumption of 30.5 $\mathsf{\mu }\mathrm{A}$ total system quiescent current.

Figure 10 illustrates the transient response of the implemented regulator under load surge that alternates between 764 $\mathrm{n}\mathrm{A}$ and 73.9 $\mathsf{\mu }\mathrm{A}$. We measured 156 mV droop with load step 4 $\mathrm{n}\mathrm{s}$ from 764 $\mathrm{n}\mathrm{A}$ to 73 $\mathsf{\mu }\mathrm{A}$ current load surge. As load step happens, the multi-vibrator ”wakes-up” and ”forces” negative clock edge within $t_d$ 600 ns of total system response. The clock period is 4 $\mathsf{\mu }\mathrm{s}$ while the settling time 20 $\mathsf{\mu }\mathrm{s}$.

Table 1. Comparison with prior-art D-LDOs.

	[10]	[9]	[13]	[15]	[14]	This Work
Process	65 $\mathrm{n}\mathrm{m}$	22 $\mathrm{n}\mathrm{m}$	130 $\mathrm{n}\mathrm{m}$	65 $\mathrm{n}\mathrm{m}$	65 $\mathrm{n}\mathrm{m}$	55 $\mathrm{n}\mathrm{m}$
Control	PD	DVFS	ASF	ABS/SLS	ED PI	ED NLC
Oscillator	W/O	W/O	INT.	INT.	INT.	INT.
Active Area [$\mathrm{m}{\mathrm{m}}^2$]	0.0023	0.165	0.114	0.048	0.0057	0.035
Vin [V]	0.5–1	0.55–1.2	0.5–1.2	0.5–1	0.45–1	0.55–0.7
Vout [V]	0.3–0.45	0.5–1.15	0.45–1.14	0.4–0.95	0.4–0.95	0.5
$I_L$ Range	100 $\mathrm{n}\mathrm{A}$– 2 $\mathrm{m}\mathrm{A}$	400 $\mathsf{\mu }\mathrm{A}$– 2 $\mathrm{A}$	100 $\mathsf{\mu }\mathrm{A}$– 4.6 $\mathrm{m}\mathrm{A}$	710 pA– 0.27 $\mathrm{m}\mathrm{A}$	15 $\mathsf{\mu }\mathrm{A}$– 5.6 $\mathrm{m}\mathrm{A}$	0.5 $\mathsf{\mu }\mathrm{A}$– 80 $\mathsf{\mu }\mathrm{A}$
$C_L$[$\mathrm{n}\mathrm{F}$]	0.4	7	1 ext.	100 ext.	0.1	0.075
$I_Q$	14 $\mathsf{\mu }\mathrm{A}$	2.4 $\mathrm{m}\mathrm{A}$	20–751 $\mathsf{\mu }\mathrm{A}$	745 $\mathrm{p}\mathrm{A}$	18.1 $\mathsf{\mu }\mathrm{A}$	0.56 $\mathsf{\mu }\mathrm{A}$
Ripple [$\mathrm{m}\mathrm{V}$]	N/R	N/R	10–70	2	N/R	40–50
Settling. time, Tr. test	100 $\mathrm{n}\mathrm{s}$	N/R	N/R	48 $\mathsf{\mu }\mathrm{s}$	1 $\mathsf{\mu }\mathrm{s}$	20 $\mathsf{\mu }\mathrm{s}$
$V_{tr}$ @$I_{tr}$, Tr. test	40 $\mathrm{m}\mathrm{V}$ @ 1.06 $\mathrm{m}\mathrm{A}$	100 $\mathrm{m}\mathrm{V}$ @ 0.5 $\mathrm{A}$	40 $\mathrm{m}\mathrm{V}$ @ 0.7 $\mathrm{m}\mathrm{A}$	76.5 $\mathrm{m}\mathrm{V}$ @ 0.27 $\mathrm{m}\mathrm{A}$	49.8 $\mathrm{m}\mathrm{V}$ @ 2.3 $\mathrm{m}\mathrm{A}$	150 $\mathrm{m}\mathrm{V}$ @ 73 $\mathsf{\mu }\mathrm{A}$
Load step, Tr. test	<1 $\mathrm{n}\mathrm{s}$	250 $\mathrm{p}\mathrm{s}$	N/R	500 ns	0.1 $\mathrm{n}\mathrm{s}$	4 $\mathrm{n}\mathrm{s}$
FOM [$\mathrm{p}\mathrm{F}$], Tr. test	0.469	9.3 *	4.3 *	0.049	0.086	0.175

* Normalization is performed as explained in Section 3.

shows the performance comparison of the proposed design with prior D-LDO implementations. Architectures that employ adaptive controllers as presented by [9,11,13] are based on adaptive sampling frequency for faster regulation. However, among them, architectures that employ complex digital computational units [9,11] occupy a larger active area of 0.057 $\mathrm{m}\mathrm{m}$${}^2$ and 0.165 $\mathrm{m}\mathrm{m}$${}^2$ respectively. In terms of FOM comparison, dynamic frequency scaling architectures [9,13] lack behind the rest. Moreover, it is observed that the transient test of [15] has been performed with 500 $\mathrm{n}\mathrm{s}$ load step that compared to 4 $\mathrm{n}\mathrm{s}$ of this work is 125 times slower while the FOM of this work remains 3.5 times bigger than the presented transient test at [15]. Furthermore, the FOM as achieved in [14] is naturally less than the FOM presented in Figure 10 as it uses state-of-the-art self-biased comparators in contrast to conventional comparators of this work.

5. Conclusions

A D-LDO that constitutes the main regulator of an ultra-low-power and ultra-low-voltage SoC-IoT application should incorporate an integrated clock generation unit. To fulfill this requirement, we propose a D-LDO design aimed at micro-power IoT systems that is based on a burst oscillator that offers instant response under transient load. In contrast to ring-oscillator-based topologies, the event response of the proposed burst oscillator is not constrained by the system design specification of the operational frequency. The D-LDO regulator as implemented shows off 558 $\mathrm{n}\mathrm{A}$ minimum quiescent current and 99.2% maximum current efficiency with a 1.16x improvement of power efficiency compared to analog-LDO oriented to ultra-low-power IoT loads.