Journal of Low Power Electronics and Applications

15 pages, 7333 KiB

Open AccessArticle

0.7 V Supply SC Circuits with Relaxed Slew Rate Requirements Using GB-Enhanced Multiple-Output Class AB/AB Op-Amps

by Hector Daniel Rico-Aniles, Anindita Paul, Jaime Ramirez-Angulo, Antonio Lopez-Martin and Ramon G. Carvajal

J. Low Power Electron. Appl. 2025, 15(2), 24; https://doi.org/10.3390/jlpea15020024 - 15 Apr 2025

Abstract

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature [...] Read more.

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature essentially relaxes the op-amp slew rate requirements, allowing a higher speed and simple low-voltage operation. A power-efficient GB boosting technique based on resistive local common mode feedback is used to significantly improve the GB and internal/external slew rate of the op-amps with only a 36.5% additional power dissipation. Full article

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17 pages, 6539 KiB

Open AccessArticle

Charge Pump Phase-Locked Loop-Based Frequency Conditioning of a MEMS Resonator

by Xinyuan Hu and Yanfeng Jiang

J. Low Power Electron. Appl. 2025, 15(2), 23; https://doi.org/10.3390/jlpea15020023 - 12 Apr 2025

Abstract

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked [...] Read more.

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked loop-based frequency conditioning method for MEMS resonators is explored. An optimization scheme is proposed to enhance the frequency stability and signal quality of MEMS resonators. The experimental results show that the method significantly improves the resonator performance and achieves effective control of the resonant frequency. This research provides a new technical path for the design of high-performance MEMS oscillators, which has important theoretical significance and practical application value. Full article

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17 pages, 2374 KiB

Open AccessArticle

A Lightweight and Configurable Flash Filesystem for Low-Power Devices

by Ondrej Kachman, Peter Malík, Marcel Baláž, Libor Majer and Gábor Gyepes

J. Low Power Electron. Appl. 2025, 15(2), 22; https://doi.org/10.3390/jlpea15020022 - 11 Apr 2025

Abstract

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient [...] Read more.

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization, minimize flash wear, and support portability across hardware platforms and operating systems. Reliability mechanisms integrated into CFFS are also discussed. We compare CFFS with widely used low-power embedded filesystems—LittleFS, SPIFFS, and FDS—highlighting its advantages in memory efficiency and reduced flash memory wear. Experimental results demonstrate that CFFS achieves up to 99% memory utilization while significantly reducing erase operations. Full article

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15 pages, 3377 KiB

Open AccessArticle

Machine Learning Using Approximate Computing

by Padmanabhan Balasubramanian, Syed Mohammed Mosayeeb Al Hady Zaheen and Douglas L. Maskell

J. Low Power Electron. Appl. 2025, 15(2), 21; https://doi.org/10.3390/jlpea15020021 - 9 Apr 2025

Abstract

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means [...] Read more.

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means clustering, one of the more widely used unsupervised machine learning algorithms. The k-means algorithm partitions data into k clusters, where k also denotes the number of centroids, with each centroid representing the center of a cluster. The clustering process involves assigning each data point to the nearest centroid by minimizing the within-cluster sum of squares (WCSS), a key metric used to evaluate clustering quality. A lower WCSS value signifies better clustering. Conventionally, WCSS is computed with high precision using an accurate adder. In this paper, we investigate the impact of employing various approximate adders for WCSS computation and compare their results against those obtained with an accurate adder. Further, we propose a new approximate adder (NAA) in this paper. To assess its effectiveness, we utilize it for the k-means clustering of some publicly available artificial datasets with varying levels of complexity, and compare its performance with the accurate adder and many other approximate adders. The experimental results confirm the efficacy of NAA in clustering, as NAA yields WCSS values that closely match or are identical to those obtained using the accurate adder. We also implemented hardware designs of accurate and approximate adders using a 28 nm CMOS standard cell library. The design metrics estimated show that NAA achieves a 37% reduction in delay, a 22% reduction in area, and a 31% reduction in power compared to the accurate adder. In terms of the power-delay product that serves as a representative metric for energy efficiency, NAA reports a 57% reduction compared to the accurate adder. In terms of the area-delay product that serves as a representative metric for design efficiency, NAA reports a 51% reduction compared to the accurate adder. NAA also outperforms several existing approximate adders in terms of design metrics while preserving clustering effectiveness. Full article

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13 pages, 6647 KiB

Open AccessArticle

A Power-Efficient 50 MHz-BW 76.8 dB Signal-to-Noise-and-Distortion Ratio Continuous-Time 2-2 MASH Delta-Sigma Analog-to-Digital Converter with Digital Calibration

by Zhiyu Li, Xueqian Shang, Haigang Feng and Xinpeng Xing

J. Low Power Electron. Appl. 2025, 15(2), 20; https://doi.org/10.3390/jlpea15020020 - 9 Apr 2025

Abstract

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for [...] Read more.

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB. Full article

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22 pages, 10817 KiB

Open AccessArticle

Energy Saving in Wireless Sensor Networks via LEACH-Based, Energy-Efficient Routing Protocols

by Georgios Siamantas, Dimitris Rountos and Dionisis Kandris

J. Low Power Electron. Appl. 2025, 15(2), 19; https://doi.org/10.3390/jlpea15020019 - 29 Mar 2025

Cited by 1

Abstract

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of [...] Read more.

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of sensor nodes is pursued in various ways. One of them is the usage of protocols that achieve energy-efficient routing. LEACH is one of the pioneering protocols of this type and has numerous descendants. This research article focuses on energy-efficient routing protocols that are based on LEACH. Specifically, a study of LEACH along with many of its successors is provided. In addition, a novel protocol of this kind, named T-LEACH_SAS is introduced. This protocol combines the threshold-based approach for selecting cluster heads that was first introduced in T-LEACH, which is a well-known protocol, along with a mechanism for sleep–awake scheduling. The performance of T-LEACH_SAS is compared against that of both LEACH and T-LEACH via simulation tests that confirm that T-LEACH_SAS indeed provides a promising choice for energy-efficient routing in WSNs. Full article

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13 pages, 72870 KiB

Open AccessArticle

Compact High-Scanning Rate Frequency Scanning Antenna Based on Composite Right/Left-Handed Transmission Line

by Zongrui He, Kaijun Song, Jia Yao and Yedi Zhou

J. Low Power Electron. Appl. 2025, 15(2), 18; https://doi.org/10.3390/jlpea15020018 - 28 Mar 2025

Abstract

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches [...] Read more.

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches is employed, whose second mode exhibits excellent transmission characteristics. The measurements demonstrate that the antenna can achieve scanning from −67.5° to 35.5° in the frequency band range of 5.65–6.5 GHz, with a scanning rate of 7.3. During scanning, the highest gain in the band is 12.3 dBi, the lowest is 10 dBi, and the gain fluctuation is within 2.3 dB, showing good scanning characteristics. Additionally, the length of the proposed antenna is approximately 3.84λ₀ for a central frequency of 5.95 GHz. Full article

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14 pages, 6516 KiB

Open AccessArticle

Junction Temperature Estimation Model of Power MOSFET Device Based on Photovoltaic Power Enhancer

by Ning Li, Shubin Zhang and Yanfeng Jiang

J. Low Power Electron. Appl. 2025, 15(2), 17; https://doi.org/10.3390/jlpea15020017 - 24 Mar 2025

Abstract

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the [...] Read more.

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the power device’s junction temperature is critical in the system design. To address this problem, a novel thermal behavior estimation model based on electro-thermal analysis is proposed in this paper, which can be used for asymmetric power MOSFETs in a photovoltaic power enhancer system. Thermal coupling effects and dissipative boundary conditions are, firstly, analyzed in a three-dimensional finite element model. A coupling impedance matrix is constructed through step power response extraction to describe the significant thermal coupling effects among devices. The complete heat sink is decoupled into several sub-parts representing different dissipative boundary conditions. A compact RC network model for estimating junction temperature is established based on the combination of the coupling impedance and the sub-heat-sink impedance. The proposed model is verified by finite element simulation and experimental measurement. Full article

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16 pages, 3892 KiB

Open AccessReview

2D Spintronics for Neuromorphic Computing with Scalability and Energy Efficiency

by Douglas Z. Plummer, Emily D’Alessandro, Aidan Burrowes, Joshua Fleischer, Alexander M. Heard and Yingying Wu

J. Low Power Electron. Appl. 2025, 15(2), 16; https://doi.org/10.3390/jlpea15020016 - 24 Mar 2025

Cited by 1

Abstract

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic [...] Read more.

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic computing, inspired by the biological brain, offers a transformative paradigm for addressing these challenges. This review paper provides an overview of advancements in 2D spintronics and device architectures designed for neuromorphic applications, with a focus on techniques such as spin-orbit torque, magnetic tunnel junctions, and skyrmions. Emerging van der Waals materials like CrI₃, Fe₃GaTe₂, and graphene-based heterostructures have demonstrated unparalleled potential for integrating memory and logic at the atomic scale. This work highlights technologies with ultra-low energy consumption (0.14 fJ/operation), high switching speeds (sub-nanosecond), and scalability to sub-20 nm footprints. It covers key material innovations and the role of spintronic effects in enabling compact, energy-efficient neuromorphic systems, providing a foundation for advancing scalable, next-generation computing architectures. Full article

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26 pages, 2271 KiB

Open AccessArticle

Hardware/Software Co-Design Optimization for Training Recurrent Neural Networks at the Edge

by Yicheng Zhang, Bojian Yin, Manil Dev Gomony, Henk Corporaal, Carsten Trinitis and Federico Corradi

J. Low Power Electron. Appl. 2025, 15(1), 15; https://doi.org/10.3390/jlpea15010015 - 11 Mar 2025

Abstract

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture [...] Read more.

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture recognition, which often necessitate the use of recurrent neural networks (RNNs). However, training RNNs on edge devices presents major challenges due to limited memory and computing resources. In this study, we propose a system for RNN training through sequence partitioning using the Forward Propagation Through Time (FPTT) training method, thereby enabling edge learning. Our optimized hardware/software co-design for FPTT represents a novel contribution in this domain. This research demonstrates the viability of FPTT for fine-tuning real-world applications by implementing a complete computational framework for training Long Short-Term Memory (LSTM) networks utilizing FPTT. Moreover, this work incorporates the optimization and exploration of a scalable digital hardware architecture using an open-source hardware-design framework, named Chipyard and its implementation on a Field-Programmable Gate Array (FPGA) for cycle-accurate verification. The empirical results demonstrate that partitioned training on the proposed architecture enables an 8.2-fold reduction in memory usage with only a 0.2× increase in latency for small-batch sequential MNIST (S-MNIST) compared to traditional non-partitioned training. Full article

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20 pages, 1710 KiB

Open AccessArticle

Design of Ultra-Low-Power Rail-to-Rail Input Common Mode Range Standard-Cell-Based Comparators

by Antonio Manno, Giuseppe Scotti and Gaetano Palumbo

J. Low Power Electron. Appl. 2025, 15(1), 14; https://doi.org/10.3390/jlpea15010014 - 8 Mar 2025

Abstract

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with [...] Read more.

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology. Full article

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11 pages, 1151 KiB

Open AccessArticle

Current-Mode Quadrature Oscillator Simple Designs

by Julia Nako, Costas Psychalinos and Shahram Minaei

J. Low Power Electron. Appl. 2025, 15(1), 13; https://doi.org/10.3390/jlpea15010013 - 7 Mar 2025

Abstract

Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm [...] Read more.

Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm the validity of the presented concept and show that the resulting structure has attractive characteristics in both frequency and time-domain. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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21 pages, 7139 KiB

Open AccessArticle

Investigation of Short Channel Effects in Al_0.30Ga_0.60As Channel-Based Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

by Pooja Srivastava, Aditi Upadhyaya, Shekhar Yadav, Chandra Mohan Singh Negi and Arvind Kumar Singh

J. Low Power Electron. Appl. 2025, 15(1), 12; https://doi.org/10.3390/jlpea15010012 - 21 Feb 2025

Abstract

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability [...] Read more.

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec. Full article

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11 pages, 6241 KiB

Open AccessArticle

Low-Level Kinetic-Energy-Powered Temperature Sensing System

by Ashaduzzaman, James M. Mangum, Syed M. Rahman, Tamzeed B. Amin, Md R. Kabir, Hung Do, Gordy Carichner, David Blaauw and Paul M. Thibado

J. Low Power Electron. Appl. 2025, 15(1), 11; https://doi.org/10.3390/jlpea15010011 - 13 Feb 2025

Abstract

Powering modern nanowatt sensors from omnipresent low-level kinetic energy: This study investigates the power levels produced by a varying-capacitance kinetic energy harvesting system. A model system consisting of a uniformly driven rotating capacitor was built to develop an accurate output power performance model. [...] Read more.

Powering modern nanowatt sensors from omnipresent low-level kinetic energy: This study investigates the power levels produced by a varying-capacitance kinetic energy harvesting system. A model system consisting of a uniformly driven rotating capacitor was built to develop an accurate output power performance model. We found a quantitative linear relationship between the rectified output current and the input applied bias voltage, driving frequency, and capacitance variation. We also demonstrate that our variable capacitor system is equivalent to a fixed capacitor driven with an alternating current power source. Both the fixed-capacitance and varying-capacitance energy harvesting systems recharge a three-volt battery, which in turn powers a custom ultralow-power-consuming temperature sensor system. Full article

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17 pages, 1231 KiB

Open AccessArticle

The REGALE Library: A DDS Interoperability Layer for the HPC PowerStack

by Giacomo Madella, Federico Tesser, Lluis Alonso, Julita Corbalan, Daniele Cesarini and Andrea Bartolini

J. Low Power Electron. Appl. 2025, 15(1), 10; https://doi.org/10.3390/jlpea15010010 - 12 Feb 2025

Abstract

Large-scale computing clusters have been the basis of scientific progress for several decades and have now become a commodity fuelling the AI revolution. Dark Silicon, energy efficiency, power consumption, and hot spots are no longer looming threats of an Information and Communication Technologies [...] Read more.

Large-scale computing clusters have been the basis of scientific progress for several decades and have now become a commodity fuelling the AI revolution. Dark Silicon, energy efficiency, power consumption, and hot spots are no longer looming threats of an Information and Communication Technologies (ICT) niche but are today the limiting factor of the capability of the entire human society and a contributor to global carbon emissions. However, from the end user, system administrators, and system integrator perspective, handling and optimising the system for these constraints is not straightforward due to the elevated degree of fragmentation in the software tools and interfaces which handles the power management in high-performance computing (HPC) clusters. In this paper, we present the REGALE Library. It is the result of a collaborative effort in the EU EuroHPC JU REGALE project, which aims to effectively materialize the HPC PowerStack initiative, providing a single layer of communication among different power management tools, libraries, and software. The proposed framework is based on the data distribution service (DDS) and real-time publish–subscribe (RTPS) protocols and FastDDS as their implementation. This enables the various actors in the ecosystem to communicate and exchange messages without any further modification inside their implementation. In this paper, we present the blueprint, functionality tests, and performance and scalability evaluation of the DDS implementation currently used in the REGALE Library in the HPC context. Full article

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12 pages, 3180 KiB

Open AccessArticle

Design and Analysis of a Novel 12-Bit Current-Steering–Capacitive Digital-to-Analog Converter

by Xian Yang Lim, Boon Chiat Terence Teo, Venkadasamy Navaneethan, Wu Cong Lim and Liter Siek

J. Low Power Electron. Appl. 2025, 15(1), 9; https://doi.org/10.3390/jlpea15010009 - 11 Feb 2025

Abstract

This article introduces a novel digital-to-analog converter (DAC), which addresses a few weaknesses that a traditional capacitive DAC (CDAC) has, such as matching and parasitic capacitance-induced code dependency and a challenging bridge capacitor design. Our novel idea is a hybrid DAC of a [...] Read more.

This article introduces a novel digital-to-analog converter (DAC), which addresses a few weaknesses that a traditional capacitive DAC (CDAC) has, such as matching and parasitic capacitance-induced code dependency and a challenging bridge capacitor design. Our novel idea is a hybrid DAC of a CDAC and a current-steering DAC (CSDAC) and is named the CSCDAC. In this paper, a 12-bit CSCDAC is designed, and the post-layout simulation is provided. The Nyquist 12-bit CSCDAC exhibits a spurious free dynamic range (SFDR) of 67.62 dB under an operating frequency of 2 GS/s, with an expected average power of 54 mW. The 12-bit CSCDAC occupies a 0.154 mm² die area, whereas the core area is 0.044 mm². Full article

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26 pages, 1186 KiB

Open AccessArticle

Optimizing BFloat16 Deployment of Tiny Transformers on Ultra-Low Power Extreme Edge SoCs

by Alberto Dequino, Luca Bompani, Luca Benini and Francesco Conti

J. Low Power Electron. Appl. 2025, 15(1), 8; https://doi.org/10.3390/jlpea15010008 - 5 Feb 2025

Abstract

Transformers have emerged as the central backbone architecture for modern generative AI. However, most ML applications targeting low-power, low-cost SoCs (TinyML apps) do not employ Transformers as these models are thought to be challenging to quantize and deploy on small devices. This work [...] Read more.

Transformers have emerged as the central backbone architecture for modern generative AI. However, most ML applications targeting low-power, low-cost SoCs (TinyML apps) do not employ Transformers as these models are thought to be challenging to quantize and deploy on small devices. This work proposes a methodology to reduce Transformer dimensions with an extensive pruning search. We exploit the intrinsic redundancy of these models to fit them on resource-constrained devices with a well-controlled accuracy tradeoff. We then propose an optimized library to deploy the reduced models using BFLoat16 with no accuracy loss on Commercial Off-The-Shelf (COTS) RISC-V multi-core micro-controllers, enabling the execution of these models at the extreme edge, without the need for complex and accuracy-critical quantization schemes. Our solution achieves up to

220 \times

speedup with respect to a naïve C port of the Multi-Head Self Attention PyTorch kernel: we reduced MobileBert and TinyViT memory footprint up to ∼94% and ∼57%, respectively, and we deployed a tinyLLAMA SLM on microcontroller, achieving a throughput of 1219 tokens/s with an average power of just 57 mW. Full article

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18 pages, 16317 KiB

Open AccessArticle

A Novel Low-Power Differential Input Current Summing Second-Generation Voltage Conveyor

by Riccardo Olivieri, Davide Colaiuda, Gianluca Barile, Vincenzo Stornelli and Giuseppe Ferri

J. Low Power Electron. Appl. 2025, 15(1), 7; https://doi.org/10.3390/jlpea15010007 - 29 Jan 2025

Abstract

This paper presents a novel transistor-level design of a modified second-generation voltage conveyor (VCII), which incorporates two differential current inputs (Y+ and Y−) and gives a voltage output at terminal X that mirrors the sum of these currents. The circuit operation is based [...] Read more.

This paper presents a novel transistor-level design of a modified second-generation voltage conveyor (VCII), which incorporates two differential current inputs (Y+ and Y−) and gives a voltage output at terminal X that mirrors the sum of these currents. The circuit operation is based on current mirrors that maintain the X terminal in a stable “quiescent” state when no differential current is applied at Y+ and Y−. When a current flows into one of the two inputs, the sum is mirrored into X, providing a summed current measurement. This design, developed in a standard 0.35 μm CMOS transistors technology, ensures circuit high accuracy and robustness. The low power consumption of 24.6 μW makes it well-suited for portable biomedical applications as in environmental fields. Full article

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25 pages, 7838 KiB

Open AccessArticle

Distributed Consensus Gossip-Based Data Fusion for Suppressing Incorrect Sensor Readings in Wireless Sensor Networks

by Martin Kenyeres, Jozef Kenyeres and Sepideh Hassankhani Dolatabadi

J. Low Power Electron. Appl. 2025, 15(1), 6; https://doi.org/10.3390/jlpea15010006 - 26 Jan 2025

Cited by 1

Abstract

Incorrect sensor readings can cause serious problems in Wireless Sensor Networks (WSNs), potentially disrupting the operation of the entire system. As shown in the literature, they can arise from various reasons; therefore, addressing this issue has been a significant challenge for the scientific [...] Read more.

Incorrect sensor readings can cause serious problems in Wireless Sensor Networks (WSNs), potentially disrupting the operation of the entire system. As shown in the literature, they can arise from various reasons; therefore, addressing this issue has been a significant challenge for the scientific community over the past few decades. In this paper, we examine the applicability of seven distributed consensus gossip-based algorithms for sensor fusion (namely, the Randomized Gossip algorithm, the Geographic Gossip algorithm, three initial configurations of the Broadcast Gossip algorithm, the Push-Sum protocol, and the Push-Pull protocol) to compensate for incorrect data in WSNs. More specifically, we consider a scenario where the sensor-measured data (measured by a set of independent sensor nodes) are skewed due to Gaussian noise with a various standard deviation

σ

, resulting in discrepancies between the measured values and the true value of observed physical quantities. Subsequently, the aforementioned algorithms are employed to mitigate this skewness in order to improve the accuracy of the measured data. In this paper, WSNs are modeled as random geometric graphs with various connectivity, and the performance of the algorithms is evaluated using two metrics (specifically, the mean square error (MSE) and the number of sent messages required for an algorithm to be completed). Based on the presented results, it is identified that all the examined algorithms can significantly suppress incorrect sensor readings (MSE without sensor fusion = −0.42 dB if

σ

= 1, and MSE without sensor fusion = 14.05 dB if

σ

= 5), and the best performance is achieved by PS in dense graphs and by GG in sparse graphs (both algorithms achieve the maximum precision MSE = −24.87 dB if

σ

= 1 and MSE = −21.02 dB if

σ

= 5). Additionally, the performance of the analyzed distributed consensus gossip algorithms is compared to the best deterministic consensus algorithm applied for the same purpose. Full article

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