Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

Mambu, Kévin; Charles, Henri-Pierre; Kooli, Maha; Dumas, Julie

doi:10.3390/jlpea12010018

Open AccessArticle

Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

CEA, LIST, Université Grenoble Alpes, F-38000 Grenoble, France

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J. Low Power Electron. Appl. 2022, 12(1), 18; https://doi.org/10.3390/jlpea12010018

Submission received: 15 December 2021 / Revised: 1 February 2022 / Accepted: 14 February 2022 / Published: 16 March 2022

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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Abstract

In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by the memory wall. However, it does not address the energy wall problem caused by data transfer over memory hierarchies. This paper proposes the data-locality management unit (DMU) to efficiently transfer data from a DRAM memory to a computational SRAM (C-SRAM) memory allowing IMC operations. The DMU is tightly coupled within the C-SRAM and allows one to align the data structure in order to perform effective in-memory computation. We propose a dedicated instruction set within the DMU to issue data transfers. The performance evaluation of a system integrating C-SRAM within the DMU compared to a reference scalar system architecture shows an increase from

\times 5.73

to

\times 11.01

in speed-up and from

\times 29.49

to

\times 46.67

in energy reduction, versus a system integrating C-SRAM without any transfer mechanism compared to a reference scalar system architecture.

Keywords: in-memory computing; energy modeling; non-von neumann; instruction set; compilation; stencils; convolutions; sram; energy wall; memory wall

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MDPI and ACS Style

Mambu, K.; Charles, H.-P.; Kooli, M.; Dumas, J. Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM. J. Low Power Electron. Appl. 2022, 12, 18. https://doi.org/10.3390/jlpea12010018

AMA Style

Mambu K, Charles H-P, Kooli M, Dumas J. Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM. Journal of Low Power Electronics and Applications. 2022; 12(1):18. https://doi.org/10.3390/jlpea12010018

Chicago/Turabian Style

Mambu, Kévin, Henri-Pierre Charles, Maha Kooli, and Julie Dumas. 2022. "Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM" Journal of Low Power Electronics and Applications 12, no. 1: 18. https://doi.org/10.3390/jlpea12010018

APA Style

Mambu, K., Charles, H.-P., Kooli, M., & Dumas, J. (2022). Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM. Journal of Low Power Electronics and Applications, 12(1), 18. https://doi.org/10.3390/jlpea12010018

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

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Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

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