Ultra-Low-Power Circuits for Intermittent Communication
Abstract
:1. Introduction
1.1. The world of Batteryless Devices
1.2. Challenges of Intermittent Communication
1.3. Contributions
2. Related Works
2.1. Ultra Low-Power Communication Techniques
2.1.1. Radio Frequency Backscatter
2.1.2. Visible Light Communication (VLC)
2.2. Protocols for Reliable Batteryless Communication
3. Circuits Supporting Reliable Intermittent Communications
3.1. Automodulator
- An analog stage that samples the capacitor voltage through the VCAP signal and discretizes it into four different levels represented by three digital signals;
- A logic combination circuit that uses the information provided by the analog stage and, when triggered, starts producing the modulation signal VMOD for the energy status RF backscatter communication;
- An ultra-low-power and low-frequency oscillator (CLOCK) that provides the modulation frequency upon which the logic combiner constructs the modulation signal.
- Externally, the backscatter front end (visible in Figure 4), which provides access to the RF backscatter channel for the modulation signal and retrieves the neighboring node’s energy status information, providing a digital output VREC used by the node system to enable the protocol operations.
3.2. Synchronizer
3.3. Digital Decoding
- First, in the case of VLC synchronization, the trigger signal prompts the MCU to synchronize with the new incoming energy status update cycle;
- The backscatter front-end digital output VREC interrupts the microcontroller and represents the demodulated energy status burst received from a neighbor in the specific time slot;
- The microcontroller accumulates the bits and forms the transmitted energy status burst;
- Considering the duration of the burst, the microcontroller decodes the energy status and, if needed, decides to transmit data to the selected neighbor, avoiding packet losses due to power failures.
4. Results
- The sync signal represents the synchronization pulse given by the analog comparator of node 1. In the specific presented scenario, a synchronization event appears every 100 ms;
- VREC1 represents the received and demodulated bursts shared on the backscatter on the first node;
- VMOD1 represents the modulation signal on node 1. The updated energy status period is set to 50 ms (i.e., two bursts per each synchronization period);
- VMOD2 represents the modulation signal on node 2, the same for node 1;
- VC represents the node 1 synchronizer capacitor voltage responsible for the delay generation after the synchronization event;
- Trigger represents the node 1 trigger signal that fires the automodulator operation with two edges.
- First, a synchronization event is received (Sync pulse) by both nodes and starts the energy status update process.
- On node 1, the synchronizer timing capacitor starts charging (voltage VC increases), and the SR latch produces the first trigger event delayed by roughly 10 ms. Node 1 is fully charged and transmits over the backscatter channel, with a long burst encoding its high energy level, which is visible on the VMOD1.
- The same process takes place for node 2, which is in a charging phase and transmits a medium energy level burst visible on the VMOD2. Thus, no data communication can start between the two nodes.
- The timing capacitor voltage VC decreases, and after roughly 50 ms, a second energy status update is triggered on node 1.
- At that energy update interval, both nodes are at high energy levels and transmit long bursts. Both nodes receive the bursts. This is visible on the VREC1 for node 1.
- After decoding the received energy status, secure data communication can start between the two nodes using the communication slot (which, in a typical application, can be even larger and cover different energy status updates as it uses a different radio).
- After the communication completes, energy is consumed, and both nodes return to low-energy statuses.
5. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Battery-Powered | Batteryless |
---|---|
Relatively high maintenance costs | Quasi-zero maintenance costs |
High disposal costs | Low disposal costs |
Relatively large weight and dimensions | Drastically reduced weight and dimensions |
Well-known energy budget | Limited and not constant energy budget |
Continuous operations | Intermittent operations |
Energy Level | Burst Pulses Length | Th 1 -2 -3 | Counter Outputs |
---|---|---|---|
Lowest | 32 | 0-0-0 | Q6 |
Mid-low | 64 | 1-0-0 | Q6-Q7 |
Mid-high | 128 | 1-1-0 | Q6-Q7-Q8 |
Highest | 256 | 1-1-1 | Q6-Q7-Q8-Q9 |
Block | Current [µA] | Power [µW] | |
---|---|---|---|
Automodulator | Logic core | 0.39 | 1.29 |
Low-frequency oscillator | 2.06 | 6.80 | |
Analog stage | 0.48 | 1.58 | |
Capacitor sense current | 0.25 | 0.83 | |
Synchronizer | Delay cell | 0.45 | 1.5 |
Overall | 3.63 | 12.0 |
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Torrisi, A.; Yıldırım, K.S.; Brunelli, D. Ultra-Low-Power Circuits for Intermittent Communication. J. Low Power Electron. Appl. 2022, 12, 60. https://doi.org/10.3390/jlpea12040060
Torrisi A, Yıldırım KS, Brunelli D. Ultra-Low-Power Circuits for Intermittent Communication. Journal of Low Power Electronics and Applications. 2022; 12(4):60. https://doi.org/10.3390/jlpea12040060
Chicago/Turabian StyleTorrisi, Alessandro, Kasım Sinan Yıldırım, and Davide Brunelli. 2022. "Ultra-Low-Power Circuits for Intermittent Communication" Journal of Low Power Electronics and Applications 12, no. 4: 60. https://doi.org/10.3390/jlpea12040060