A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The paper clearly describes the methodology authors followed to develop the formal verification framework for the correctness of DMR-NCL circuits. The introduction and background sections introduces the subject coincisely and clearly. An extensive presentation of possible error case and proposed safety checks. The vulnerability analysis of DMR-NCL from SEU/SEL, important for the employment of such logic in high-reliability contexts or, in radiation tolerant applications is based on reasonable hypotheses (power supply isolation bewteen groups). The results are presented clearly and are clearly deducible  from the discussion.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The paper presents a formal framework for the verification and vulnerability analysis of redundancy-based error-resilient Quasi-Delay Insensitive (QDI) NULL Convention Logic (NCL) asynchronous circuits. The primary objective is to address the challenges faced by conventional clock-based digital designs and to support redundancy-based error-tolerant QDI architectures, which have potential applications in harsh environments, safety-critical systems, and IoT devices. The proposed framework includes a formal verification methodology for redundancy-based QDI NCL circuits and a vulnerability analysis framework for error scenarios. The verification methodology ensures functional correctness and deadlock-free operation of the circuits, while the vulnerability analysis assesses the capability of the circuits to recover from single-event upsets (SEUs) and single-event latchups (SELs) without causing incorrect outputs or deadlock. The paper demonstrates the effectiveness of the proposed methodologies through extensive simulations and benchmark circuits of varying sizes and complexities. The authors also outline future work to extend the approach to verify sequential DMR-NCL circuits and customize it for similar redundancy-based QDI architectures. Overall, the paper contributes a scalable and versatile formal framework for ensuring the resilience and reliability of redundancy-based error-resilient NCL asynchronous circuits, with potential implications for various application domains.

 

I didn't see any size compariosns, specifically performance is given but not the area or trnaistor cost of the added circuitry.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This paper proposes a novel method for modeling and validating the correctness of combinational DMR-NCL circuits synthesized from their synchronous counterparts. NCL circuits are well-known and popular for certain applications requiring high level of timing robustness, and this research facilitates EDA support with circuit modeling and verification. The analysis process of this paper is detailed and clear, and the experimental results are well discussed.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf