Reliability Enhancement Methods for Relaxation Oscillator with Delay Time Cancellation

Abstract

Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the low-power delay time cancellation (DTC) technique and several enhancement methods, including a novel offset trimming approach, an error state detection and recovery (ESDAR) circuit, and a specialized frequency-trimming method. Simulation results for an 8 MHz relaxation oscillator in a 40 nm CMOS process show that the proposed DTC technique and enhancements improve frequency variation due to power supply fluctuations to ±0.05% and reduce temperature-induced frequency variation to ±0.4%.

1. Introduction

Relaxation oscillators exhibit lower power consumption than LC oscillators, which typically operate at several GHz [1] and offer better temperature stability than ring oscillators [2] in low-frequency applications. Additionally, they are more cost-effective than quartz crystal oscillators due to their compatibility with CMOS technology. Consequently, they are extensively utilized in microcontroller units (MCUs) as sleep timers [3], systems’ main clock sources [4], and other applications [5]. However, a significant challenge affecting relaxation oscillators’ frequency errors is the variation in the comparator’s offset voltage and delay time due to changes in process, supply voltage, and temperature (PVT). These factors are the primary reasons why relaxation oscillators typically operate at frequencies below 1 MHz [6,7,8]. Temperature compensation for comparator delay is achieved using current sources with positive and negative temperature coefficients [9]. However, variations in comparator delay due to supply voltage remain an issue. Inverter-based comparators with trip point regulation can reduce comparator delay variations, but the results are limited by the resolution of trip point regulation [6,8]. The chopping technique is used to mitigate the comparator’s offset voltage [7]. However, delay time remains a significant factor affecting frequency error. The comparator delay cancellation effectively mitigates the impact of comparator delay and offset voltage, but it compromises current efficiency due to the use of four comparators [10]. Frequency locked loops (FLLs) can address these issues due to their high open-loop gain. For instance, integrating a standard relaxation oscillator within a voltage averaging feedback loop has successfully produced a 14 MHz oscillator with minimal temperature-induced frequency errors [11]. Similarly, incorporating a relaxation oscillator in a self-threshold-tracking loop has resulted in an 8 MHz low-power, and high-precision oscillator [12]. By utilizing FLL and a parallel combination of two switched resistors, the oscillator in [13] operates at 32 MHz with low frequency errors. Furthermore, the introduction of FLL and second-order temperature compensation significantly improved the oscillator’s frequency stability in [14]. However, oscillators with FLL often suffer from slow start-up time due to limited bandwidth. Therefore, it remains essential to mitigate the effects of the variations in the comparator’s offset voltage and delay time without using FLLs.

The primary contributions of this paper are twofold: first, we propose a low-power delay time cancellation (DTC) technique to address the aforementioned issues without relying on FLLs; second, we introduce a series of enhancement methods, including offset trimming, an error state detection and recovery (ESDAR) circuit, and a frequency-trimming method based on ESDAR, to improve the reliability of the relaxation oscillator. The organization of this paper is as follows: in Section 2, we explain how the comparator’s offset voltage and delay time affect the frequency of relaxation oscillators and introduce the principle of DTC. In Section 3, we analyze the tolerance limit of the DTC technique and propose an offset trimming method to enhance this tolerance. Section 4 provides a detailed description of the ESDAR circuit. In Section 5, we introduce a frequency-trimming method based on the ESDAR circuit. Section 6 presents the simulation results, and Section 7 offers a brief conclusion.

2. Principle of Delay Time Cancellation

The frequency of conventional relaxation oscillators is influenced by the comparators’ offset voltage (V_os) and delay time (t_d). As illustrated in Figure 1a, considering the impact of V_os and t_d, the comparator switches its state when V_in reaches V_l + V_os + V_dly (where V_l is the reference voltage) resulting in a period error of t_os + t_d. If the reference voltage is increased to a higher level V_h, and V_in continues to rise from V_l + V_os + V_dly, the comparator will invert its state again when V_in reaches V_h + V_os + V_dly, as shown in Figure 1b. Then, the charge time t₄ can be expressed as

$$t_4={\displaystyle \frac{(V_h-V_l)}{k}},$$

(1)

where k represents the slope of V_in. Equation (1) indicates that t₄ is not affected by V_os and t_d. Therefore, this property can be utilized to mitigate the effects of V_os and t_d in the design of relaxation oscillators.

The proposed oscillator is depicted in Figure 2. It consists of a reference voltage generator providing V_h and V_l, a charging circuit, two comparators, a control circuit generating the control signals S_1a, S_2a, S_3a, S_4a, S_1b, S_2b, and an ESDAR circuit producing the reset signals Rstn₁, Rstn₂ and Rstn₃. The waveforms of the signals around CMP₂ are shown (the signals around CMP₁ are not depicted due to the symmetry of the oscillator) in Figure 3. The delayed clock signal Clk_b_d is utilized to generate the control signals S_2a, S_4a, and S_2b. The signals S_2a and S_2b control the charging and discharging of capacitor C₂, respectively.

The signal S_4a regulates the voltage of V_ref, enabling it to switch between V_h and V_l. With these control signals, the signal V_c2, which exhibits two charging phases within one clock cycle, can be obtained. During the first charging phase, V_c2 is charged to V_l + V_os + V_dly. In the second charging phase, V_c2 is charged to V_h + V_os + V_dly. Consequently, the period of the clock is given by

$$T=2t_{hf}=2{\displaystyle \frac{C\left[\right(V_h+V_{os}+V_{dly})-(V_l+V_{os}+V_{dly}\left)\right]}{I}}=2{\displaystyle \frac{C(V_h-V_l)}{I}}=2RC.$$

(2)

It is evident from Equation (2) that the period/frequency of the clock is not influenced by V_os and t_d.

3. Tolerance Limit of the DTC Technique and Offset Trimming

Figure 3 illustrates that the time for the first charging phase, t_{pre_cg}, must satisfy 0 < t_{pre_cg} < t_hf. Consequently, we derive

$$0<{\displaystyle \frac{C\left(V_l+V_{os}+V_{dly}\right)}{I}}<RC.$$

(3)

Given that

$$I={\displaystyle \frac{(V_h-V_l)}{R}},$$

(4)

Equation (3) can be reformulated as

$$0<{\displaystyle \frac{V_l+V_{os}+V_{dly}}{V_h-V_l}}<1.$$

(5)

Thus, the range of V_os + V_dly can be expressed as

$$-V_l<V_{os}+V_{dly}<V_h-2V_i.$$

(6)

Equation (6) illustrates that reducing V_os can decrease the comparator’s current draw, by allowing for a larger acceptable V_dly and t_d. Consequently, while reducing V_os does not reduce frequency error, it is beneficial for minimizing the oscillator’s power consumption. Thus, an offset trimming method is proposed to effectively reduce V_os.

To explain the offset trimming method, the relevant circuits, including the variable resistor R and R_t, and the comparator, are extracted from Figure 2 and redrawn as Figure 4, which includes the details of R_t. As depicted in Figure 4a, in the oscillator’s normal operation mode before offset trimming, the comparator’s input V_im is connected to V_l or V_h. The comparator’s input V_ip is connected V_c. The 5-bit variable resistor R_t is set to its median value by grounding Tap₁₅. Consequently, the voltage V_imr is given by

$$V_{imr}=V_{l_{-}15}+V_{\mathit{os}}$$

(7)

where V_{l_15} denotes the voltage at V_l when Tap₁₅ is connected to ground, serving as the reference voltage for offset trimming. Under these conditions, V_os reduces the acceptable maximum V_dly, as demonstrated in Equation (6).

Therefore, offset trimming should be performed before the oscillator enters its normal operation mode. The offset trimming process consists of two phases: the offset measurement phase and the resistance setting phase. In the offset measurement phase, all switches in R_t are deactivated via the control word R_t<4:0>. Tap₁₅ is connected to V_im, and V_ip iterates from Tap₀ to Tap₃₁ until the comparator’s output, cmp_o, transitions to a high level. Assuming that cmp_o transitions to a high level when V_ip connects to Tap_n, as illustrated in Figure 4b, the offset voltage V_os can be expressed as

$$V_{\mathit{os}}=\Delta V\left(n-15\right)$$

(8)

where ∆V represents the voltage drop across a unit resistor within R_t, and n denotes the Tap number that triggers a high-level output from the comparator. As deduced from Equation (8), the maximum offset trimming error is ∆V/2. The trimming range is defined as −15∆V ≤ V_os ≤ 16∆V, ensuring a balanced range due to the selection of V_{l_15} as the reference voltage for offset trimming.

Then during the resistance setting phase, as depicted in Figure 4c, Tap_n is grounded. Consequently, the voltage V_imr is given by

$$V_{imr }=V_{l_{-}15}+(15-n)\Delta V+V_{os}=V_{l_{-}15}$$

(9)

It is shown that V_imr is not affected by V_os after offset trimming.

Given that the V_os of the comparator is specified to be 70 mV and the current flowing through R_t approximates 1.26 μA, the maximum R_t is deliberately set to 160 kΩ to achieve a trimming range of ±100 mV. Figure 5 depicts the oscillator’s tolerance to variations in the comparator’s delay time. Without offset trimming, a substantial frequency error arises when the delay time exceeds 26 ns. Conversely, with offset trimming, the tolerance limit extends to 36 ns. This demonstrates that the proposed offset trimming method effectively reduces the influence of V_os, thereby enhancing the oscillator’s tolerance to fluctuations in the comparator’s delay time. Therefore, a five-transistor amplifier with a 30 ns delay time is utilized in this work.

4. Error State Detection and Recovery Circuit

To enable the charging circuit to perform two distinct charging processes within a single cycle, as depicted in Figure 3, we propose a specialized control circuit, as illustrated in Figure 2. However, sudden changes in external conditions, such as a drop in supply voltage, may cause the control circuit to generate incorrect signals, leading to the incorrect clock signal shown in Figure 6. As depicted in Figure 6, the oscillation stops around 3 μs due to the drop in VDDA. Although VDDA recovers around 4.3 μs, the control circuit generates incorrect signals, including S_1a, causing incorrect charging and output pulses from the comparators. This results in an undesired output clock from the oscillator.

To address this issue, we propose an ESDAR circuit, as illustrated in Figure 2. This circuit is capable of generating a reset signal in response to an incorrect output clock. It cannot be replaced by a power-on reset circuit because the conditions causing the incorrect output clock and those triggering the power-on reset circuit are not always the same. This circuit continuously monitors the outputs of the comparators and divides them using D-flip flops. One example of a divided signal, Comp_{1o_div}, is shown in Figure 7a. When Comp_{1o_div} is sampled by a D-flip flop synchronized with the Clk_b clock signal, the output consistently remains high. Consequently, under normal operating conditions, the signal Rstn₁ remains high, as depicted in Figure 7a.

In contrast, during abrupt changes in VDDA, the control circuit may generate erroneous signals, causing the comparator to produce only a single pulse within a complete cycle. Under such conditions, the output of the D-flip flop transitions to a low state, as illustrated in Figure 7b. Consequently, the signal Rstn₁ also drops to a low state, initiating a reset of the oscillator. In the initial condition, the current mirrors in the RVG and CMP are disabled by Rstn₁; the current mirrors in the charging circuit are disabled by Rstn₂; and the signal Clk is held low by Rstn₃, as shown in Figure 2.

Figure 8 depicts the operational response of the oscillator, incorporating the ESDAR circuit, to a sudden reduction in VDDA. At approximately 5.2 μs, the Rstn₁ signal initiates the reset process of the oscillator, demonstrating the effectiveness of the ESDAR circuit. Simulation results indicate that the ESDAR circuit functions effectively within a VDDA drop slope range of 0.1 µs/V to 1 µs/V and a minimum voltage of 0 V to 1 V.

5. Frequency-Trimming Method

To mitigate frequency errors in relaxation oscillators, frequency trimming is essential. This process includes temperature compensation to compensate for the temperature-dependent variations in resistor R, and adjustment of the frequency variations caused by the process variation. The latter is achieved by modulating the variable resistor, R, and the variable capacitor, C, while temperature compensation is facilitated by introducing a positive temperature coefficient of absolute temperature (PTAT) current, I_p, into the circuit, as shown in Figure 9 [15]. As illustrated in Figure 9, the control word KT is used for temperature compensation. The control word WT is used to adjust the value of R by changing connections of the relevant switches. Considering the effect of I_p, the output clock frequency can be expressed as

$$f_0={\displaystyle \frac{1}{2RC}}\cdot {\displaystyle \frac{I}{I+\alpha I_p}},$$

(10)

where α represents the position where I_p is inserted. If I is a zero-temperature coefficient current, the temperature coefficient of the current ratio I/(I + αI_p) can be adjusted by modifying α, thereby compensating for the temperature-dependent variations in the resistor R.

However, as demonstrated in Equation (10) and Figure 9, f₀ varies with changes in α, which in turn depends on alterations in resistance R. This implies that achieving the desired frequency requires a concurrent process of temperature compensation and adjustment of the absolute frequency value. Moreover, given the extensive combination possibilities of trim codes totaling 131,072 (stemming from an 8-bit WT code, a 6-bit KT code, a 2-bit CT code and two temperature points), the frequency measurement during the trimming process incurs significant costs. Therefore, optimizing this process is crucial for cost-effective and precise frequency control.

Fortunately, the relationship between the parameters α, KT and WT in this circuit can be expressed as

$$KT={\displaystyle \frac{(B+WT)\alpha -C}{A}},$$

(11)

where the constants A, B and C are set to 6, 280 and 88, respectively. By utilizing Equation (11), it becomes feasible to calculate the value of KT for any adjustment in WT, while keeping α constant. Consequently, the trimming process can be optimized using Equation (11). The proposed trimming flowchart is shown in Figure 10. Initially, WT and KT are set to 128 and 32, respectively. Next, CT is adjusted to make the current oscillation frequency f₀ approach the target frequency f_t. Subsequently, by measuring f₀ at 25 °C and 125 °C with varying KT, the optimal KT that minimizes temperature-induced frequency error is determined, and the corresponding α is calculated. Then, WT is tuned using the bisection method, and KT is adjusted to maintain α constant until the frequency error |f_t − f₀|at 25 °C is minimized. This concludes the frequency-trimming process.

Figure 11 illustrates the variations in f₀ with respect to the change in WT, while keeping the optimal α. It demonstrates that the clock frequency can be adjusted without change the temperature efficient by using the proposed frequency-trimming process. With this process, the combination possibilities of trim codes can be reduced to 140, significantly reducing the frequency-trimming costs.

During the frequency-trimming process, the oscillation frequency may significantly exceed the target frequency, f_t, such as in the condition of WT = 0, CT = 3. Under these circumstances, the oscillator may fail to function properly as it cannot meet the requirement of 0 < t_{pre_cg}< t_hf, as mentioned in Section 3. To address this issue, the ESDAR circuit is introduced into the frequency-trimming process. As illustrated in Figure 12, when the oscillator malfunctions due to an excessively high frequency, the comparators produce only a single pulse within a complete cycle, resulting in a reset pulse from Rstn₁. Therefore, the reset pulse indicates that the oscillation frequency is higher than target frequency during the frequency-trimming process.

The flowchart for using the bisection method to tune WT with the assistance of the ESDAR circuit is shown in Figure 13. First, initialize WT₁ to 0 and WT₂ to 255. Then, define WT₃ as the integer value that most closely approximates the arithmetic mean of WT₁ and WT₂. Next, evaluate whether the following conditions are simultaneously satisfied, either both conditions 1 and 2, or conditions 1 and 3:

• When WT is equal to WT₃, the oscillation frequency is less than f_t.
• When WT is equal to WT₁, the oscillation frequency is greater than f_t.
• When WT is equal to WT₁, Rstn₁ outputs a reset signal.

If these conditions are met concurrently, set the value of WT₂ to be equal to WT₃. If the conditions are not met concurrently, set the value of WT₁ to be equal to WT₃. This iterative procedure is continued until |WT₁ − WT₂| = 1. Ultimately, the final value of WT is selected as the one between WT₁ and WT₃ that results in the minimum frequency error. By following the procedures shown in Figure 10 and Figure 13, the frequency-trimming process can be implemented successfully.

6. Simulation Results

The proposed DTC technique and reliability enhancement methods are implemented in an 8 MHz relaxation oscillator designed using a 40 nm CMOS process. The oscillator’s duty cycle ranges from 48% to 51% across PVT variations. This duty cycle error is primarily caused by fluctuations in the driving capability of the RS flip-flop within the control circuit. Figure 14a demonstrates that with the DTC technique, the frequency variation due to power supply voltage fluctuations is improved to ±0.05%. Figure 14b illustrates that within the temperature range of −40 °C to 125 °C, the frequency variation is reduced to approximately ±0.4% (due to the second-order dependence of the resistor) with the DTC technique, compared to ±0.8% without it. The frequency variations at fast-fast (ff) and slow-slow (ss) corners are also illustrated in Figure 14, highlighting the stability of frequency despite process variations. The performance comparison with other open-loop relaxation oscillators is presented in

Table 1. Performance comparison with other open-loop relaxation oscillators.

	[6]	[7]	[8]	[9]	[10]	[16]
Process [nm]	180	65	55	180	350	180
Freq. [Hz]	100 k	18.5 k	33 k	1.1 M	1 M	28 k
Current eff. [μA/MHz]	5.4	7	9.24	0.4	63.6	1.19
Temp. sen. [ppm/°C]	51	85	58	64	48	95.5
Temp. range [°C]	−40~85	−40~90	−40~125	−20~80	−40~125	−20~80
Line sen. [%/V]	0.4	5	0.75	3	0.28	3
*2 FoM [μA·(108 MHz·°C·V)−1]	110.6	2972.9	403.3	83.3	863.9	340.9
Trimming points for temperature compensation	-	-	-	-	-	-
Type of results	Simulation	Measurement	Simulation	Measurement	Measurement	Measurement
	[17]	[18]	[19]	[20]	[21]	[22]
Process [nm]	130	65	28	28	90	180
Freq. [Hz]	1.2 M	3 M	28.5 k	2.1 M	100 k	4
Current eff. [μA/MHz]	4.83	5.77	1.21	1.85	3.5	2.08
Temp. sen. [ppm/°C]	296	133.3	33.3	158	104.6	40,000
Temp. range [°C]	−40~80	0~90	−40~85	−20~120	−40~90	−20~40
Line sen. [%/V]	3.6	0.6	1.9	26.8	9.37	10
*2 FoM [μA·(108 MHz·°C·V)−1]	5150.4	461.3	76.8	7841.5	3431.4	830,000
Trimming points for temperature compensation	-	-	1	3	-	-
Type of results	Measurement	Measurement	Measurement	Measurement	Measurement	Measurement
	[23]	[24]	[25]	[26]	[27]	This Work
Process [nm]	180	65	180	180	130	40
Freq. [Hz]	11	2.8	18	10.5 M	3.2 M	8 M
Current eff. [μA/MHz]	439.4	31.7	0.39	14.95	8.48	3.6
Temp. sen. [ppm/°C]	45	1260	20,000	137	1253	48 *2 291
Temp. range [°C]	−10~90	−40~60	−30~60	−40~125	−20~60	−40~125
Line sen. [%/V]	1	8.63	24.4	4.4	0.4	0.275
*1 FoM [μA·(108 MHz·°C·V)−1]	19,800	345,000	190,000	9010	4250	48
Trimming points for temperature compensation	-	-	-	-	-	2
Type of results	Measurement	Measurement	Measurement	Measurement	Measurement	Simulation

*¹ FoM represents figure-of-merit and is defined as current eff.; temp. sen; line sen. *² Oscillator is trimmed only at room temperature.

. As shown, the oscillators operating below 1 MHz demonstrated improvements in both current efficiency and temperature-induced frequency variations. However, enhancing these performances for oscillators operating above 1 MHz remains challenging. The proposed DTC technique and reliability enhancement methods, however, enable the relaxation oscillator to operate at higher frequencies with low frequency variation and improved current efficiency.

7. Conclusions

This paper presents a series of enhancements to the DTC technique to improve the reliability of relaxation oscillators. The proposed offset trimming approach, ESDAR circuit, and specialized frequency-trimming method have shown significant improvements in frequency stability and tolerance to PVT variations. The simulation results demonstrate the effectiveness of the proposed methods in enabling relaxation oscillators to operate at higher frequencies with low frequency variation and reduced current consumption. The voltage overhead in the resistor R_t may limit its application in low voltage conditions, necessitating future improvements. To enhance the credibility of this research, we will implement layout design, timing verification, post-layout simulation, fabrication and measurement in our subsequent work.