A Low-Voltage, Low-Power 2.5 GHz Ring Oscillator with Process and Temperature Compensation

Abstract

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits.

1. Introduction

Voltage-controlled oscillators (VCOs) are key building blocks in many electronic systems, serving as critical components for timing, frequency synthesis, and data communication circuits, providing a constant and stable frequency clock. Ring VCOs (R-VCOs) and LC-VCOs are among the most common architectures. LC-VCOs are known for their superior phase noise performance, relying on inductors and capacitors to create a resonant tank. However, they typically require a large silicon area and higher power consumption compared with other oscillators. On the other hand, R-VCOs, comprising a loop of delay cells, offer advantages in terms of their compact layout, low power consumption, and full integration without requiring inductors, making them suitable for applications such as IoT, wearable devices, and short-range wireless communication. Considering these, the selection between LC-VCOs and R-VCOs depends on the system requirements for the VCO performance. The widespread and continuous improvement of IoT devices requires a compact layout area and low power consumption, albeit at the expense of increased phase noise. Thus, R-VCOs are preferred in recent system designs for IoT and serial communications [1,2,3,4].

An R-VCO consists of a number (N) of delay cells. The delay cells of an R-VCO can be either single-ended or differential. A single-ended R-VCO [4,5,6,7] is a chain of inverters, and the number of its delay cells must be odd. On the other hand, the differential R-VCOs can have either an odd or even number of delay stages [1,2,3,8,9,10,11]; therefore, they offer better flexibility on the generated phases. The single-ended R-VCOs present better phase noise performance than their differential counterparts for the same number of stages, but the differential R-VCOs present better common-mode rejection of supply and substrate noise. Finally, differential R-VCOs can be separated into two categories: the fully differential and the pseudodifferential. The fully differential architectures are based on differential pairs and their tail current sources, which succeed in exhibiting better common-mode noise rejection, though the pseudodifferential architectures [12,13,14] are based on independent inverters and achieve a larger common-mode gain.

The frequency of an R-VCO primarily depends on the delay of each delay cell that comprises the ring oscillator. This delay is defined by the design parameters, including the transistor transconductances, the bias conditions, and the inherent input and output capacitances. But all of these parameters are influenced by variations in the bias conditions and the supply voltage. As a result, R-VCOs are inherently sensitive to process, voltage, and temperature (PVT) variations. While supply voltage variations can typically be mitigated using on-chip low-dropout regulators (LDOs), process and temperature variations present more significant challenges. Several techniques have been proposed to address this issue [1,14,15,16,17,18]. In [1], a process compensation mechanism based on process detection and switched resistors is presented. However, it does not mention a temperature compensation technique. A complementary-to-absolute temperature (CTAT)-based temperature-compensated R-VCO is presented in [14] with switching transistors for process compensation, but it does not include a process monitoring technique. More complicated circuitries for process and frequency detection have been used in [15,16], where a PLL-type topology is employed to detect and correct the frequency, but it makes the circuit power hungry. One other approach is to design a VCO with a wide tuning range, either by increasing the gain of the tuning curve (K_VCO) [19] or by using multi-band switched tuning mechanisms [3]. However, high K_VCO values often lead to increased sensitivity to noise [4,19] while multi-band tuning can cause abrupt frequency jumps during temperature drift, introducing lock instability and extra settling time. The unlocking of an already locked clock, due to increasing temperature, is especially critical to system reliability, as it can unlock it during an already running critical operation. To address these issues, a compensation topology can be used for the temperature and process variation. In [11], bulk-driven topology provided a good performance, but it could not be used to provide a differential output. Also, in [17], a topology with constant g_m current is presented. A topology based on the bias calibration by I-DAC is presented in [20].

For temperature compensation, circuits such as proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current generators have been used [4,14]. These sources generate a bias current that tracks the temperature changes, compensating for the frequency drift. Process compensation, on the other hand, requires identification of the silicon process corner (e.g., slow–slow, fast–fast) and adjusting operating parameters accordingly. For this purpose, a topology that accurately detects the process corner is proposed in this paper.

Thus, the key points of the proposed topology are the development of an R-VCO, with low frequency drift over temperature and process variations, operating with low supply voltage and low power consumption, suitable for IoT applications [21,22].

A combined temperature- and process-compensated R-VCO is proposed in this paper, which aims to keep the oscillation frequency constant and within specifications in terms of current consumption, phase noise, and control voltage. In the next sections, this paper is organized as follows. Section 2 describes the proposed delay cells, R-VCO, and compensation techniques. In Section 3, the post-layout simulation results are presented, and the conclusions are provided in Section 4.

2. The VCO Architecture

The proposed R-VCO architecture is designed to eliminate the effects of both temperature and process variations. The first compensation circuit utilizes a PTAT (proportional-to-absolute temperature) current source, which helps counteract frequency drift caused by temperature fluctuations. The second circuit addresses the process variations by detecting the process corner and adjusting the VCO’s frequency accordingly. Process corner detection is a more complex challenge, but it has been demonstrated in recent studies as an effective means to compensate for process-related variations [1,9]. By combining these two techniques, we can achieve a VCO that operates within a narrow frequency range, even under varying temperature and process conditions.

The block diagram of the proposed architecture is depicted in Figure 1. It consists of four main blocks: (a) the four-stage ring oscillator, (b) the frequency control topology, (c) the temperature compensation circuit, and (d) the process compensation circuit.

The ring oscillator is based on a four-stage, differential topology, as shown in Figure 1. The number of stages has been chosen to provide four differential output phases. The oscillator frequency is controlled by the bias current I_bias of the delay cell, as shown in Figure 2. Therefore, a voltage-to-current converter (V2I) is required to convert the control voltage (V_ctrl) to current. The target frequency is at 2.5 GHz with an average consumption less than 400 μW and a phase noise about −80 dB/Hz at 1 MHz offset.

2.1. The Delay Cell

A differential delay cell [19] has been used for the ring oscillator, modified accordingly to provide the ability for process corner compensation. As shown in Figure 2, it relies on an nmos differential pair (M_n1, M_n2), with a passive load and a pair of cross-connected pmos transistors. The switched resistors are enabled accordingly, depending on the specific process corner. The tuning of the delay cell is supplied by the tail transistor M_n3. The tail transistor copies a multiple of the current provided by the diode-connected transistor M_n (Figure 1). The M_n3 transistor operates in the deep triode region. The final current is a combination of the voltage-to-current converter (V2I) that converts V_ctrl to current and the PTAT current.

The delay cell in [19] was studied to offer a wide tuning range, controlled by V_DD. To control it by M_n3 only, and to avoid noise issues, a supply voltage regulator is necessary [11]. In our case, we want to avoid a wide tuning range to improve noise induced by V_ctrl, and also we need a low supply voltage; therefore, the voltage headroom of the transistors is limited. Hence, in this design, supply voltage V_DD is considered regulated and constant, and the frequency is controlled by the bias current I_bias of M_n3.

Considering that the pair of M_n1 and M_n2 operates differentially, V_gs alternates between the two transistors, and the current of each transistor is complementary to each other. Assuming that I_bias = 2·I_Mn1, the oscillation frequency f_osc is defined by the bias current of M_n3 I_bias, as shown in Equation (1) [19]:

$$f_{osc}={\displaystyle \frac{1}{2\pi }}{\displaystyle \frac{g_{mMn1}}{C_L}}={\displaystyle \frac{1}{2\pi }}{\displaystyle \frac{\sqrt{2{\mu }_n{C}_{ox}{\left(\frac{W}{L}\right)}_{Mn1}{I}_{Mn1}}}{C_L}},$$

(1)

where g_mMn1 is the transconductance of M_n1 (and M_n2); C_L is the total capacitance of output nodes, including the input capacitance of the following stage; μ_n is the carrier mobility; C_ox is the oxide capacitance; and W/L is the aspect ratio of the transistors M_n1 and M_n2. Then, the frequency tuning is proportional to I_bias, as shown in Equation (2).

$$f_{osc}={\displaystyle \frac{1}{2\pi }}{\displaystyle \frac{I_{bias}}{C_L{V}_{eff}}},$$

(2)

where V_eff = V_gs − Vth of M_n1 and M_n2.

2.2. The Temperature Compensation Technique and Circuit

The oscillation frequency depends on the temperature, mostly due to two factors: the I_d and Vth of the transistors of the differential pair. It is known that I_d of mosfets is

$$I_{dMn1,2}={\displaystyle \frac{1}{2}}{\mu }_n{C}_{ox}{\left({\displaystyle \frac{W}{L}}\right)}_{Mn1,2}{V}_{eff}^2,$$

(3)

The mobility factor μ_n decreases with the temperature [23]:

$${\mu }_n\propto T^{-m},$$

(4)

where m is a factor within the range 1.5 to 2.

The threshold voltage Vth decreases with temperature at a rate of about −2 mV/°C. So, considering V_gs and I_d are almost constant, V_eff increases slightly with temperature. Regarding g_m, it decreases with temperature:

$$g_{mMn1,2}(T)=\sqrt{2{\mu }_n(T)C_{ox}{\left({\displaystyle \frac{W}{L}}\right)}_{Mn1,2}{I}_{dMn1,2}}\propto \sqrt{{\mu }_n\left(T\right)}\propto T^{-m/2}$$

(5)

Considering the factors affected by temperature, it is evident that the frequency decreases as the temperature increases. To compensate for this, an extra proportional-to-absolute temperature (PTAT) current can be injected into the current mirror and added to the current of the controller I_ctrl, as shown in Figure 3. This could compensate for the drift in frequency due to temperature variations.

The circuit used to generate the PTAT current is based on the beta multiplier [24] shown in Figure 3. The transistors M_n1 and M_n2 are biased with the same current. M_p4 is equal to M_p5, and M_n1 is equal to M_n2. As already mentioned, the transistors have a negative gate-source threshold voltage (Vth) temperature coefficient, while the resistor (R) has a positive temperature coefficient. The desired temperature coefficient of the PTAT current can be achieved by selecting the right combination of transistor sizes and resistor values.

2.3. The Process Compensation Technique and Topology

The process compensation requires a topology that detects the process corner. As shown in Figure 4, this topology consists of three sub-blocks: a process-dependent sub-block detecting the process variation, a process-independent sub-block generating constant references, and a comparison and decision sub-block generating control signals for the VCO setup. The process-dependent circuit consists of a current mirror and a resistor. The circuit produces a process-variant voltage value (V_p) used to track the process corner. This block consists of similar elements, with the delay cells, keeping a similar behavior between the corner detection circuit and the delay cell for each process corner. As the VCO frequency is mostly defined by the nmos differential cell and the resistor of the delay cell, the process-detecting circuit includes only nmos transistor and resistor, both of the same type as those of the delay cell. Thus, the biasing conditions of the VCO are influenced in the same way by the voltage V_p. The process-independent topology is a typical voltage divider consisting of three resistors of the same type. Therefore, the process and temperature variations have no impact on the circuit, and it can produce two constant, process-independent voltages, V_ref1 and V_ref2. Only V_DD variation could slightly affect the values of V_ref1 and V_ref2, but this voltage is considered to be provided by an LDO with less than 2% variation, which gives enough headroom to V_ref1 and V_ref2 variations so that the topology can find the correct corner. Finally, the decision sub-block consists of two comparators that compare the process-dependent voltage (V_p) with the process-independent voltages (V_ref1, V_ref2). If the circuit operates in the typical case, the V_p value is between V_ref1 and V_ref2. In the case of the slow–slow (ss) corner, V_p is lower than V_ref1 and V_ref2, while in the case of the fast–fast (ff) corner, V_p is higher than both V_ref1 and V_ref2. For each case, the comparators create a 2-bit control signal that enables or disables the corresponding resistors R1 and R2 in the delay elements depicted in Figure 2, in order to adjust the oscillation frequency.

3. Simulation Results

The proposed compensated VCO architecture was designed and simulated in a 22 nm CMOS process with a 0.8 V supply voltage and a target frequency of 2.5 GHz. The main target of the proposed topology is a VCO with low frequency drift over temperature and process variations, operating with a low supply voltage and low power consumption, suitable for IoT applications. So, additional limitations are generated by the fact that only one supply domain is used, namely, 0.8 V for the overall topology, including the oscillator itself, the biasing circuit, and the circuit for the control voltage. Post-layout simulations show the performance of the proposed architecture.

Applying a middle range control voltage Vctrl equal to 400 mV, without any compensation, the oscillation frequency is gradually reduced by the temperature increment, from 2.8 GHz to 2.2 GHz, as shown in Figure 5. This results in a frequency drift equal to 23.9% of the central frequency across the temperature range from −40 °C to 125 °C. When temperature compensation is applied, the frequency drift is significantly reduced to 5.4% under the same conditions, as depicted in Figure 5. This plot depicts the performance for the typical (tt) case only.

However, the frequency still shows a great distribution across the process corners. Figure 6 depicts the frequency for temperatures from −40 °C to 125 °C and the typical, slow–slow, and fast–fast (tt, ss, ff) corners. The circuit presents a frequency drift equal to 24.3% for the ff corner and 23% for the ss corner. After applying the process compensation method described in Section 2.3, the frequency variation is significantly decreased, as depicted in Figure 7, from 47.3% to 7.2%. In the same figure, the compensated frequency for the slow–fast and fast–slow (sf, fs) corners is depicted as well, where its behavior is close to the tt case.

The compensated frequency for different values of control voltage V_ctrl (200 mV, 300 mV, 500 mV, and 600 mV) is shown in Figure 8. At greater V_ctrl, the frequency shows a slight trend towards a negative slope with respect to the temperature, while in the lower V_ctrl, the opposite. Also, as depicted in Figure 8a,b, the oscillator cannot retain oscillations at V_ctrl less than 300 mV in the ss corner and at less than −20 °C, but the oscillator in a PLL will not be settled in this case, as V_ctrl would increase to initiate oscillation close to the desired frequency of 2.5 GHz. Therefore, the main focus for an optimized frequency compensation is given at V_ctrl equal to 400 mV, as this value is considered suitable for the specific supply voltage range of the circuit, which is 0.8 V.

More corner simulations have been performed, adding a V_DD variation of ±2%. This range was selected as it covers the specifications for the line-regulation of most LDOs [25,26,27,28,29,30] that can be used on chip to supply the VCO. When targeting an optimized performance at a frequency of 2.5 GHz for a V_ctrl equal to 400 mV, the results of the compensated frequency over temperature in each process corner are provided in Figure 9a and Figure 9b, for V_DD variations of +2% and −2%, respectively.

The results presented in Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9 are summarized in

Table 1. Frequency values over process corners and temperature range from −40 °C to 125 °C.

Corner	Vctrl (mV)	Compensation	fo (GHz)	fmin (GHz)	fmax (GHz)	Variation (%)
tt	400	No	2.553	2.216	2.825	23.9
tt	400	Yes	2.553	2.428	2.565	5.4
tt, ss, ff	400	No	2.553	1.968	3.175	47.3
tt, ss, ff, sf, fs	200	Yes	2.441	2.215	2.518	12.4
tt, ss, ff, sf, fs	300	Yes	2.499	2.311	2.542	9.2
tt, ss, ff, sf, fs	400	Yes	2.553	2.391	2.576	7.2
tt, ss, ff, sf, fs	500	Yes	2.601	2.432	2.613	7
tt, ss, ff, sf, fs	600	Yes	2.652	2.442	2.680	9
tt, ss, ff, sf, fs, VDD −2%	400	Yes	2.491	2.347	2.526	7.2
tt, ss, ff, sf, fs, VDD +2%	400	Yes	2.612	2.419	2.623	7.8

. In this table, the minimum f_min and maximum f_max frequencies over process corners and for a temperature range from −40 °C to 125 °C are given together with the center frequency fo. In this table, f_o is defined as the oscillation frequency in the tt corner, at 27 °C. The variation (%) is the peak-to-peak variation taken with a reference at f_o in each case.

As shown in Table 1, without compensation over process corners and temperature, the frequency is almost 50%, and becomes equal to 7.2% after compensation for V_ctrl = 400 mV. The value of 400 mV has been taken as the main reference to compare the results before and after compensation, in the typical case. The minimum and maximum frequencies, together with the center frequency over V_ctrl, are depicted in Figure 10.

Applying the full compensation circuit, the frequency tuning and the VCO gain (K_VCO) are evaluated. In Figure 11, the frequency over V_ctrl, and in Figure 12, K_VCO are depicted, respectively, for the nominal supply voltage of 0.8 V and temperature of 27 °C. As shown, K_VCO is about 520 MHz/V in the typical case. The K_VCO has a small variation vs. V_ctrl, as shown in Figure 12 for each case, although it is overall lower in the ff corner.

The phase noise of the VCO is depicted in Figure 13, where the value at 1 MHz offset is about −80 dBc/Hz. The typical and the two extreme conditions (worst and best) are only shown in Figure 13.

Monte Carlo simulations were performed to evaluate the impact of the random variations on the circuit. One indicative case is depicted in Figure 14, for the topology running at V_DD = 0.8 V, temperature 27 °C, and V_ctrl = 400 mV. The results from 200 samples show a frequency mean value of 2.49 GHz with a standard deviation of 124 MHz. The layout of the overall topology is shown in Figure 15 and occupies 227 × 61 μm². A large area is occupied by decoupling capacitors, placed in the bias circuits, which are required to reduce phase noise. Although they take a greater layout area than the active circuits, this size ensures good noise performance over all operating biasing conditions imposed by process and temperature corners.

The average power consumption of the whole circuit is 380 μW, where the ring oscillator itself dissipates 264 μW.

The performance of the proposed circuits is summarized in

Table 2. Comparison table of compensated ring VCOs.

	[4]	[14]	[15]	[16]	[17]	[20]	This Work
Technology (nm)	180	28	180	90	130	3 nm	22
Supply voltage (V)	3.3	1	1.8	-	3.3	0.8	0.8
Temp (°C)	−40 to 120	−40 to 125	−25 to 125	−50 to 100	−40 to 125	−55 to 125	−40 to 125
Central f (GHz)	0.480	4	2.3	3	1.25	10.6	2.5
Variation @ fo (%)	1.9	-	3.0	17	10	10	7.2
Calibration	T	PVT	PVT	PT	PT	PT	PT
In PLL	Yes	Yes	Yes	PLL_like	No	Yes	No
Power consumption (mW)	NA	2.27	-	2.55	3.4	5.6	0.38
Phase noise (dBc/Hz) @ 1 MHz	−107	-	-	-	−88	−69.1	−80

. In the same table, some other R-VCOs are provided for comparison with the proposed one. The results in [4,14,15] are based οn full PLL implementations. Therefore, some results dedicated to the VCO are not available. Thus, a PLL topology with compensation is presented in [4], where the frequency drift after compensation is small, but this topology applies compensation only over temperature, and the results with process variations are not presented. The topologies in [14,15] are also based on a PLL topology, but offer PVT compensation. In [16], a PLL-like topology is used to compensate for the variations, with the presented results related to the output period only. In [17], a constant-g_m-based topology is presented. The two-stage ring oscillator shows a relatively good performance in terms of phase noise, but with an increased power consumption equal to 3.4 mW. An I-DAC based calibration method for an R-VCO designed in a 3 nm process is presented in [20] with good overall performance.

4. Conclusions

This paper presents a temperature and process compensated R-VCO architecture. By employing PTAT-based temperature compensation and a novel process corner detection technique, the proposed VCO architecture significantly reduces frequency drift across temperature and process variations. The design achieves a phase noise of about −80 dBc/Hz at a 1 MHz offset, with an average power consumption of 380 μW. These results demonstrate that the proposed VCO is well-suited for IoT applications, where small size, low power, and stability are crucial.