A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

Abstract

An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S₂₁) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S₂₂). It achieves an average power gain (S₂₁) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S₁₁) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S₂₂) of less than −10.6 dB with a very high reversion isolation (S₁₂) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

1. Introduction

The Federal Communications Commission (FCC), in 2002, offered a 3.1–10.6 GHz ultra-wideband frequency (UWB) range, for the implementation of very high data rate wireless communication links [1]. The FCC set an upper limit on highest power spectral density to −41.3 dBm/MHz over the 3.1–10.6 GHz frequency range, so that the newly designed wireless communication devices could not interfere with the wireless services existing in the same local area network [1,2,3]. This upper limit for power spectral density makes the UWB technology suitable for many interesting wireless applications, such as wireless personal area networks (WPAN), medical imaging, short-range radars for vehicles and wireless sensor nodes [4,5]. It gives reasons for low-power very-large scale integration (VLSI) design industries and researchers to develop low-power, low-noise, and reliable UWB radio-frequency integrated circuits (RFICs) for these applications. Moreover, continuous shrinking in complementary metal oxide semiconductor (CMOS) chip fabrication technologies and split manufacturing techniques in RF designs [6,7], makes it possible to design and fabricate RFICs on the nanometer scale [8,9].

LNA as a primary module of UWB wireless communication receiver requires designers to meet many challenges like 50 Ω input matching, a low noise figure, flat gain, low power, and the receiver’s stability across the complete UWB frequency range [2,3,9]. Two frequently used UWB LNA topologies by many researchers are common-source (CS) [8,10,11,12,13,14,15,16] and common-gate (CG) [2,3,4,5,17] (Figure 1). The CS-topology is suitable to design LNAs for narrow and wide-band matching with high power gain (S₂₁). However, using the proper band-pass network, CS topologies can also be used for wideband LNA designs, but it degrades the gain and noise performance of the LNA. A common-source LNA with impedance feedback topology (Figure 1c) is also famous among some researchers [10,11,12,13,17]. However, the noise figure of a resistive feedback LNA is higher than that of CS topology. Distributed amplifiers (DA) (Figure 1d) are favored by some researchers to realize flat gain LNA for UWB [18,19]. The average power gain of DA is around 8–10 dB [18,19]. Active inductor-based input matching techniques (Figure 1e) can also be used for gain flatness in CG-topology [20]. However, due to the inclusion of an additional metal-oxide semiconductor (MOS) device used as an active inductor at the input, it increases NF as compared to traditional CG-LNA. For example, NF of the LNA proposed in [20] is greater than 4.5 dB.

This paper reports a design of a low-power LNA using CG feedback-body biased topology for an UWB frequency. A CG configuration provides a very simple technique for UWB input impedance matching by setting 1/g_m equal to 50 Ω, where gm is the transconductance of CG transistor. Implementation of feedback-body biasing for input CG transistor leads to the further decrease in the power supply (V_dd) due to the decrease in threshold voltage, which results from a decrease in power consumption. The advantage of a wideband input matching capability and utilizing the body-biasing to decrease power consumption brought our attention to the traditional CG LNA topologies for the 3.1–10.6 GHz UWB frequency. This paper is organized as follows: Section 2 describes the proposed LNA design methodology for the proposed LNA. In Section 3, the results of the proposed LNA circuit and comparison with the previous work are presented. Finally, Section 4 concludes this paper.

2. Operational Principle and Circuit Implementation

The circuit diagram of the proposed UWB LNA shown in Figure 2 consists of four stages. At the input side, a common-gate cascode topology has been used to achieve wideband input matching. The source inductor (L_s1) and gate-source parasitic capacitance (C_gs1) dictates the input resonance frequency of the CG-stage. The transistor M₁ has been configured to feedback-body biasing through the feedback resistor R₁ connected to drain terminal of M₂, to boost-up the noise figure performance and the power consumption, whereas the transistor M₂ is cascoded with M₁ to enhance the gain of the first stage. The CG first stage has been cascoded with two stages of common source configuration using transistors M₃ and M₄ respectively, to enhance the gain and bandwidth proposed for UWB LNA. In first CS stage, L_d3 serves as a series peaking inductor, which increases the gain flatness. At the output side, a buffer stage has been used for enhancing the output matching (S₂₂) performance of the proposed LNA. The output of the transistor is tuned by a parallel LC resonating circuit, in which an inductor (L_d4) resonates with the total gate-drain parasitic capacitances (i.e., C_gd4 + C_gd5) of the transistors M₄ and M₅, respectively. The output is taken from the source terminal of transistor M₅ whereas M₆ behaves as a saturated load.

The capacitors C_in, C₁, C₂ and C₃ are the coupling capacitors, whereas the resistors R₂ to R₅ are used as biasing resistors. Maximum power flow from receiver end to the load end is one of the important requirements for an LNA design, and for this purpose, a parallel to series LC network has been used between common gate first stage’s output and the input of second stage. In this, drain inductor (L_d2) and gate-drain parasitic capacitance (C_gd2) of M₂ are figured as parallel resonance circuit resonating at $1/\sqrt{L_{\mathrm{d}2}{C}_{\mathrm{gd}2}}$, whereas inductor L₁ and the capacitance C₁ are used to form series resonance circuit resonating at $1/\sqrt{L_1{C}_1}$. A frequency response equivalent to a band-pass filter can be achieved when parallel LC tank resonates at the same centerfrequency at which series LC tank does. This condition can be achieved when ${\left(L_{\mathrm{d}2}{C}_{\mathrm{gd}2}\right)}^{-\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}={\left(L_1{C}_1\right)}^{-\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$, i.e., $L_{\mathrm{d}2}{C}_{\mathrm{gd}2}=L_1{C}_1$.

Table 1. Parameters for the proposed LNA.

Transistors W (µm) × L (µm)		Inductance (nH)		Resistance (KΩ)		Capacitance (pF)
M1	30 × 0.09	Ls1	5.5	R1	0.5	Cin	1.0
M2	45 × 0.09	Ld2	8.5	R2	5.0	C1	1.0
M3	35 × 0.09	L1	5.0	R3	5.0	C2	1.5
M4	18 × 0.09	Ld3	10.0	R4	0.5	C3	1.5
M5	21 × 0.09	L2	8.5	R5	5.0
M6	35 × 0.09	Ld4	7.1

provides the parameter values for the proposed LNA design.

2.1. Forward Body Baising to Decrease Power Consumption

Due to the cascode architecture of transistors M₁ and M₂, it demands high V_dd supply. This limits the design of LNA to low power consumption. To mitigate this problem, the forward-body bias technique has been implemented in this paper, to operate the proposed UWB LNA at lower V_dd supply of 0.7 V. The transistor M₁ is the key-element in deciding the input impedance matching and noise figure of the complete LNA circuit, and to isolate it from transistor M₂, the forward-body bias technique has been applied only to M₁. This provides more degrees of freedom in finalizing the device dimensions of M₂, to keep transconductance (g_m2) constant and to provide constant current to primary amplifying transistor M₁ [19,20,21]. The threshold voltage V_th of the transistor M₁ can be characterized by:

$$V_{\mathrm{th}}=V_{\mathrm{t}0}+{\gamma }_0(\sqrt{2{\phi }_{\mathrm{f}}-V_{\mathrm{BS}}}-\sqrt{2{\phi }_{\mathrm{f}}})$$

(1)

where V_t0 is the threshold voltage for zero body-to-source voltage (i.e., V_BS =0), γ₀ is a constant that describes body-effect and usually has a value in the range of 0.3–0.4 V and φ_f is the bulk Fermi-potential. It is clear from Equation (1) that applying a forward voltage to body terminal will reduce the threshold voltage of MOS device which in turn helps in reducing the power consumption.

2.2. Frequency Response of S₁₁ and S₂₂

In this section, the proposed LNA design has been analyzed for the frequency response of the input reflection coefficient (S₁₁) and the output reflection coefficient (S₂₂). The approximate expressions for S₁₁ and S₂₂ have been derived here using the small-signal model of the proposed LNA shown in Figure 3, where the effect of the input capacitor (C_in) on the overall input impedance (Z_in) has been neglected.

After using fundamental network theorems, the input impedance of the proposed LNA design can be obtained as:

$$Z_{\mathrm{in}}(\omega )\approx \left(\frac{j\omega L_{\mathrm{s}1}}{1-{\omega }^2{L}_{\mathrm{s}1}{C}_{\mathrm{gs}1}}\right)||Z_{\mathrm{X}}(\omega )=Z_{\mathrm{s}1}(\omega )\Vert Z_{\mathrm{X}}(\omega )$$

(2)

where Z_s1(ω) is impedance of parallel LC tank and Z_X(ω) can be expressed as:

$$Z_{\mathrm{X}}(\omega )=\frac{\left[\begin{array}{l}{r}_{\mathrm{o}1}\left(1+g_{\mathrm{m}2}{r}_{\mathrm{o}2}+j\omega C_{\mathrm{gs}2}\left(r_{\mathrm{o}2}+Z_{\mathrm{Load}1}(\omega )\right)+g_{\mathrm{mb}1}{Z}_{\mathrm{Load}1}(\omega )\right)\\ +r_{\mathrm{o}2}+Z_{\mathrm{Load}1}(\omega )\left(1+g_{\mathrm{mb}1}{r}_{\mathrm{o}1}{g}_{\mathrm{m}2}{r}_{\mathrm{o}2}\right)\end{array}\right]}{\left[1+r_{\mathrm{o}1}\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\right]\left[1+g_{\mathrm{m}2}{r}_{\mathrm{o}2}+j\omega C_{\mathrm{gs}2}\left(r_{\mathrm{o}2}+Z_{\mathrm{Load}1}(\omega )\right)\right]}$$

(3)

where g_m1, g_m2 are transconductances and 1/r_o1, 1/r_o2 are drain-to-source channel conductance of M₁ and M₂ respectively. Back-gate transconductance of M₁ is denoted by g_mb1 and Z_Load1 is the total load impedance connected at the drain of transistor M₂. In Equation (3), assuming r_o1 >> 1 and r_o2 >> 1, then at the input parallel resonance condition set up by L_s1 and C_gs1 and the input impedance Z_in(ω) can be approximated as:

$$Z_{\mathrm{in}}(\omega )\approx \frac{g_{\mathrm{m}2}+j\omega C_{\mathrm{gs}2}+Z_{\mathrm{Load}1}(\omega )g_{\mathrm{mb}1}{g}_{\mathrm{m}2}}{\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\left(g_{\mathrm{m}2}+j\omega C_{\mathrm{gs}2}\right)})$$

(4)

The input reflection coefficient (S₁₁) can be expressed as:

$$S_{11}=\left(Z_{\mathrm{in}}(\omega )-R_{\mathrm{s}}\right)\times {\left(Z_{\mathrm{in}}(\omega )+R_{\mathrm{s}}\right)}^{-1}$$

(5)

In general, S₁₁ ≤ −10 dB is an essential requirement for the entire frequency of interest. From Equations (4) and (5) we have:

$$S_{11}\mathrm{dB}=20{\log }_{10}\sqrt{\frac{{\left(g_{\mathrm{m}2}-R_{\mathrm{s}}{g}_{\mathrm{m}2}\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\right)}^2+{\left|j\omega C_{\mathrm{gs}2}\left(1-R_{\mathrm{s}}\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\right)+Z_{L\mathrm{oad}1}(\omega )g_{\mathrm{mb}1}{g}_{\mathrm{m}2}\right|}^2}{{\left(g_{\mathrm{m}2}+R_{\mathrm{s}}{g}_{\mathrm{m}2}\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\right)}^2+{\left|j\omega C_{\mathrm{gs}2}\left(1+R_{\mathrm{s}}\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)\right)+Z_{\mathrm{Load}1}(\omega )g_{\mathrm{mb}1}{g}_{\mathrm{m}2}\right|}^2}}\le -10 \mathrm{dB}$$

(6)

For the output reflection coefficient (S₂₂), output impedance estimated by looking into the output buffer transistor M₅ is keeping input of the buffer stage as zero. The output impedance of the proposed LNA can be expressed as:

$$\begin{gathered} Z_{\mathrm{out}}(\omega )\approx \frac{1+j\omega Z_4(\omega )C_{\mathrm{gs}5}}{g_{\mathrm{m}5+}j\omega C_{\mathrm{gs}5}}\Vert r_{\mathrm{o}5}\Vert r_{\mathrm{o}6} \\ \approx \frac{1+j\omega Z_4(\omega )C_{\mathrm{gs}5}}{g_{\mathrm{m}5+}j\omega C_{\mathrm{gs}5}} \end{gathered}$$

(7)

where Z_4(ω) is the impedance of the LC tank formed by L_d4 with (C_gd4 + C_gd5). C_gd4 is the gate-to-drain parasitic capacitance of transistor M₄, whereas C_gs5 and g_m5 are the gate-source parasitic capacitance and transconductance of the transistor M₅, respectively. The output reflection coefficient (S₂₂) is given by:

$$S_{22}=\frac{Z_{\mathrm{out}}(\omega )-R_{\mathrm{s}}}{Z_{\mathrm{out}}(\omega )+R_{\mathrm{s}}}$$

(8)

2.3. Noise Figure Analysis

The noise equivalent model of the proposed UWB is shown in Figure 4. The input CG transistor M₁ plays a significant role in overall the noise figure of the LNA while the noise contribution of cascoded transistor M₂ and other successive stages is very small. In Figure 4, the main noise sources included are: the thermal noise due to signal source resistance R_s represented by $\overline{V_{\mathrm{n},R\mathrm{s}}^2}=4kT{R}_{\mathrm{s}}\Delta f$, the gate-induced noise of M₁ represented by $\overline{i_{\mathrm{n},\mathrm{g}1}^2}=4kT\delta g_{\mathrm{g}1}\Delta f$ and the channel-induced thermal noise of M₁ represented by $\overline{i_{\mathrm{n},\mathrm{d}1}^2}=4kT\gamma g_{\mathrm{d}0}\Delta f$ where, k is the Boltzmann constant, T is the temperature in Kelvin, $\Delta f$ is noise bandwidth, δ is the coefficient of gate-induced noise and γ is the coefficient of channel-induced thermal noise. The g_g and g_d0 are given by $g_{\mathrm{g}}=\left({\omega }^2{C}_{\mathrm{gs}1}^2\right)/\left(5g_{\mathrm{d}0}\right)$ and $g_{\mathrm{d}0}=g_{\mathrm{m}1}/\alpha$ respectively, where g_g is the equivalent gate conductance and g_d0 is the zero-bias drain conduction of transistor M₁. Another important noise source of MOS transistor of noise due to the bulk-resistance (R_B) given by $\overline{i_{\mathrm{nb}1}^2}=4kT{R}_{\mathrm{B}}{g}_{\mathrm{mb}1}^2\Delta f$ [22]. This bulk-resistance is distributive in nature, which is very difficult of analyze quantitatively [23]. Furthermore, this noise is also not correlated with the gate induced noise and the channel induced thermal noise. However, the effect of noise due to bulk resistance can be decreased by decreasing the value of g_mb1 and is clear from the expression of g_mb1 given by:

$$g_{\mathrm{mb}1}=\frac{\partial I_{\mathrm{D}}}{\partial V_{\mathrm{BS}}}=g_{\mathrm{m}}·\frac{{\gamma }_0}{2\sqrt{\left|2{\varphi }_f\right|+V_{\mathrm{SB}}}}$$

(9)

This will be possible if we apply a forward voltage to the body terminal of M₁. The correlation coefficient c between induced gate noise ($\overline{i_{\mathrm{n},\mathrm{g}1}^2}$) and channel induced thermal noise ($\overline{i_{\mathrm{n},\mathrm{d}1}^2}$) is also ignored here for simplifying our noise figure analysis. The noise figure of the proposed LNA can be expressed as:

$$NF=1+\frac{\overline{V_{\mathrm{n},\mathrm{out},\mathrm{g}1}^2}+\overline{V_{\mathrm{n},\mathrm{out},\mathrm{d}1}^2}}{\overline{V_{\mathrm{n},\mathrm{out},\mathrm{Rs}}^2}}$$

(10)

where $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{Rs}}^2}$, $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{g}1}^2}$ and $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{d}1}^2}$ are the rms output noise voltages at the drain terminal of M₂ due to $\overline{V_{\mathrm{n},\mathrm{Rs}}^2}$, $\overline{i_{n,g1}^2}$ and $\overline{i_{\mathrm{n},\mathrm{d}1}^2}$, respectively. The $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{R}s}^2}$, $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{g}1}^2}$ and $\overline{V_{\mathrm{n},\mathrm{out},\mathrm{d}1}^2}$ can be expressed as:

$$\overline{V_{\mathrm{n},\mathrm{out},\mathrm{Rs}}^2}=\overline{V_{\mathrm{n},\mathrm{Rs}}^2}\times \frac{g_{\mathrm{m}2}^2{(g_{\mathrm{m}1}+g_{\mathrm{mb}1})}^2{\left|Z_{\mathrm{s}1}(\omega ).Z_{\mathrm{Load}1}(\omega )\right|}^2}{{\left|\begin{array}{l}\left(g_{\mathrm{m}2}+j\omega C_{\mathrm{gs}2}\right)\left(R_{\mathrm{s}}+Z_{\mathrm{s}1}(\omega )+R_{\mathrm{s}}{Z}_{\mathrm{s}1}(\omega )(g_{\mathrm{m}1}+g_{\mathrm{mb}1})\right)\\ +g_{\mathrm{mb}1}{g}_{\mathrm{m}2}{Z}_{\mathrm{Load}1}(\omega )\left(R_{\mathrm{s}}+Z_{\mathrm{s}1}(\omega )\right)\end{array}\right|}^2},$$

(11)

$$\overline{V_{\mathrm{n},\mathrm{out},\mathrm{g}1}^2}=\frac{\alpha \delta {\omega }^2{C}_{\mathrm{gs}1}^2{R}_{\mathrm{s}}}{5g_{\mathrm{m}1}}\times \overline{V_{\mathrm{n},\mathrm{out},\mathrm{Rs}}^2},$$

(12)

and:

$$\overline{V_{\mathrm{n},\mathrm{out},\mathrm{d}1}^2}=\frac{\gamma g_{\mathrm{m}1}}{\alpha R_s{\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)}^2}\left[1+\frac{R_{\mathrm{s}}^2}{{\left|Z_{\mathrm{s}1}(\omega )\right|}^2}\right]\times \overline{V_{\mathrm{n},\mathrm{out},\mathrm{Rs}}^2},$$

(13)

Respectively. Substituting the Equations (11)–(13) in Equation (10), we get the noise figure expression of the proposed UWB LNA as:

$$NF\approx 1+\frac{\alpha \delta {\omega }^2{C}_{\mathrm{gs}1}^2{R}_{\mathrm{s}}}{5g_{\mathrm{m}1}}+\frac{\gamma g_{\mathrm{m}1}}{\alpha R_{\mathrm{s}}{\left(g_{\mathrm{m}1}+g_{\mathrm{mb}1}\right)}^2}\left[1+\frac{R_{\mathrm{s}}^2}{{\left|Z_{\mathrm{s}1}(\omega )\right|}^2}\right]$$

(14)

3. Simulation Results

The proposed LNA is designed and simulated using a 90 nm CMOS process for 3–14 GHz UWB frequency range. The simulation results for S-parameters, noise figure and stability of the proposed FBB UWB LNA are shown in Figure 5. It can be observed from Figure 5a that the proposed LNA UWB input matching with S₁₁has less than −10.6 dB for a frequency range of 3.3 GHz to 13.0 GHz. For this purpose, the transconductance (g_m1) of M₁ was set to 26 mS so that 1/g_m1 ≈ 38.4 Ω, so that the difference from the 50 Ω antenna impedance will be contributed to by the successive stages in the LNA architecture. Due to the CG cascode topology the proposed UWB LNA has a very high reverse isolation (S₁₂) of less than −72.4 dB was achieved throughout the complete UWB range (Figure 5b).

The frequency response for power gain (S₂₁) is shown in Figure 5c and it can be observed from the figure that S₂₁ was greater than 14.2 dB throughout the frequency range of 3.0 GHz to 13.0 GHz. The proposed LNA shows a flat S₂₁ for 15.7 ± 0.5 dB for a frequency range of 4.5 GHz to 13.0 GHz whereas, the output reflection coefficient (S₂₂) was less than −10.8 dB for the 3.0 GHz to 13.0 GHz frequency range (Figure 5d). The noise figure plot of the LNA proposed is shown in Figure 5e and it can be observed from the noise figure versus frequency plot, NF was ranging from 3.0 dB to 4.0 dB for the complete UWB frequency range.

In extension to the parameters discussed earlier for the designing of LNA, another significant parameter to be considered is the Stability factor (K). The absolute stability is an essential requirement for the designed LNA. The stability factor can be expressed as:

$$K=\frac{1-{\left|S_{11}\right|}^2-{\left|S_{22}\right|}^2+{\left|S_{11}{S}_{22}-S_{12}{S}_{21}\right|}^2}{2\left|S_{12}{S}_{21}\right|}>1$$

(15)

$$|\Delta |=\left|S_{11}{S}_{22}-S_{12}{S}_{21}\right|<1$$

(16)

The stability factor (K) should be greater than 1 and the delta (|Δ|) should be less than 1 for an unconditional stability of a system throughout the complete UWB frequency range. Figure 5f shows the stability of the proposed LNA design, where minimum value obtained for K was equal to 330 at 13.0 GHz, which is far greater than unity and the value of delta (|Δ|) at less than 0.12.

To evaluate the effect of feedback body bias technique on noise figure, power gain and input reflection coefficient, the proposed LNA has been simulated with feedback body bias at V_dd supply of 0.7 V and without body biasing at V_dd supply of 0.7 V and 0.9 V. It can be observed from Figure 6 that noise figure, power gain and input matching performance of the proposed LNA was improved with a CG FBB topology with the advantage of requirement of lower V_dd supply.

Another significant parameter to be considered is linearity. The input signal received from the antenna must be linearly amplified by the designed LNA. As LNAs are usually biased at a very low voltage, at this low voltage the linearity survives due to transconductance (g_m) and drain-conductance (g_ds) nonlinearities of the MOS device. Linearity of the proposed LNA has been analyzed graphically in terms of a 1-dB compression point (P1dB), and a third order interface point (IIP3) for which input power was swept from −40 dBm to −10 dBm. It can be observed from Figure 7a that P1dB at the fundamental frequency of 7.0 GHz was −23.0 dBm. A two tone test was performed at a center frequency of 7.0 GHz that gave two tones at f₁ = 6.995 GHz and f₂ = 7.005 GHz with frequency spacing of 10 MHz to find IIP3. Extrapolating the fundamental signal and third order signal outputs and finding out the intersection of the two gives the approximate value of IIP3. It can be observed from Figure 7b that IIP3 of the proposed LNA was −19 dBm.

The designed UWB LNA must be stable against temperature variations. To ensure this, the designed LNA was simulated at nominal, slow-slow (SS), and fast-fast (FF) process corners and at different temperatures of −25°, 25° and 50° Celsius (Figure 8). It can be observed from Figure 8a,b that the feedback of the proposed UWB LNA had a minimum NF that varied from 2.87–3.75 dB to 3.0–4.0 dB at the FF and SS corners respectively, and it varied from 3.1–3.6 dB to 3.3–4.3 dB for −25 °C to −50 °C temperature variations, respectively. Figure 8c,d shows the frequency responses of the input reflection coefficient against process and temperature variations. It can be observed that S₁₁ was less −9.0 dB for 4–13 GHz for all process corners, and was less than 9.1 dB for 5–13 GHz for the temperature range of −25 °C to 50 °C. The power gain frequency response of the proposed LNA is shown in Figure 8e–f, which confirmed the robustness of the proposed UWB LNA against temperature variations.

Results in this study were obtained with theoretical calculations and simulations with standard model files in 90 nm technology. The chip-layout of the proposed LNA is shown in Figure 9, which is designed using the Cadence Layout tool using a 90 nm CMOS process. The dimensions of all the inductors have been calculated using the expression from Mohan et al. (1999) [24]. All the inductors have been designed using metal-1 layer with a turn width and turn spacing of 5 µm and an outer diameter (D_out) of 300 µm for each. As the designed LNA is required to achieve a large bandwidth, the Q-factor of the inductors used in the proposed LNA was very small and ranges from 0.6–1.5. The capacitors C_in and C₁ were designed using metal-insulator-metal using metal-2 and metal-3 layers. The capacitors C₂ and C₃ were designed using a N-type MOS device, whereas the N-diffusion resistors were used to decrease the layout area. The chip layout occupied 1.318 mm² of area. In order to evaluate and compare the overall performance of the proposed UWB LNA with previous work, a figure-of-merit (FOM) has been evaluated. The figure-of-merit can be obtained as [14,22,23]:

$$FOM[GHz/mW]=\frac{{\left|S_{21}\right|}_{abs}\times B{W}_{GHz}}{(F-1)\times P_{mW}}$$

(17)

where |S₂₁|_abs is the absolute value of S₂₁, BW is the 3-dB bandwidth measured in GHz, F is noise factor and P_mW is the power consumption in mW.

The simulation results of the proposed UWB LNA were compared with the previous published work from a wide literature in

Table 2. Comparison of the simulation results of proposed LNA with previously published work.

Ref. & Year	Topology	Tech (nm)	Vdd (V)	BW (GHz)	S11 (dB)	S21 (dB)	S22 (dB)	NF (dB)	IIP3 (dBm)	Power (mW)	FOM1
This work S	CG Feedback Body Bias	90	0.7	3.3–13.0	<−10.6	14.7 ± 0.5 @ 4.5–13.0 GHz	<−10.8	3.0 ± 0.5	−19 @ 7.0 GHz	5.2	8.54
[10], 2010 m	CS-resistive feedback	90	1.2	3.1–10.6	<−14.1	10.4 ± 0.2 *, 10.68 $	-	3.075 ± 0.155	+4	21.6	-
[28], 2011 m	Current-reused	90	1.2	2.6–10.2	<−9	12.5 $		3–7	-	7.2	-
[16], 2008 m	CS-resistive feedback	90	1.2	0.2–9	<−10	10	--	4.2 #	−8	20	-
[29], 2013 S	CS Forward Body Bias	130	0.6	3.1–10.6	≤−5	21 $	≤−10.6	1.0–3.9	+4.56 @ 6.0 GHz	4.1	-
[30], 2015 m	CS Forward Body Bias	130	1.0	3.0–10.0	≤−11.4	12.1 $	≤11.7	3.04–3.48	−6.6 @ 6.0 GHz	13.0	-
[17], 2015 S	Noise cancelling	130	1.3	2.3–9.37 a	≤−8	10.3 $	≤−8	3.68–9.2	−4 @ 4.5 GHz	9.97	5.71
[27], 2013 m	CS Resistive Termination	180	1.0	3–5.6 a	≤−9 @ 3–11 GHz	9 a	≤−8 @ 3–7.5 GHz	4.6–5.3 a	+2 @ 5.3 GHz	9.0	-
[22], 2015 L	CS Forward Body Bias	180	1.5	3.1–10.6	<−10.6	14.4 ± 1.4	<−12.1	2.2–3.2	−6.0	9.0	-
[25], 2013 S	Common Gate	180	1.2	3.1–10.6	<−5.5	12.75 ± 0.83	<−7	2.5–3.7	−8.2 @ 5 GHz	12.14	12.58
[26], 2018 S	Noise cancelling	180	1.8	3–12	<−10	19.24–20.24	-	1.72–1.99		23.23	7.1
[31], 2008 S	Forward Body Bias	180	0.6	5	<−8	14.1	-	3.65	−17.1	1.68	-

^S Simulation results, ^m measurement results, ^L Layout data, ^a 3dB BW, * average value, ^$ max value, ^# minimum.

. Comparison mainly focused on noise figure (NF), input reflection coefficient (S₁₁), output reflection coefficient (S₂₂), power gain (S₂₁) and power consumption for 3.1–10.6 GHz UWB frequency. The LNAs implemented in References [8,23,25] uses common-source resistive feedback topology for wideband input matching, but the noise figure was in 3.0–5.3 dB range and consumed more power as compared to the LNA proposed in this paper. A noise cancelling technique was utilized in References [14,23] with a high power consumption of 9.97 mW and 23.23 mW respectively. CS with an FBB technique was used in References [20,26,27], however, the power consumed by the LNA proposed in References [20,26] was greater than 9 mW and 13.0 mW, respectively. Due to the use of the small power supply LNA proposed in References [27] it consumed less power but had S₁₁ of ≤−5 dB. It can be observed from Table 2 that the proposed LNA design had better overall performance in terms of the noise figure, S₁₁, S₂₁, S₂₂, bandwidth and the power consumption.

4. Conclusions

A low power UWB LNA was proposed in this paper for the UWB frequency range. The proposed LNA was designed and simulated using a 90nm CMOS process and implemented using common-gate cascade topology, with a feedback body biasing technique. Drain to body feedback was implemented using a resistor of 0.5 KΩ between the body terminal of M₁ and the drain of M₂ to alter the noise figure and power consumption. Detailed S₁₁, S₂₂ and noise figure analysis was also provided to support the simulation results of the proposed LNA. The proposed LNA achieved a flat power gain (S₂₁) of 14.7 ± 0.5 dB for 4.5–13.0 GHz and noise figure of 3.0–4.0 dB. An output reflection coefficient of <−10.8 dB was achieved throughout the complete UWB range with a very small power consumption of 5.2 mW, including the output buffer stage and has a chip-layout area of 1.318 mm²_, which makes the proposed LNA design a good candidate for low power and low noise wireless applications.