Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion
Abstract
:1. Introduction
2. Asynchronous Quantization
3. System Overview
3.1. Reconfigurable Analog Mixed-Signal Platform
3.2. Asynchronous Data Converter Design
3.2.1. Successive-Approximation Register
3.2.2. Comparator
3.2.3. Time-to-Digital Converter
4. Asynchronous Sampling Implementation
4.1. Extrema Sampling
4.2. RAMP Triggering Implementation
5. System Implementation and Example Applications
5.1. Power Consumption
5.2. Voice Recording
5.3. Electromyography
5.4. Electrocardiogram
6. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Extrema Sampling Ramp Implementation | 4.95 W |
SAR ADC Static Power Consumption | 14.75 nW |
SAR ADC Energy/Conversion | 47.4 nJ |
SAR ADC Resolution | 10 bits |
TDC Power Consumption | 1.01 W @ 1.15 kHz |
TDC Resolution | 10 bits |
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Kelly, B.M.; DiLello, A.T.; Graham, D.W. Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion. J. Low Power Electron. Appl. 2019, 9, 25. https://doi.org/10.3390/jlpea9030025
Kelly BM, DiLello AT, Graham DW. Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion. Journal of Low Power Electronics and Applications. 2019; 9(3):25. https://doi.org/10.3390/jlpea9030025
Chicago/Turabian StyleKelly, Brandon M., Alexander T. DiLello, and David W. Graham. 2019. "Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion" Journal of Low Power Electronics and Applications 9, no. 3: 25. https://doi.org/10.3390/jlpea9030025
APA StyleKelly, B. M., DiLello, A. T., & Graham, D. W. (2019). Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion. Journal of Low Power Electronics and Applications, 9(3), 25. https://doi.org/10.3390/jlpea9030025