3.1. RO-Based TRNG Randomness-Degradation Mechanism
Both radiated and conducted interference can suppress the jitter of ROs and degenerate the randomness of the RO-based TRNG. As shown in
Figure 8, the uncertain logic value can be sampled when the oscillating signal of the RO jitters. Otherwise, the D flip-flops the certain logic, which means that the output is not random. With the RO array, the jitter range covers the whole sampling period [
1]. Good-quality random bitstreams can be generated by the TRNG. When the RO-based TRNG was disturbed by intentional EMI, the ROs were locked, and the jitter was suppressed [
7], as shown in
Figure 8d. Therefore, the randomness of the output bitstream deteriorated. The reason for this disastrous result was that the injection-locking condition of the RO was independent of the stage and only related to the gate-delay. With the same CMOS process, the gate-delays were consistent, and all ROs had to be synchronously locked once locking occurred. Even with the existing process deviation, it was overcome by EMI to achieve synchronization, according to
Section 2.2.
To prove the correctness of the above explanation, a specific RO-based TRNG circuit was built using an SMIC-130 nm process library and was simulated by HSPICE in which the array consisted of two ROs of 7, 9, 11, and 13 stages, respectively. To simulate the noise environment in the actual circuit, a −28 dBm Gaussian white-noise voltage was generated in MATLAB, which was superimposed onto the DC power supply of the circuit. Noise voltage was essential to cause the oscillating signal to jitter.
The simulated oscillating parameters are shown in
Table 2. The free-oscillating frequencies of the ROs were 3166, 2476, 2034, and 1726 MHz, and the average gate-delay was about 22.56, 22.44, 22.35, and 22.29 ps, respectively, with a slight difference. According to Equation (
1), the 22,550 MHz sinusoidal EMI wave could overcome the delay difference and lock all ROs where the average gate-delays were equal to 22.17 ps and oscillating frequencies were fixed to the corresponding values. The standard deviation of the period distribution, which can represent jitter strength, was calculated. Under EMI conditions of 0.35 V and 22,550 MHz, all ROs were locked, and the jitters were 1.14, 1.14, 1.15, and 1.15 ps. Compared with the no-EMI condition in
Table 2, jitters were suppressed by 60%, 64%, 67%, and 70%. This phenomenon is also represented by the period-distribution histograms in
Figure 9b,d.
Figure 9a,c represents the bitstream output by the TRNG. Black and white pixels are used to represent zero and one, respectively. The binary images can be obtained by scanning the bitstream from left to right and from top to bottom. In the no-EMI case, the binary image was arranged in a disordered manner, which represents a certain degree of randomness. When all ROs were locked by the EMI, the binary image tended to be completely black, and the occurrence probability of zero and one was not uniform. It could not even pass the first test of the NIST Statistical Test Suite [
3], which detects whether zero and one appear the same number of times, called the monobit test.
3.2. Immunity Modeling and Gate-Delay Differentiation
To solve the problem of the randomness of the RO-based TRNG deteriorating sharply due to synchronous locking, the design method of gate-delay differentiation was proposed in this paper: the average gate-delay of each RO in the TRNG was intentionally set to be different so that the locking regions of ROs were staggered from each other. This avoided all the ROs being locked in some EMI situations.
An array with four ROs was considered, composed of inverters with different gate-delays. According to the conclusion of
Section 2.1, each RO had a conical locking region. Due to the difference in gate-delay, the conical locking regions of the four ROs were staggered, as shown in
Figure 10a.
The scattered distribution was beneficial to the EMI immunity of the RO-based TRNG:
To lock all four types of ROs, available and can only be selected in the red area, which is the overlapping area of the four conical locking regions. The required had to be greater than , and the selection of was also very harsh;
To lock three types of ROs, the available and can only be selected in the yellow area. This required that > , and the available selection range of was also small;
To lock two types of ROs, and can only be selected from the gray area. In such a case, it required > , and the selection range of was large. However, randomness did not become much worse because of only two types of ROs being locked;
To lock one type of RO, and can only be selected from the light green area, which is easy to achieve. The influence of one type of RO locked on randomness can be ignored.
In a traditional EM attack on RO-based TRNG, the gate-delays of four types of RO were the same, and there was no staggering between conical locking regions, as shown in
Figure 10b. It was easy to realize synchronous locking for all ROs, which was destructive to the RO-based TRNG.
In
Figure 10, we considered the locking region of the frequency. Similarly, average gate-delay
, which can be converted from
, also had a conical locking region. It was clearer and more appropriate to analyze the locking situation of the RO array, because the analytical method of
discarded the independent factor of the RO stage, which made it easier for us to see the essence of locking. In the following simulation and test, we used the
-type conical locking region to illustrate this.
To improve immunity, the gate-delay difference of each RO must be increased. The ideal situation is only one type of RO locking under any interference condition. To differentiate gate-delays, changing the channel width of transistors in the inverter, the load of each inverter, and the interconnect length are feasible because of the simplicity of implementation and low cost. Meanwhile, we can flexibly choose the implementation according to the situation: for the RO-based TRNG on application-specific integrated circuits (ASICs), changing the channel width of transistors is the first choice; for the RO-based TRNG on an FPGA, the load of each inverter and the interconnect length are appropriate. For a specific CMOS process, the response of the oscillating RO frequency to different capacitor loads and different transistor sizes can be simulated in advance. According to the response data, suitable capacitor loads and transistor size parameters can be selected and assigned for the ROs. Increasing the number of ROs with different average gate-delays matters, so that there is a smaller proportion of ROs in the locked state.
Therefore, we verified the design method of gate-delay differentiation with HSPICE using the RO-based TRNG circuit in
Section 3.1. Two implementation strategies for differentiating gate-delay are shown in
Table 3: Case 1 is changing the inverter size, and Case 2 is changing the capacitor load of the inverter. Although increasing the size of the inverter and capacitance load slowed down the circuit and caused additional power consumption, these shortcomings were tolerable compared with the goal of improving immunity.
For Case 1, the inverters composed of 7-, 9-, 11-, and 13-stage ROs were designed with the sizes in
Table 3, which led to different gate-delays. The simulation results are shown in
Figure 11. In
Figure 11a, the conical locking regions are shown to be staggered. Only when the
>
V could all ROs in the array be locked. To observe the output bitstream of RO-based TRNG, some representative interferences were selected to realize the locking of 0, 1, 2, 3, and 4 types of RO, respectively; see
Table 4 for the interference and jitter information. The jitters of locked ROs, which are marked as red, were much lower than those of unlocked ROs.
Interference seemed to result in two kinds of consequences: one was suppressing jitter, as we know, and the other was intensifying it. In the unlocked state, as shown in the black data, the larger the was, the more severe the jitter was; in the locked state, as shown in the red data, the larger was, the more strongly the jitter was suppressed.
Bitstream binary images were obtained, as shown in
Figure 11(b1–b5). When there were three or more types of ROs locked, output bitstreams showed strong regularity, and the randomness of the RO-based TRNG was greatly reduced. However, the required
was also large. When only one or two types of RO were locked, the randomness hardly changed. This agreed well with our theoretical analysis. To obtain the quantization results of the randomness, the bitstream was tested in the NIST suite. When three or four types of ROs were locked, the
p-value was far less than 0.01, which shows that the randomness was seriously damaged.
For Case 2, each inverter of the 7-, 9-, 11-, and 13-stage RO was loaded with 0, 0.13, 0.28, and 0.44 fF capacitors, respectively. The simulation results are shown in
Figure 12, which were very similar to those of Case 1. Detailed jitter and interference information is shown in
Table 5. Adding different capacitor loads can also stagger the locking regions of the ROs to improve electromagnetic immunity.
To prove that the design method of gate-delay differentiation to improve the immunity did not depend on the CMOS process, the RO-based TRNG built with SMIC 65-nm was simulated by HSPICE. The circuit setting was the same as Case 2 in the above experiment. To simulate such a situation, the corresponding average gate-delays of ROs loaded with 0, 0.037, 0.074, and 0.111 fF capacitors were 11.90, 12.25, 12.59, and 12.94 ps. According to Equation (
1), these ROs could be locked by the interference of 41,700, 40,300, 39,300, and 38,300 MHz, respectively. This suggested that if the inverters in TRNG were loaded with the same capacitors as above, all the ROs would be locked synchronously, and the randomness deteriorated, as shown in
Figure 13(c1–c4). If each inverter of the 7-, 9-, 11-, and 13-stage RO was loaded with 0, 0.037, 0.074, and 0.111 fF capacitors, respectively, the locking regions were staggered, as shown in
Figure 13a. The same interference conditions above could not lock all the ROs synchronously, and the randomness of the bitstream did not become worse, which can be seen in
Figure 13(b1–b4). The results proved that the improvement of immunity was independent of the CMOS process.