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Article

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Cheongju 28644, Korea
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(12), 1395; https://doi.org/10.3390/electronics10121395
Submission received: 6 May 2021 / Revised: 8 June 2021 / Accepted: 9 June 2021 / Published: 10 June 2021
(This article belongs to the Section Microelectronics)

Abstract

:
Mechanical stress is demonstrated in the fabrication process of nanosheet FETs. In particular, unwanted mechanical instability stemming from gravity during channel-release is covered in detail by aid of 3-D simulations. The simulation results show the physical weakness of suspended nanosheets and the impact of nanosheet thickness. Inner spacer engineering based on geometry and elastic property are suggested for better mechanical stability. The formation of wide contact area between inner spacer and nanosheet, as well as applying rigid spacer dielectric material, are preferred.

1. Introduction

As logic technology continues scaling for smaller chip size, better output performance, and low static power consumption, channel geometry in field-effect transistors (FETs) have evolved from planar to nanowire structures, as is well known. Gate-all-around (GAA) field-effect transistors (FETs) show better gate controllability and short-channel effects (SCEs) suppression than FinFETs do [1]. However, due to the limitation of nanowire perimeter in GAA FETs, vertically stacked structures comprising multiple silicon nanowires or nanosheets have been preferred for wider effective channel width [2,3,4]. Compared with FinFETs, stacked GAAs require formation of channels suspended from substrate. Generally, fabrication methods for suspended channels have been categorized in two ways. The first approach is to use a sacrificial layer deposited on a substrate such as a dielectric (e.g., SiO2) or inorganic layer (e.g., SixGe1−x) [5,6,7]. Silicon channels can be suspended from the substrate when the sacrificial layer is selectively wet-etched. The second approach is to use reactive dry etching, called the ‘Bosch process’, to form stacked channels [2,8]. Sequentially performed isotropic dry etching, thermal oxidation, and removal of sacrificial oxide are used to form suspended channels.
However, both the above-mentioned approaches to form suspended channels encountered a mechanical instability, known as stiction, which is associated with the capillary force of chemicals during wet-etching [9]. Fortunately, this concern has been avoided by improved dry etching and supercritical drying [10,11,12,13]. The other concern during the suspension of channels is vertical stress associated with gravity. Nanosheet FETs (NS FETs), due to their wider perimeter and larger volume, have much heavier channel mass than that of nanowire FETs. Even though stiction can be avoided by aid of the several knobs mentioned above, improvements against gravity have been modest so far. Most research about NS FETs has focused on improvements of electrical performances in terms of DC or AC [14,15]. In this context, discussions on mechanical stability and implementing improvements seem timely in the development of NS FETs.
In this work, for the first time, the impact of gravity during fabrication processing of NS FETs is demonstrated. In particular, we discuss the mechanical displacement of nanosheets when channels are released. The results are quantitively analyzed by aid of a 3-D numerical simulator. Based on the results, fabrication guidelines in terms of inner spacer engineering are suggested to improve mechanical stability of NS FETs.

2. Materials and Methods

Figure 1 provides a summary of the fabrication process of NS FETs. Si/SixGe1−x stacks are iteratively deposited on a substrate by epitaxial growth. Then, a dummy gate composed of poly-Si is deposited as a hard mask. Thereafter, Si/SixGe1−x stacks are dry etched for source/drain (S/D) formation. SixGe1−x indent etching, inner spacer deposition, and heavily doped silicon formation at the S/D are sequentially performed. There is no critical concern until the step shown in Figure 1d, but mechanical failure occurs among the nanosheets during channel-release, as shown in Figure 1e. In this context, our simulation studies were performed under the situation shown in Figure 1e. Summary of device fabrication processing with 3-dimensional graphics has been reported in previous works, in detail [16,17].
Figure 2 provides a schematic diagram of an NS FET for mechanical simulation. The device has three suspended nanosheet channels; the gate length (LG), channel width (WCH), and channel-to-channel vertical space (VSPC) are 12 nm, 30 nm, and 10 nm, respectively. The three-dimensional (3-D) numerical simulator COMSOL was utilized with the solid mechanics module. The mesh size was defined as 2 nm. Dominant material parameters to determine the simulation result were Young’s modulus, Poisson ratio, and density. All simulations were performed under a steady-state condition. Moreover, the substrate, raised S/D, and its hard mask were supposed to be free from mechanical stress to observe the mechanical behavior in nanosheets. Gravity, which is the most important parameter in this simulation, was applied in all structures. Detailed device geometry and material properties are summarized in Table 1.

3. Results

Figure 3 shows the simulation results of mechanical stress when the nanosheets were released. As there is no filling material underneath the nanosheets, mechanical displacement was concentrated in the middle of each nanosheet. In addition, in terms of location of the spot, there was no difference between the nanosheet at the first floor and that of the third floor. Considering that the process to form suspended multiple nanosheets (or nanowires) is very difficult to control due to adhesion between nanosheets [14], this result would be informative during device fabrication. Figure 4 shows the simulation results for various nanosheet thicknesses (TNS). Considering stacked nanosheets, more than five stories are preferred for better performance of logic, and channel thickness should be thinner under the same S/D height (HSD) [18]. However, the mechanical displacement abruptly increased as TNS was reduced to less than 3 nm. According to the material mechanics, the section moment of inertia (I) is an important factor for flexural rigidity. The flexural rigidity (D) and I can be described by,
I = 1 12 W CH T CH 3
D = E I
where E is Young’s modulus [19]. It was found that mechanical deformation could be reduced when TNS is thick, because of increased D. In the case of an n-type NS FET, a few nanometers of inner spacer is deposited between the nanosheets. Currently, most reports related with inner spacer have been performed in terms of electrical performance [20,21,22,23,24]. However, in view of the mechanical stress, the inner spacer plays a large role in the support of each nanosheet.
As inner spacer thickness (TINN) changes from 3 nm to 1 nm, the mechanical deformation increased 1.8 times due to increased vacuum area underneath each nanosheets (Figure 5). It should be noted that typical shape of inner spacer is not rectangular but close to that of a ribbon because of the process limitations [14].
Figure 6 shows that the magnitude of mechanical displacement depends on the contact area between the inner spacer and the nanosheet. Compared with the rectangular shape (contact area = 3 nm), the semicircle shape inner spacer (contact area = 0 nm) shows two times higher stress due to lack of vertical support. Hence, the rectangular shape of inner spacer is preferred despite the difficult fabrication process. Alternatively, inner space engineering can be performed via material engineering, as shown in Figure 7. As the Young’s modulus of the inner spacer increases, mechanical strength of the dielectric layer becomes rigid and strong; hence, the stability of suspended nanosheets can be improved.

4. Conclusions

Mechanical stability stemming from gravity was demonstrated in the fabrication process of nanosheet FETs (NS FETs) during channel-release. Mechanical displacement was concentrated in the middle of each nanosheet, and depended on the nanosheet thickness (TNS), inner spacer geometry, and materials. As a result, increasing the inner spacer thickness and contact area at the inner spacer/nanosheet interface is preferred. Moreover, applying an inner spacer with high Young’s modulus can be a possible alternative for better mechanical stability.

Author Contributions

J.-Y.P. conceived this project and designed all the experiments. K.-S.L. conducted all the simulations including mechanical displacement, and wrote this paper. Both authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the National Research Foundation (NRF) of Korea grant funded by the Korea government (MSIT) (No. 2020M3H2A1076786 and 2021R1F1A1049456). The EDA tool was supported by the IC Design Education Center (IDEC), Republic of Korea. K.-S. Lee and J.-Y Park are with the School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Cheongju, Chungbuk 28644, Republic of Korea.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Summary of fabrication process flow of nanosheet FETs (NMOS). (a) Si/SixGe1−x stacking by iterative epitaxial growth. (b) Dummy poly-Si gate patterning and source/drain dry etching. (c) Si/SixGe1−x in-dent etching and inner spacer deposition. (d) Epitaxial growth for source and drain. (e) Replacement of poly-Si gate and channel-release by selective dry etching. (f) Gate stack formation including high-k, dipole engineering, and work function metals.
Figure 1. Summary of fabrication process flow of nanosheet FETs (NMOS). (a) Si/SixGe1−x stacking by iterative epitaxial growth. (b) Dummy poly-Si gate patterning and source/drain dry etching. (c) Si/SixGe1−x in-dent etching and inner spacer deposition. (d) Epitaxial growth for source and drain. (e) Replacement of poly-Si gate and channel-release by selective dry etching. (f) Gate stack formation including high-k, dipole engineering, and work function metals.
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Figure 2. (a) Schematic geometry of Figure 1e for mechanical simulations. (b) Cross-sectional view of structure along x-direction. (c) Cross-sectional view of structure along the y-direction.
Figure 2. (a) Schematic geometry of Figure 1e for mechanical simulations. (b) Cross-sectional view of structure along x-direction. (c) Cross-sectional view of structure along the y-direction.
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Figure 3. (a) Simulated mechanical displacement profiles from Figure 1e and Figure 2. (b) Extracted mechanical displacement along the x–x’ direction.
Figure 3. (a) Simulated mechanical displacement profiles from Figure 1e and Figure 2. (b) Extracted mechanical displacement along the x–x’ direction.
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Figure 4. Extracted mechanical displacement with various channel thicknesses.
Figure 4. Extracted mechanical displacement with various channel thicknesses.
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Figure 5. Extracted mechanical displacement with inner spacer thickness (TINN).
Figure 5. Extracted mechanical displacement with inner spacer thickness (TINN).
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Figure 6. Extracted mechanical displacement with inner space geometry. TINN was fixed at 3 nm.
Figure 6. Extracted mechanical displacement with inner space geometry. TINN was fixed at 3 nm.
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Figure 7. Mechanical displacement with various possible inner spacer materials.
Figure 7. Mechanical displacement with various possible inner spacer materials.
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Table 1. Parameters for Mechanical Simulation.
Table 1. Parameters for Mechanical Simulation.
ParameterValueMaterial
Gate Length, LG12 nmVacuum
Channel Width, WCH30 nmSi
Channel-to-Channel Vertical Space, VSPC10 nmVacuum
Nanosheet Thickness, TNS5 nmSi
Inner Spacer Thickness, TINN3 nmSi3N4
Source/Drain Length, LSD12 nmSi
Source/Drain Height, HSD 45 nmSi
Substrate100 nm× 100 nm× 30 nmSi
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MDPI and ACS Style

Lee, K.-S.; Park, J.-Y. Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics 2021, 10, 1395. https://doi.org/10.3390/electronics10121395

AMA Style

Lee K-S, Park J-Y. Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics. 2021; 10(12):1395. https://doi.org/10.3390/electronics10121395

Chicago/Turabian Style

Lee, Khwang-Sun, and Jun-Young Park. 2021. "Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs" Electronics 10, no. 12: 1395. https://doi.org/10.3390/electronics10121395

APA Style

Lee, K. -S., & Park, J. -Y. (2021). Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs. Electronics, 10(12), 1395. https://doi.org/10.3390/electronics10121395

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