High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

Round 1

Reviewer 1 Report

For the use in IoT system, the author proposed an efficient reconfiguration method utlizing dynamic partial reconfiguration features and LZ4 data compression algorithms.

Through the experiment, the proposed method shows the better preformance then the existing one.

But need some English editing for the following parts;

1) p.2, the 4th line from top: .... such as IoT systems since IoT systems have ... --> .... such as IoT systems since they have ...

2) p.2, The 9th line from top: DPR is one the vital features in FPGAs ,,,,, --> DPR is one of the vital features in FPGAs ,,,,, 

3) p.8, The last pharagraph: The power adaptive technique switches between the three algorithms according.....

         --> The power adaptive technique switches among the three algorithms according.....

4) p.8, The last pharagraph: The proposed power adaptive technique switches encryption algorithms according to the  system power level. --> It woud be better if clearly describing "the syetem power level" as "the IoT end devise system power level".

5) p.9, The 1st line in section 3.1: .... in the design led to portioning  .... --> .... in the design led to partioning...

6) p.9, the 3rd to 2nd line from the bottom: The taps are either exclusive OR or ............ in the feedback path[24].

     --> incomplete sentence.

7) p.10, Fig.6: confusing between connected and crossing over lines.

8) p.10, the 1st line from the top: Flip Flops' role in the configuration is acting as shift registers so they can form sequences that have pseudo random values. -->  Flip Flops' role in the configuration is acting as shift registers so they can generate pseudo random sequences.

9) p.10, the 3rd and 5th line from the top: seems  [24] should be [25].

10) p.10, the 1st sentence of the 3rd paragraph: -->  incomplete sentence

11) p.12, the 1st sentence of the 2nd paragraph: In the design proposed, the use of the compression algorithms to compress the bitstreams file ..... from the memory therefore, the reconfiguration time will be decreased. 

   --> In the proposed design, the use of the compression algorithms to compress the bitstreams file ..... from the memory. Therefore the reconfiguration time will be decreased.

12)  p. 16, Figure 12: the legend for the graph is required.

13)  Careful English proof reading and gramma checking are required  

Author Response

Thank you so much for the detailed review. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The use of compression for saving resources and time in FPGAs partial reconfiguration is not a novelty, but the proposal of using LZ4 is interesting. The selected application selected as proof of concept is also of interest because of the increase of attention over lightweight cryptography. Some comments/suggestions follow:

• It will be interesting to include also a comparison with the procedure in [1] in order to show clearly the advantages of using compression algorithms such as LZ4 to trivial compression.
• There are some typos and grammatical errors, the manuscript should be thoroughly revised.

 

References:

[1] B. Sellers, J. Heiner, M. Wirthlin and J. Kalb, "Bitstream compression through frame removal and partial reconfiguration," 2009 International Conference on Field Programmable Logic and Applications, 2009, pp. 476-480, doi: 10.1109/FPL.2009.5272502.

Author Response

Thank you so much for the detailed review. Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Authors have addressed my comments and suggestions. The text requires some minor grammatical corrections.

Author Response

Thank you very much for the review. Please Check the attacahment.

Author Response File: Author Response.pdf