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Review
Peer-Review Record

Low-Power Ultra-Small Edge AI Accelerators for Image Recognition with Convolution Neural Networks: Analysis and Future Directions

Electronics 2021, 10(17), 2048; https://doi.org/10.3390/electronics10172048
by Weison Lin *, Adewale Adetomi and Tughrul Arslan
Reviewer 1:
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Electronics 2021, 10(17), 2048; https://doi.org/10.3390/electronics10172048
Submission received: 30 June 2021 / Revised: 9 August 2021 / Accepted: 19 August 2021 / Published: 25 August 2021

Round 1

Reviewer 1 Report

I am grateful for the invitation for reviewing this article. This paper focuses on surveying power-sensitive edge AI devices by comparing three features such as computation ability, power consumption, and area size, which would help designers in choosing or designing a suitable architecture. This work contributes significantly to the field of Edge AI Accelerators. Therefore, this paper deserves to be considered for publication. However, several minor revisions should be further addressed.

First, it is strange to put the references’ number after the punctuation. I recommend putting it before the punctuation mark.

Second, there are some format errors and grammatical errors in this article, please check carefully.

Third, are there any limitations in your work? This work only discusses the three key features, why? the reason should be further addressed.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

This work have academic reference significance for researchers and designers in the related fields. The paper is scientifically written with relatively rich information. I have the comments as follows: 
1. The motivation of this study needs to be further highlighted in the introduction.
2. Reference citation marks should be written before the punctuation marks at the end of the sentence. For example, the following serial number marks are wrong: [1], [2], [3], [4], [5], etc. References should be written in the form of Ref. [1] instead of [1] as the subject.
3.  In Table 5, should "FPCA 2014" be "FPGA"?
4. In line 28, You say "As shown in Table 2-7, it can be noticed that FPGA and application-specific integrated circuits (ASIC) are the most used approaches to implement edge AI devices", but one can not see this conclusion directly from Table 2-7.  There needs to be further specific instructions. 
5. Regarding "3.4. Implementation technology", the explanation is not comprehensive enough, and it is recommended to expand appropriately.
6. In Section 4, the introduction on the "design direction" is not detailed enough, and this part of the content needs to be appropriately strengthened and expanded.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

This paper presented a survey of edge AI accelerators and CGRA accelerators that are applied in image recognition.

 

The paper is well written and structured.

I don't think all the hardware possibilities have been touched. For example, can't BeableBone AI  used for image recognition?  (It have specialized hardware resources for AI)

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The authors have made a great work addressing all my concerns. I recommend the paper to be accepted.

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