A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC

Bai, Suping; Wan, Zhi; Wan, Peiyuan; Zhang, Hongda; Ma, Yongkuo; Zhang, Xiaoyu; Liu, Xu; Chen, Zhijie

doi:10.3390/electronics10212650

Open AccessArticle

A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC

by

Suping Bai

^1,*,

Zhi Wan

¹

,

Peiyuan Wan

²,

Hongda Zhang

²,

Yongkuo Ma

²,

Xiaoyu Zhang

²,

Xu Liu

²

and

Zhijie Chen

²

¹

The School of Electro-Optical Engineering, Changchun University of Science and Technology, Changchun 130022, China

²

Faculty of Information Technology, College of Microelectronics, Beijing University of Technology, Beijing 100124, China

^*

Author to whom correspondence should be addressed.

Electronics 2021, 10(21), 2650; https://doi.org/10.3390/electronics10212650

Submission received: 26 September 2021 / Revised: 26 October 2021 / Accepted: 27 October 2021 / Published: 29 October 2021

(This article belongs to the Collection Analog IC Design—Analog and RF Interface for Electronic Systems)

Download

Browse Figures

Versions Notes

Abstract

This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm². The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.

Keywords: analog-to-digital converter (ADC); hybrid-domain quantization; high speed; voltage-to-time converter (VTC); time-to-digital converter (TDC)

Share and Cite

MDPI and ACS Style

Bai, S.; Wan, Z.; Wan, P.; Zhang, H.; Ma, Y.; Zhang, X.; Liu, X.; Chen, Z. A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC. Electronics 2021, 10, 2650. https://doi.org/10.3390/electronics10212650

AMA Style

Bai S, Wan Z, Wan P, Zhang H, Ma Y, Zhang X, Liu X, Chen Z. A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC. Electronics. 2021; 10(21):2650. https://doi.org/10.3390/electronics10212650

Chicago/Turabian Style

Bai, Suping, Zhi Wan, Peiyuan Wan, Hongda Zhang, Yongkuo Ma, Xiaoyu Zhang, Xu Liu, and Zhijie Chen. 2021. "A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC" Electronics 10, no. 21: 2650. https://doi.org/10.3390/electronics10212650

APA Style

Bai, S., Wan, Z., Wan, P., Zhang, H., Ma, Y., Zhang, X., Liu, X., & Chen, Z. (2021). A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC. Electronics, 10(21), 2650. https://doi.org/10.3390/electronics10212650

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Menu

A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC

Abstract

Share and Cite

Article Metrics

Article Access Statistics

Further Information

Guidelines

MDPI Initiatives

Follow MDPI